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raw | patch | inline | side by side (parent: f762808)
raw | patch | inline | side by side (parent: f762808)
author | Nikhil Devshatwar <nikhil.nd@ti.com> | |
Thu, 4 Jul 2019 08:48:54 +0000 (14:18 +0530) | ||
committer | Andreas Dannenberg <dannenberg@ti.com> | |
Mon, 8 Jul 2019 14:22:07 +0000 (09:22 -0500) |
Channel allocation for MAIN_0_R5_2 is done such that
Main NAV UDMA Tx and Rx channels start with different offsets.
This cannot be used for block copy carveout since the Tx and Rx channels
are not overlapping at start or end of the range.
Fix this by allocating more channels to MAIN_0_R5_0 so that the
MAIN_0_R5_2 channel ranges start at same value.
Autogen table takes care of the corresponding ring allocations as well.
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
Main NAV UDMA Tx and Rx channels start with different offsets.
This cannot be used for block copy carveout since the Tx and Rx channels
are not overlapping at start or end of the range.
Fix this by allocating more channels to MAIN_0_R5_0 so that the
MAIN_0_R5_2 channel ranges start at same value.
Autogen table takes care of the corresponding ring allocations as well.
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
soc/j721e/evm/rm-cfg.c | patch | blob | history | |
soc/j721e/evm/sysfw_img_cfg.h | patch | blob | history |
diff --git a/soc/j721e/evm/rm-cfg.c b/soc/j721e/evm/rm-cfg.c
index 4b93956812ffe56bacc1c0aeb56993ade939fe9f..5d69018e6b98f0b2ce686930f8700b312d021109 100644 (file)
--- a/soc/j721e/evm/rm-cfg.c
+++ b/soc/j721e/evm/rm-cfg.c
/* AUTO GENERATED ENTRIES BELOW */
-
/* Main Nav UHC TX Channel */
{
.start_resource = 0,
},
{
.start_resource = 118,
- .num_resource = 5,
+ .num_resource = 7,
.type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
RESASG_SUBTYPE_UDMAP_RX_CHAN),
.host_id = HOST_ID_MAIN_0_R5_0,
},
{
- .start_resource = 123,
- .num_resource = 16,
+ .start_resource = 125,
+ .num_resource = 15,
.type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
RESASG_SUBTYPE_UDMAP_RX_CHAN),
.host_id = HOST_ID_MAIN_0_R5_2,
},
- {
- .start_resource = 139,
- .num_resource = 1,
- .type = RESASG_UTYPE (J721E_DEV_NAVSS0_UDMAP_0,
- RESASG_SUBTYPE_UDMAP_RX_CHAN),
- .host_id = HOST_ID_ALL,
- },
/* Main Nav extended TX channels */
{
},
{
.start_resource = 418,
- .num_resource = 5,
+ .num_resource = 7,
.type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
RESASG_SUBTYPE_RA_UDMAP_RX),
.host_id = HOST_ID_MAIN_0_R5_0,
},
{
- .start_resource = 423,
- .num_resource = 16,
+ .start_resource = 425,
+ .num_resource = 15,
.type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
RESASG_SUBTYPE_RA_UDMAP_RX),
.host_id = HOST_ID_MAIN_0_R5_2,
},
- {
- .start_resource = 439,
- .num_resource = 1,
- .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
- RESASG_SUBTYPE_RA_UDMAP_RX),
- .host_id = HOST_ID_ALL,
- },
/* Main Nav TX Extended rings */
{
index 0982311441fdc3d6a09d355d61043728876a7940..b1f6afe3effa3ec67d05326a1edfb0743177ebf7 100644 (file)
#ifndef SYSFW_IMG_CFG_H
#define SYSFW_IMG_CFG_H
-#define BOARDCFG_RM_RESASG_ENTRIES 254
+#define BOARDCFG_RM_RESASG_ENTRIES 252
#endif /* SYSFW_IMG_CFG_H */