rm-cfg: j721e: Partition generic IR resource across core0/core1 ti2019.06 ti2019.06-rc5 ti2020-rc1 ti2020.00-rc1
authorNikhil Devshatwar <nikhil.nd@ti.com>
Thu, 23 Jan 2020 19:31:39 +0000 (01:01 +0530)
committerLokesh Vutla <lokeshvutla@ti.com>
Fri, 24 Jan 2020 15:06:29 +0000 (20:36 +0530)
Main NAVSS interrupt router for MCU R5 subsystem is shared between
both CPU cores.

However, SYSFW models them to core specific devices where it
appears that the interrupt router is dedicated for each core.

MCU NAVSS IR is dedicated per MCU core but main NAVSS IR is not.
Due to this, drivers calling GET_RANGE gets the same range on
both cores, causing conflict in the interrupt partitioning.

Fix this by partitioning the shared interrupt pool between
MCU R5 core0 and core1.

Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
soc/j721e/evm/rm-cfg.c

index 82bfe060699031d511bce4d7a81276b96709d3a5..b028b5a4416f1720bb3f854f599633e1bc606e2c 100644 (file)
@@ -154,7 +154,7 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
                },
                {
                        .start_resource = 376U,
-                       .num_resource = 8U,
+                       .num_resource = 4U,
                        .type = RESASG_UTYPE(J721E_DEV_MCU_R5FSS0_CORE0,
                                        RESASG_SUBTYPE_MCU_R5FSS0_CORE0_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0),
                        .host_id = HOST_ID_MCU_0_R5_0,
@@ -190,8 +190,8 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
                        .host_id = HOST_ID_MCU_0_R5_2,
                },
                {
-                       .start_resource = 376U,
-                       .num_resource = 8U,
+                       .start_resource = 380U,
+                       .num_resource = 4U,
                        .type = RESASG_UTYPE(J721E_DEV_MCU_R5FSS0_CORE1,
                                        RESASG_SUBTYPE_MCU_R5FSS0_CORE1_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0),
                        .host_id = HOST_ID_MCU_0_R5_2,