From: Nishanth Menon Date: Sat, 18 May 2019 12:19:26 +0000 (-0500) Subject: include: Add AM65X specific headers corresponding to SYSFW X-Git-Tag: ti2019.02-rc1~11 X-Git-Url: https://git.ti.com/gitweb?p=processor-firmware%2Fsystem-firmware-image-gen.git;a=commitdiff_plain;h=6c918cf454b3e5a82df3d697bee624eaa41b3881 include: Add AM65X specific headers corresponding to SYSFW Introduce initial AM65X specific headers Signed-off-by: Nishanth Menon Signed-off-by: Andreas Dannenberg Reviewed-by: Suman Anna --- diff --git a/include/soc/am65x/devices.h b/include/soc/am65x/devices.h new file mode 100644 index 0000000..a1bc921 --- /dev/null +++ b/include/soc/am65x/devices.h @@ -0,0 +1,282 @@ +/* + * K3 System Firmware Board Configuration Data Definitions + * + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef SOC_AM6_DEVICES_H +#define SOC_AM6_DEVICES_H + +#define AM6_DEV_DCC4 13 +#define AM6_DEV_DCC6 15 +#define AM6_DEV_DCC0 9 +#define AM6_DEV_MCU_DCC2 19 +#define AM6_DEV_DCC5 14 +#define AM6_DEV_MCU_DCC0 17 +#define AM6_DEV_MCU_DCC1 18 +#define AM6_DEV_DCC1 10 +#define AM6_DEV_DCC3 12 +#define AM6_DEV_DCC7 16 +#define AM6_DEV_DCC2 11 +#define AM6_DEV_MCU_I2C0 114 +#define AM6_DEV_I2C3 113 +#define AM6_DEV_I2C2 112 +#define AM6_DEV_WKUP_I2C0 115 +#define AM6_DEV_I2C0 110 +#define AM6_DEV_I2C1 111 +#define AM6_DEV_TIMER5 30 +#define AM6_DEV_TIMER6 31 +#define AM6_DEV_TIMER7 32 +#define AM6_DEV_MCU_TIMER0 35 +#define AM6_DEV_TIMER8 33 +#define AM6_DEV_TIMER2 27 +#define AM6_DEV_MCU_TIMER1 36 +#define AM6_DEV_MCU_TIMER2 37 +#define AM6_DEV_TIMER4 29 +#define AM6_DEV_TIMER3 28 +#define AM6_DEV_TIMER9 34 +#define AM6_DEV_TIMER11 26 +#define AM6_DEV_TIMER10 25 +#define AM6_DEV_TIMER0 23 +#define AM6_DEV_MCU_TIMER3 38 +#define AM6_DEV_TIMER1 24 +#define AM6_DEV_WKUP_PSC0 79 +#define AM6_DEV_CBASS0 82 +#define AM6_DEV_PLL_MMR0 101 +#define AM6_DEV_MCU_CPT2_AGGR0 7 +#define AM6_DEV_CPT2_AGGR0 6 +#define AM6_DEV_DEBUGSS0 68 +#define AM6_DEV_EHRPWM4 44 +#define AM6_DEV_EHRPWM1 41 +#define AM6_DEV_EHRPWM0 40 +#define AM6_DEV_EHRPWM3 43 +#define AM6_DEV_EHRPWM5 45 +#define AM6_DEV_EHRPWM2 42 +#define AM6_DEV_ELM0 46 +#define AM6_DEV_MCU_UART0 149 +#define AM6_DEV_WKUP_UART0 150 +#define AM6_DEV_UART1 147 +#define AM6_DEV_UART0 146 +#define AM6_DEV_UART2 148 +#define AM6_DEV_SA2_UL0 136 +#define AM6_DEV_CAL0 2 +#define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4 206 +#define AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3 207 +#define AM6_DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0 208 +#define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3 209 +#define AM6_DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1 210 +#define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5 211 +#define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6 212 +#define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0 213 +#define AM6_DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2 214 +#define AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2 215 +#define AM6_DEV_PBIST0 73 +#define AM6_DEV_PBIST1 74 +#define AM6_DEV_MCU_PBIST0 75 +#define AM6_DEV_NAVSS0 118 +#define AM6_DEV_DSS0 67 +#define AM6_DEV_GPMC0 60 +#define AM6_DEV_MMCSD1 48 +#define AM6_DEV_WKUP_PLLCTRL0 77 +#define AM6_DEV_PLLCTRL0 76 +#define AM6_DEV_USB3SS1 152 +#define AM6_DEV_USB3SS0 151 +#define AM6_DEV_MCU_MCSPI0 142 +#define AM6_DEV_MCSPI2 139 +#define AM6_DEV_MCU_MCSPI2 144 +#define AM6_DEV_MCSPI0 137 +#define AM6_DEV_MCSPI1 138 +#define AM6_DEV_MCSPI4 141 +#define AM6_DEV_MCSPI3 140 +#define AM6_DEV_MCU_MCSPI1 143 +#define AM6_DEV_DEBUGSS_WRAP0 21 +#define AM6_DEV_CBASS_INFRA0 85 +#define AM6_DEV_STM0 8 +#define AM6_DEV_MCU_RTI1 135 +#define AM6_DEV_RTI0 130 +#define AM6_DEV_RTI3 133 +#define AM6_DEV_RTI1 131 +#define AM6_DEV_MCU_RTI0 134 +#define AM6_DEV_RTI2 132 +#define AM6_DEV_PSRAMECC0 128 +#define AM6_DEV_EFUSE0 69 +#define AM6_DEV_MCASP0 104 +#define AM6_DEV_MCASP1 105 +#define AM6_DEV_MCASP2 106 +#define AM6_DEV_MCU_ARMSS0 129 +#define AM6_DEV_MCU_ARMSS0_CPU0 159 +#define AM6_DEV_MCU_ARMSS0_CPU1 245 +#define AM6_DEV_CCDEBUGSS0 66 +#define AM6_DEV_WKUP_CTRL_MMR0 155 +#define AM6_DEV_MCU_CBASS_FW0 91 +#define AM6_DEV_MCU_CPSW0 5 +#define AM6_DEV_SERDES0 153 +#define AM6_DEV_SERDES1 154 +#define AM6_DEV_OLDI_TX_CORE_MAIN_0 216 +#define AM6_DEV_MCU_ADC1 1 +#define AM6_DEV_MCU_ADC0 0 +#define AM6_DEV_WKUP_DMSC0 22 +#define AM6_DEV_MCU_PLL_MMR0 108 +#define AM6_DEV_MCU_SEC_MMR0 109 +#define AM6_DEV_GIC0 56 +#define AM6_DEV_MCU_DEBUGSS0 71 +#define AM6_DEV_EQEP0 49 +#define AM6_DEV_EQEP2 51 +#define AM6_DEV_EQEP1 50 +#define AM6_DEV_WKUP_GPIO0 59 +#define AM6_DEV_GPIO0 57 +#define AM6_DEV_GPIO1 58 +#define AM6_DEV_COMPUTE_CLUSTER_MSMC0 196 +#define AM6_DEV_COMPUTE_CLUSTER_PBIST0 197 +#define AM6_DEV_COMPUTE_CLUSTER_CPAC0 198 +#define AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST0 199 +#define AM6_DEV_COMPUTE_CLUSTER_CPAC1 200 +#define AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST1 201 +#define AM6_DEV_COMPUTE_CLUSTER_A53_0 202 +#define AM6_DEV_COMPUTE_CLUSTER_A53_1 203 +#define AM6_DEV_COMPUTE_CLUSTER_A53_2 204 +#define AM6_DEV_COMPUTE_CLUSTER_A53_3 205 +#define AM6_DEV_WKUP_CBASS0 94 +#define AM6_DEV_MCU_ROM0 78 +#define AM6_DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0 217 +#define AM6_DEV_ESM0 52 +#define AM6_DEV_PRU_ICSSG2 64 +#define AM6_DEV_PRU_ICSSG0 62 +#define AM6_DEV_PRU_ICSSG1 63 +#define AM6_DEV_MCU_ESM0 53 +#define AM6_DEV_ECAP0 39 +#define AM6_DEV_WKUP_ESM0 54 +#define AM6_DEV_MCU_EFUSE0 72 +#define AM6_DEV_MCU_CTRL_MMR0 107 +#define AM6_DEV_PSC0 70 +#define AM6_DEV_CTRL_MMR0 99 +#define AM6_DEV_MCU_MCAN0 102 +#define AM6_DEV_MCU_MCAN1 103 +#define AM6_DEV_DDRSS0 20 +#define AM6_DEV_MCU_NAVSS0 119 +#define AM6_DEV_MCU_FSS0 55 +#define AM6_DEV_DFTSS0 117 +#define AM6_DEV_WKUP_GPIOMUX_INTRTR0 156 +#define AM6_DEV_GPIOMUX_INTRTR0 100 +#define AM6_DEV_MAIN2MCU_LVL_INTRTR0 97 +#define AM6_DEV_MAIN2MCU_PLS_INTRTR0 98 +#define AM6_DEV_ICEMELTER_WKUP_0 218 +#define AM6_DEV_GPU0 65 +#define AM6_DEV_PDMA_DEBUG0 122 +#define AM6_DEV_PDMA0 123 +#define AM6_DEV_PDMA1 124 +#define AM6_DEV_MCU_PDMA0 125 +#define AM6_DEV_MCU_PDMA1 126 +#define AM6_DEV_MCU_MSRAM0 116 +#define AM6_DEV_CMPEVENT_INTRTR0 3 +#define AM6_DEV_DEBUGSUSPENDRTR0 81 +#define AM6_DEV_TIMESYNC_INTRTR0 145 +#define AM6_DEV_CBASS_DEBUG0 83 +#define AM6_DEV_CBASS_FW0 84 +#define AM6_DEV_MCU_CBASS_DEBUG0 90 +#define AM6_DEV_WKUP_CBASS_FW0 96 +#define AM6_DEV_PCIE0 120 +#define AM6_DEV_PCIE1 121 +#define AM6_DEV_GTC0 61 +#define AM6_DEV_K3_LED_MAIN_0 219 +#define AM6_DEV_WKUP_VTM0 80 +#define AM6_DEV_MMCSD0 47 +#define AM6_DEV_MCU_ECC_AGGR0 92 +#define AM6_DEV_ECC_AGGR1 87 +#define AM6_DEV_ECC_AGGR2 88 +#define AM6_DEV_MCU_ECC_AGGR1 93 +#define AM6_DEV_WKUP_ECC_AGGR0 95 +#define AM6_DEV_VDC_DATA_VBUSM_32B_REF_WKUP2MCU 220 +#define AM6_DEV_VDC_DATA_VBUSM_32B_REF_MCU2WKUP 221 +#define AM6_DEV_VDC_DATA_VBUSM_64B_REF_MAIN2MCU 222 +#define AM6_DEV_VDC_DATA_VBUSM_64B_REF_MCU2MAIN 223 +#define AM6_DEV_VDC_DMSC_DBG_VBUSP_32B_REF_DBG2DMSC 224 +#define AM6_DEV_VDC_INFRA_VBUSP_32B_REF_WKUP2MAIN_INFRA 225 +#define AM6_DEV_VDC_INFRA_VBUSP_32B_REF_MCU2MAIN_INFRA 226 +#define AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWWKUP2MCU 227 +#define AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWMCU2MAIN 228 +#define AM6_DEV_VDC_MCU_DBG_VBUSP_32B_REF_DBGMAIN2MCU 229 +#define AM6_DEV_ECC_AGGR0 86 +#define AM6_DEV_VDC_NAV_PSIL_128B_REF_MAIN2MCU 230 +#define AM6_DEV_MCU_PSRAM0 127 +#define AM6_DEV_GS80PRG_SOC_WRAP_WKUP_0 231 +#define AM6_DEV_GS80PRG_MCU_WRAP_WKUP_0 232 +#define AM6_DEV_MCU_CBASS0 89 +#define AM6_DEV_MX_WAKEUP_RESET_SYNC_WKUP_0 233 +#define AM6_DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0 234 +#define AM6_DEV_MX_EFUSE_MCU_CHAIN_MCU_0 235 +#define AM6_DEV_DUMMY_IP_LPSC_WKUP2MCU 236 +#define AM6_DEV_DUMMY_IP_LPSC_WKUP2MAIN_INFRA 237 +#define AM6_DEV_DUMMY_IP_LPSC_DEBUG2DMSC 238 +#define AM6_DEV_DUMMY_IP_LPSC_DMSC 239 +#define AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN_INFRA 240 +#define AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN 241 +#define AM6_DEV_DUMMY_IP_LPSC_MCU2WKUP 242 +#define AM6_DEV_DUMMY_IP_LPSC_MAIN2MCU 243 +#define AM6_DEV_DUMMY_IP_LPSC_EMIF_DATA 244 +#define AM6_DEV_BOARD0 157 +#define AM6_DEV_WKUP_DMSC0_CORTEX_M3_0 161 +#define AM6_DEV_WKUP_DMSC0_INTR_AGGR_0 162 +#define AM6_DEV_NAVSS0_CPTS0 163 +#define AM6_DEV_NAVSS0_INTR_ROUTER_0 182 +#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER0 164 +#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER1 165 +#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER2 166 +#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER3 167 +#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER4 168 +#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER5 169 +#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER6 170 +#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER7 171 +#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER8 172 +#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER9 173 +#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER10 174 +#define AM6_DEV_NAVSS0_MAILBOX0_CLUSTER11 175 +#define AM6_DEV_NAVSS0_MCRC0 176 +#define AM6_DEV_NAVSS0_MODSS_INTA0 180 +#define AM6_DEV_NAVSS0_MODSS_INTA1 181 +#define AM6_DEV_NAVSS0_PROXY0 185 +#define AM6_DEV_NAVSS0_PVU0 177 +#define AM6_DEV_NAVSS0_PVU1 178 +#define AM6_DEV_NAVSS0_RINGACC0 187 +#define AM6_DEV_NAVSS0_SEC_PROXY0 186 +#define AM6_DEV_NAVSS0_TIMER_MGR0 183 +#define AM6_DEV_NAVSS0_TIMER_MGR1 184 +#define AM6_DEV_NAVSS0_UDMAP0 188 +#define AM6_DEV_NAVSS0_UDMASS_INTA0 179 +#define AM6_DEV_MCU_NAVSS0_INTR_AGGR_0 189 +#define AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0 190 +#define AM6_DEV_MCU_NAVSS0_MCRC0 193 +#define AM6_DEV_MCU_NAVSS0_PROXY0 191 +#define AM6_DEV_MCU_NAVSS0_RINGACC0 195 +#define AM6_DEV_MCU_NAVSS0_SEC_PROXY0 192 +#define AM6_DEV_MCU_NAVSS0_UDMAP0 194 + +#endif /* SOC_AM6_DEVICES_H */ diff --git a/include/soc/am65x/hosts.h b/include/soc/am65x/hosts.h new file mode 100644 index 0000000..0fe61be --- /dev/null +++ b/include/soc/am65x/hosts.h @@ -0,0 +1,85 @@ +/* + * K3 System Firmware Board Configuration Data Definitions + * + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef AM6_HOSTS_H +#define AM6_HOSTS_H + +/* Host IDs for AM6 Device */ + +/** DMSC(Secure): Device Management and Security Control */ +#define HOST_ID_DMSC (0U) +/** r5_0(Non Secure): Cortex R5 Context 0 on MCU island */ +#define HOST_ID_R5_0 (3U) +/** r5_1(Secure): Cortex R5 Context 1 on MCU island(Boot) */ +#define HOST_ID_R5_1 (4U) +/** r5_2(Non Secure): Cortex R5 Context 2 on MCU island */ +#define HOST_ID_R5_2 (5U) +/** r5_3(Secure): Cortex R5 Context 3 on MCU island */ +#define HOST_ID_R5_3 (6U) +/** a53_0(Secure): Cortex A53 context 0 on Main island */ +#define HOST_ID_A53_0 (10U) +/** a53_1(Secure): Cortex A53 context 1 on Main island */ +#define HOST_ID_A53_1 (11U) +/** a53_2(Non Secure): Cortex A53 context 2 on Main island */ +#define HOST_ID_A53_2 (12U) +/** a53_3(Non Secure): Cortex A53 context 3 on Main island */ +#define HOST_ID_A53_3 (13U) +/** a53_4(Non Secure): Cortex A53 context 4 on Main island */ +#define HOST_ID_A53_4 (14U) +/** a53_5(Non Secure): Cortex A53 context 5 on Main island */ +#define HOST_ID_A53_5 (15U) +/** a53_6(Non Secure): Cortex A53 context 6 on Main island */ +#define HOST_ID_A53_6 (16U) +/** a53_7(Non Secure): Cortex A53 context 7 on Main island */ +#define HOST_ID_A53_7 (17U) +/** gpu_0(Non Secure): SGX544 Context 0 on Main island */ +#define HOST_ID_GPU_0 (30U) +/** gpu_1(Non Secure): SGX544 Context 1 on Main island */ +#define HOST_ID_GPU_1 (31U) +/** icssg_0(Non Secure): ICSS Context 0 on Main island */ +#define HOST_ID_ICSSG_0 (50U) +/** icssg_1(Non Secure): ICSS Context 1 on Main island */ +#define HOST_ID_ICSSG_1 (51U) +/** icssg_2(Non Secure): ICSS Context 2 on Main island */ +#define HOST_ID_ICSSG_2 (52U) + +/** Host catch all. Used in board configuration resource assignments to + * define resource ranges useable by all hosts. Cannot be used as a host + * in TISCI message headers */ +#define HOST_ID_ALL (128U) + +/** Number of unique hosts on the AM6 SoC */ +#define HOST_ID_CNT (19U) + +#endif /* AM6_HOSTS_H */ diff --git a/include/soc/am65x/resasg_types.h b/include/soc/am65x/resasg_types.h new file mode 100644 index 0000000..5e06ea3 --- /dev/null +++ b/include/soc/am65x/resasg_types.h @@ -0,0 +1,298 @@ +/* + * K3 System Firmware Board Configuration Data Definitions + * + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef RESASG_TYPES_H +#define RESASG_TYPES_H + +/** + * Resource assignment type shift + */ +#define RESASG_TYPE_SHIFT (0x0006U) +/** + * Resource assignment type mask + */ +#define RESASG_TYPE_MASK (0xFFC0U) + +/** + * Resource assignment subtype shift + */ +#define RESASG_SUBTYPE_SHIFT (0x0000U) +/** + * Resource assignment subtype mask + */ +#define RESASG_SUBTYPE_MASK (0x003FU) + +/** + * Macro to create unique resource assignment types using type and subtype + */ +#define RESASG_UTYPE(type, subtype) \ + (((type << RESASG_TYPE_SHIFT) & RESASG_TYPE_MASK) | \ + ((subtype << RESASG_SUBTYPE_SHIFT) & RESASG_SUBTYPE_MASK)) + +/** Main domain Navigator Subsystem UDMASS IA0 */ +#define RESASG_TYPE_MAIN_NAV_UDMASS_IA0 (0x000U) +/** Main domain Navigator Subsystem MODSS IA0 */ +#define RESASG_TYPE_MAIN_NAV_MODSS_IA0 (0x001U) +/** Main domain Navigator Subsystem MODSS IA1 */ +#define RESASG_TYPE_MAIN_NAV_MODSS_IA1 (0x002U) +/** MCU domain Navigator Subsystem UDMASS IA0 */ +#define RESASG_TYPE_MCU_NAV_UDMASS_IA0 (0x003U) +/** Main domain Navigator Subsystem MCRC */ +#define RESASG_TYPE_MAIN_NAV_MCRC (0x004U) +/** MCU domain Navigator Subsystem MCRC */ +#define RESASG_TYPE_MCU_NAV_MCRC (0x005U) +/** Main domain Navigator Subsystem UDMAP */ +#define RESASG_TYPE_MAIN_NAV_UDMAP (0x006U) +/** MCU domain Navigator Subsystem UDMAP */ +#define RESASG_TYPE_MCU_NAV_UDMAP (0x007U) +/** MSMC */ +#define RESASG_TYPE_MSMC (0x008U) +/** Main domain Navigator Subsystem Ring Accelerator */ +#define RESASG_TYPE_MAIN_NAV_RA (0x009U) +/** MCU domain Navigator Subsystem Ring Accelerator */ +#define RESASG_TYPE_MCU_NAV_RA (0x00AU) +/** A53 GIC IRQ (input interrupts) */ +#define RESASG_TYPE_GIC_IRQ (0x00BU) +/** Pulsar core 0 IRQ (input interrupts) */ +#define RESASG_TYPE_PULSAR_C0_IRQ (0x00CU) +/** Pulsar core 1 IRQ (input interrupts) */ +#define RESASG_TYPE_PULSAR_C1_IRQ (0x00DU) +/** ICSSG 0 IRQ (input interrupts) */ +#define RESASG_TYPE_ICSSG0_IRQ (0x00EU) +/** ICSSG 1 IRQ (input interrupts) */ +#define RESASG_TYPE_ICSSG1_IRQ (0x00FU) +/** ICSSG 2 IRQ (input interrupts) */ +#define RESASG_TYPE_ICSSG2_IRQ (0x010U) +/** Maximum RESASG_TYPE value. DO NOT create types with a value + * greater than this */ +#define RESASG_TYPE_MAX (0x3FFU) + +/** Main Nav UDMASS IA0 virtual interrupts */ +#define RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_VINT (0x00U) +/** Main Nav UDMASS IA0 source events (SEVI) */ +#define RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_SEVI (0x01U) +/** Main Nav UDMASS IA0 multicast events (MEVI) */ +#define RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_MEVI (0x02U) +/** Main Nav UDMASS IA0 global counter events (GEVI) */ +#define RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_GEVI (0x03U) +/** Main Nav Total UDMASS IA0 subtypes. Update when subtypes added */ +#define RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_CNT (0x04U) + +/** Main Nav MODSS IA0 virtual interrupts */ +#define RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_VINT (0x00U) +/** Main Nav MODSS IA0 single events (SEVI) */ +#define RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_SEVI (0x01U) +/** Total Main Nav MODSS IA0 subtypes. Update when subtypes added */ +#define RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_CNT (0x02U) + +/** Main Nav MODSS IA1 virtual interrupts */ +#define RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_VINT (0x00U) +/** Main Nav MODSS IA1 single events (SEVI) */ +#define RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_SEVI (0x01U) +/** Total Main Nav MODSS IA1 subtypes. Update when subtypes added */ +#define RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_CNT (0x02U) + +/** MCU Nav UDMASS IA0 virtual interrupts */ +#define RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_VINT (0x00U) +/** MCU Nav UDMASS IA0 single events (SEVI) */ +#define RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_SEVI (0x01U) +/** MCU Nav UDMASS IA0 multicast events (MEVI) */ +#define RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_MEVI (0x02U) +/** MCU Nav UDMASS IA0 global counter events (GEVI) */ +#define RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_GEVI (0x03U) +/** Total MCU Nav UDMASS IA0 subtypes. Update when subtypes added */ +#define RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_CNT (0x04U) + +/** Main Nav MCRC local events (LEVI) */ +#define RESASG_SUBTYPE_MAIN_NAV_MCRC_LEVI (0x00U) +/** Total Main Nav MCRC subtypes. Update when subtypes added */ +#define RESASG_SUBTYPE_MAIN_NAV_MCRC_CNT (0x01U) + +/** MCU Nav MCRC local events (LEVI) */ +#define RESASG_SUBTYPE_MCU_NAV_MCRC_LEVI (0x00U) +/** Total MCU Nav MCRC subtypes. Update when subtypes are added */ +#define RESASG_SUBTYPE_MCU_NAV_MCRC_CNT (0x01U) + +/** Main Nav UDMAP trigger events */ +#define RESASG_SUBTYPE_MAIN_NAV_UDMAP_TRIGGER (0x00U) +/** Nav UDMAP driver high capacity transmit channels */ +#define RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_HCHAN (0x01U) +/** Main Nav UDMAP driver standard transmit channels */ +#define RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_CHAN (0x02U) +/** Main Nav UDMAP driver external transmit channels */ +#define RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_ECHAN (0x03U) +/** Main Nav UDMAP driver high capacity receive channels */ +#define RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_HCHAN (0x04U) +/** Main Nav UDMAP driver standard receive channels */ +#define RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_CHAN (0x05U) +/** Main Nav UDMAP driver common receive flows used by receive channel + * RCHAN_RFLOW_RNG parameters */ +#define RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_FLOW_COMMON (0x06U) +/** Main Nav UDMAP driver global config invalid flow OES register */ +#define RESASG_SUBTYPE_MAIN_NAV_UDMAP_INVALID_FLOW_OES (0x07U) +/** Main Nav UDMAP driver global config register region rd/wr access */ +#define RESASG_SUBTYPE_MAIN_NAV_UDMAP_GCFG (0x08U) +/** Total Main Nav UDMAP subtypes. Update when subtypes added */ +#define RESASG_SUBTYPE_MAIN_NAV_UDMAP_CNT (0x09U) + +/** MCU Nav UDMAP trigger events */ +#define RESASG_SUBTYPE_MCU_NAV_UDMAP_TRIGGER (0x00U) +/** MCU Nav UDMAP driver high capacity transmit channels */ +#define RESASG_SUBTYPE_MCU_NAV_UDMAP_TX_HCHAN (0x01U) +/** MCU Nav UDMAP driver standard transmit channels */ +#define RESASG_SUBTYPE_MCU_NAV_UDMAP_TX_CHAN (0x02U) +/** MCU Nav UDMAP driver high capacity receive channels */ +#define RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_HCHAN (0x03U) +/** MCU Nav UDMAP driver standard receive channels */ +#define RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_CHAN (0x04U) +/** MCU Nav UDMAP driver common receive flows used by receive channel + * RCHAN_RFLOW_RNG parameters */ +#define RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_FLOW_COMMON (0x05U) +/** MCU Nav UDMAP driver global config invalid flow OES register */ +#define RESASG_SUBTYPE_MCU_NAV_UDMAP_INVALID_FLOW_OES (0x06U) +/** MCU Nav UDMAP driver global config register region rd/wr access */ +#define RESASG_SUBTYPE_MCU_NAV_UDMAP_GCFG (0x07U) +/** Total MCU Nav UDMAP subtypes. Update when subtypes added */ +#define RESASG_SUBTYPE_MCU_NAV_UDMAP_CNT (0x08U) + +/** MSMC DRU events */ +#define RESASG_SUBTYPE_MSMC_DRU (0x00U) +/** Total MSMC subtypes. Update when subtypes added */ +#define RESASG_SUBTYPE_MSMC_CNT (0x01U) + +/** Main Nav RA driver UDMAP tx rings */ +#define RESASG_SUBTYPE_MAIN_NAV_RA_RING_UDMAP_TX (0x00U) +/** Main Nav RA driver UDMAP rx rings */ +#define RESASG_SUBTYPE_MAIN_NAV_RA_RING_UDMAP_RX (0x01U) +/** Main Nav RA driver general purpose rings */ +#define RESASG_SUBTYPE_MAIN_NAV_RA_RING_GP (0x02U) +/** Main Nav RA driver global config error OES register */ +#define RESASG_SUBTYPE_MAIN_NAV_RA_ERROR_OES (0x03U) +/** Main Nav RA driver ring virtids */ +#define RESASG_SUBTYPE_MAIN_NAV_RA_VIRTID (0x04U) +/** Total Main Nav RA subtypes. Update when subtypes are added */ +#define RESASG_SUBTYPE_MAIN_NAV_RA_CNT (0x05U) + +/** MCU Nav RA driver UDMAP tx rings */ +#define RESASG_SUBTYPE_MCU_NAV_RA_RING_UDMAP_TX (0x00U) +/** MCU Nav RA driver UDMAP rx rings */ +#define RESASG_SUBTYPE_MCU_NAV_RA_RING_UDMAP_RX (0x01U) +/** MCU Nav RA driver general purpose rings */ +#define RESASG_SUBTYPE_MCU_NAV_RA_RING_GP (0x02U) +/** MCU Nav RA driver global config error OES register */ +#define RESASG_SUBTYPE_MCU_NAV_RA_ERROR_OES (0x03U) +/** MCU Nav RA driver ring virtids */ +#define RESASG_SUBTYPE_MCU_NAV_RA_VIRTID (0x04U) +/** Total MCU Nav RA subtypes. Update when subtypes added */ +#define RESASG_SUBTYPE_MCU_NAV_RA_CNT (0x05U) + +/** GIC IRQ inputs (64 - 127) from Main Nav */ +#define RESASG_SUBTYPE_GIC_IRQ_MAIN_NAV_SET0 (0x00U) +/** GIC IRQ inputs (392 - 423) from Main GPIO IR */ +#define RESASG_SUBTYPE_GIC_IRQ_MAIN_GPIO (0x01U) +/** GIC IRQ inputs (448 - 503) from Main Nav */ +#define RESASG_SUBTYPE_GIC_IRQ_MAIN_NAV_SET1 (0x02U) +/** GIC IRQ inputs (544 - 559) from Compare event IR */ +#define RESASG_SUBTYPE_GIC_IRQ_COMP_EVT (0x03U) +/** GIC IRQ inputs (712 - 727) from Wakeup GPIO IR */ +#define RESASG_SUBTYPE_GIC_IRQ_WKUP_GPIO (0x04U) +/** Total GIC IRQ subtypes. Update when subtypes added */ +#define RESASG_SUBTYPE_GIC_IRQ_CNT (0x05U) + +/** Pulsar core 0 VIM IRQ inputs (64 - 95) from MCU Nav */ +#define RESASG_SUBTYPE_PULSAR_C0_IRQ_MCU_NAV (0x00U) +/** Pulsar core 0 VIM IRQ inputs (124 - 139) from Wakeup GPIO IR */ +#define RESASG_SUBTYPE_PULSAR_C0_IRQ_WKUP_GPIO (0x01U) +/** Pulsar core 0 VIM IRQ inputs (160 - 223) from Main2MCU level IR */ +#define RESASG_SUBTYPE_PULSAR_C0_IRQ_MAIN2MCU_LVL (0x02U) +/** Pulsar core 0 VIM IRQ inputs (224 - 271) from Main2MCU pulse IR */ +#define RESASG_SUBTYPE_PULSAR_C0_IRQ_MAIN2MCU_PLS (0x03U) +/** Total Pulsar core 0 IRQ subtypes. Update when subtypes added */ +#define RESASG_SUBTYPE_PULSAR_C0_IRQ_CNT (0x04U) + +/** Pulsar core 1 VIM IRQ inputs (64 - 95) from MCU Nav */ +#define RESASG_SUBTYPE_PULSAR_C1_IRQ_MCU_NAV (0x00U) +/** Pulsar core 1 VIM IRQ inputs (124 - 139) from Wakeup GPIO IR */ +#define RESASG_SUBTYPE_PULSAR_C1_IRQ_WKUP_GPIO (0x01U) +/** Pulsar core 1 VIM IRQ inputs (160 - 223) from Main2MCU level IR */ +#define RESASG_SUBTYPE_PULSAR_C1_IRQ_MAIN2MCU_LVL (0x02U) +/** Pulsar core 1 VIM IRQ inputs (224 - 271) from Main2MCU pulse IR */ +#define RESASG_SUBTYPE_PULSAR_C1_IRQ_MAIN2MCU_PLS (0x03U) +/** Total Pulsar core 1 IRQ subtypes. Update when subtypes added */ +#define RESASG_SUBTYPE_PULSAR_C1_IRQ_CNT (0x04U) + +/** ICSSG0 IRQ inputs (110 - 117) from Main Nav */ +#define RESASG_SUBTYPE_ICSSG0_IRQ_MAIN_NAV (0x00U) +/** ICSSG0 IRQ inputs (152 - 159) from Main GPIO IR */ +#define RESASG_SUBTYPE_ICSSG0_IRQ_MAIN_GPIO (0x01U) +/** Total ICSSG 0 IRQ subtypes. Update when subtypes added */ +#define RESASG_SUBTYPE_ICSSG0_IRQ_CNT (0x02U) + +/** ICSSG1 IRQ inputs (110 - 117) from Main Nav */ +#define RESASG_SUBTYPE_ICSSG1_IRQ_MAIN_NAV (0x00U) +/** ICSSG1 IRQ inputs (152 - 159) from Main GPIO IR */ +#define RESASG_SUBTYPE_ICSSG1_IRQ_MAIN_GPIO (0x01U) +/** Total ICSSG1 IRQ subtypes. Update when subtypes added */ +#define RESASG_SUBTYPE_ICSSG1_IRQ_CNT (0x02U) + +/** ICSSG2 IRQ inputs (110 - 117) from Main Nav */ +#define RESASG_SUBTYPE_ICSSG2_IRQ_MAIN_NAV (0x00U) +/** ICSSG2 IRQ inputs (152 - 159) from Main GPIO IR */ +#define RESASG_SUBTYPE_ICSSG2_IRQ_MAIN_GPIO (0x01U) +/** Total ICSSG2 IRQ subtypes. Update when subtypes added */ +#define RESASG_SUBTYPE_ICSSG2_IRQ_CNT (0x02U) + +/** + * Total number of unique resource types for AM6 + */ +#define RESASG_UTYPE_CNT \ + (RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_CNT + \ + RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_CNT + \ + RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_CNT + \ + RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_CNT + \ + RESASG_SUBTYPE_MAIN_NAV_MCRC_CNT + \ + RESASG_SUBTYPE_MCU_NAV_MCRC_CNT + \ + RESASG_SUBTYPE_MAIN_NAV_UDMAP_CNT + \ + RESASG_SUBTYPE_MCU_NAV_UDMAP_CNT + \ + RESASG_SUBTYPE_MSMC_CNT + \ + RESASG_SUBTYPE_MAIN_NAV_RA_CNT + \ + RESASG_SUBTYPE_MCU_NAV_RA_CNT + \ + RESASG_SUBTYPE_GIC_IRQ_CNT + \ + RESASG_SUBTYPE_PULSAR_C0_IRQ_CNT + \ + RESASG_SUBTYPE_PULSAR_C1_IRQ_CNT + \ + RESASG_SUBTYPE_ICSSG0_IRQ_CNT + \ + RESASG_SUBTYPE_ICSSG1_IRQ_CNT + \ + RESASG_SUBTYPE_ICSSG2_IRQ_CNT) + +#endif /* RESASG_TYPES_H */