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raw | patch | inline | side by side (parent: 9c79811)
raw | patch | inline | side by side (parent: 9c79811)
author | Russ Dill <Russ.Dill@ti.com> | |
Tue, 20 Aug 2013 01:50:42 +0000 (18:50 -0700) | ||
committer | Russ Dill <Russ.Dill@ti.com> | |
Fri, 23 Aug 2013 11:18:42 +0000 (04:18 -0700) |
PRCM core is getting too big to be easily readable, break out the pieces.
Signed-off-by: Russ Dill <Russ.Dill@ti.com>
Signed-off-by: Russ Dill <Russ.Dill@ti.com>
src/include/low_power.h | patch | blob | history | |
src/include/powerdomain.h | [new file with mode: 0644] | patch | blob |
src/include/system_am335.h | patch | blob | history | |
src/pm_services/pm_handlers.c | patch | blob | history | |
src/pm_services/powerdomain.c | [new file with mode: 0644] | patch | blob |
src/pm_services/prcm_core.c | patch | blob | history |
index 1074deeb0639f88467caf3f5868faf25040f36bf..23964255046adc5c7318c38cccd847ce48d103ca 100644 (file)
--- a/src/include/low_power.h
+++ b/src/include/low_power.h
#define DS_ENABLE_SHIFT 17
#define DS_ENABLE_MASK (1 << DS_ENABLE_SHIFT)
-
-#define PD_ON 0x3
-#define PD_RET 0x1
-#define PD_OFF 0x0
-
-#define MEM_BANK_RET_ST_RET 0x1
-#define MEM_BANK_RET_ST_OFF 0x0
-
-#define MEM_BANK_ON_ST_ON 0x3
-#define MEM_BANK_ON_ST_RET 0x1
-#define MEM_BANK_ON_ST_OFF 0x0
-
#define WAKE_ALL 0x17ff /* all except MPU_WAKE in DS modes */
#define MPU_WAKE 0x800
} raw;
};
-struct pd_mpu_bits {
- int ram_retst_mask;
- int ram_retst_shift;
- int l2_retst_mask;
- int l2_retst_shift;
- int l1_retst_mask;
- int l1_retst_shift;
- int lpstchg_mask;
- int lpstchg_shift;
- int logicretst_mask;
- int logicretst_shift;
- int pwrst_mask;
- int pwrst_shift;
-};
-
-struct pd_per_bits {
- int per_retst_mask;
- int per_retst_shift;
- int ram1_retst_mask;
- int ram1_retst_shift;
- int ram2_retst_mask;
- int ram2_retst_shift;
- int icss_retst_mask;
- int icss_retst_shift;
- int lpstchg_mask;
- int lpstchg_shift;
- int logicretst_mask;
- int logicretst_shift;
- int pwrst_mask;
- int pwrst_shift;
-};
-
-int pd_state_change(int, int);
-void pd_state_restore(int);
-
-int mpu_ram_ret_state_change(int, int);
-int mpu_l1_ret_state_change(int, int);
-int mpu_l2_ret_state_change(int, int);
-int icss_mem_ret_state_change(int, int);
-int per_mem_ret_state_change(int, int);
-int ocmc_mem_ret_state_change(int, int);
-
-int per_powerst_change(int, int);
-int mpu_powerst_change(int, int);
-
-int get_pd_per_stctrl_val(struct deep_sleep_data *data);
-int get_pd_mpu_stctrl_val(struct deep_sleep_data *data);
-
-int verify_pd_transitions(void);
-
int disable_master_oscillator(void);
int enable_master_oscillator(void);
diff --git a/src/include/powerdomain.h b/src/include/powerdomain.h
--- /dev/null
@@ -0,0 +1,86 @@
+/*
+ * AM33XX-CM3 firmware
+ *
+ * Cortex-M3 (CM3) firmware for power management on Texas Instruments' AM33XX series of SoCs
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This software is licensed under the standard terms and conditions in the Texas Instruments Incorporated
+ * Technology and Software Publicly Available Software License Agreement , a copy of which is included in the
+ * software download.
+*/
+
+#ifndef __POWERDOMAIN_H__
+#define __POWERDOMAIN_H__
+
+#define PD_MPU 0x1
+#define PD_PER 0x2
+
+#define PD_ON 0x3
+#define PD_RET 0x1
+#define PD_OFF 0x0
+
+#define MEM_BANK_RET_ST_RET 0x1
+#define MEM_BANK_RET_ST_OFF 0x0
+
+#define MEM_BANK_ON_ST_ON 0x3
+#define MEM_BANK_ON_ST_RET 0x1
+#define MEM_BANK_ON_ST_OFF 0x0
+
+struct deep_sleep_data;
+
+struct pd_mpu_bits {
+ int ram_retst_mask;
+ int ram_retst_shift;
+ int l2_retst_mask;
+ int l2_retst_shift;
+ int l1_retst_mask;
+ int l1_retst_shift;
+ int lpstchg_mask;
+ int lpstchg_shift;
+ int logicretst_mask;
+ int logicretst_shift;
+ int pwrst_mask;
+ int pwrst_shift;
+};
+
+struct pd_per_bits {
+ int per_retst_mask;
+ int per_retst_shift;
+ int ram1_retst_mask;
+ int ram1_retst_shift;
+ int ram2_retst_mask;
+ int ram2_retst_shift;
+ int icss_retst_mask;
+ int icss_retst_shift;
+ int lpstchg_mask;
+ int lpstchg_shift;
+ int logicretst_mask;
+ int logicretst_shift;
+ int pwrst_mask;
+ int pwrst_shift;
+};
+
+void powerdomain_reset(void);
+void powerdomain_init(void);
+
+int pd_state_change(int, int);
+void pd_state_restore(int);
+
+int mpu_ram_ret_state_change(int, int);
+int mpu_l1_ret_state_change(int, int);
+int mpu_l2_ret_state_change(int, int);
+int icss_mem_ret_state_change(int, int);
+int per_mem_ret_state_change(int, int);
+int ocmc_mem_ret_state_change(int, int);
+
+int per_powerst_change(int, int);
+int mpu_powerst_change(int, int);
+
+int get_pd_per_stctrl_val(struct deep_sleep_data *data);
+int get_pd_mpu_stctrl_val(struct deep_sleep_data *data);
+
+int verify_pd_transitions(void);
+
+#endif
+
index 51fa1b09cc2907b4c5a125940a0877b6df394fa7..c74a45f1cbb61c2b18af549e3aafe6242ba87fac 100644 (file)
#define BB_MPU_WAKE *((volatile int *)(BITBAND_SRAM(&cmd_wake_sources, 11)))
#define BB_USBWOUT1 *((volatile int *)(BITBAND_SRAM(&cmd_wake_sources, 12)))
-#define PD_MPU 0x1
-#define PD_PER 0x2
-
#define RESUME_REG 0x0
#define STAT_ID_REG 0x1
#define PARAM1_REG 0x2
index 75aa04185c8f1fd4522060ffe967f8bf1058ff8e..50ae586142bd6e8b3448f046949e7e42561c9653 100644 (file)
#include <system_am335.h>
#include <clockdomain.h>
#include <hwmod.h>
+#include <powerdomain.h>
/* Enter RTC mode */
void a8_lp_rtc_handler(struct cmd_data *data)
diff --git a/src/pm_services/powerdomain.c b/src/pm_services/powerdomain.c
--- /dev/null
@@ -0,0 +1,287 @@
+/*
+ * AM33XX-CM3 firmware
+ *
+ * Cortex-M3 (CM3) firmware for power management on Texas Instruments' AM33XX series of SoCs
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This software is licensed under the standard terms and conditions in the Texas Instruments Incorporated
+ * Technology and Software Publicly Available Software License Agreement , a copy of which is included in the
+ * software download.
+*/
+
+#include <device_am335x.h>
+#include <low_power.h>
+#include <prcm.h>
+#include <prmam335x.h>
+#include <prm43xx.h>
+#include <system_am335.h>
+#include <powerdomain.h>
+
+/* PRM_MPU bits */
+static const struct pd_mpu_bits am335x_mpu_bits = {
+ .ram_retst_mask = AM335X_MPU_RAM_RETSTATE_MASK,
+ .ram_retst_shift = AM335X_MPU_RAM_RETSTATE_SHIFT,
+ .l2_retst_mask = AM335X_MPU_L2_RETSTATE_MASK,
+ .l2_retst_shift = AM335X_MPU_L2_RETSTATE_SHIFT,
+ .l1_retst_mask = AM335X_MPU_L1_RETSTATE_MASK,
+ .l1_retst_shift = AM335X_MPU_L1_RETSTATE_SHIFT,
+ .lpstchg_mask = AM335X_MPU_LOWPOWERSTATECHANGE_MASK,
+ .lpstchg_shift = AM335X_MPU_LOWPOWERSTATECHANGE_SHIFT,
+ .logicretst_mask = AM335X_MPU_LOGICRETSTATE_MASK,
+ .logicretst_shift = AM335X_MPU_LOGICRETSTATE_SHIFT,
+ .pwrst_mask = AM335X_MPU_POWERSTATE_MASK,
+ .pwrst_shift = AM335X_MPU_POWERSTATE_SHIFT,
+};
+
+/* PRM_MPU bits */
+static const struct pd_mpu_bits am43xx_mpu_bits = {
+ .ram_retst_mask = AM43XX_MPU_RAM_RETSTATE_MASK,
+ .ram_retst_shift = AM43XX_MPU_RAM_RETSTATE_SHIFT,
+ .l2_retst_mask = AM43XX_MPU_L2_RETSTATE_MASK,
+ .l2_retst_shift = AM43XX_MPU_L2_RETSTATE_SHIFT,
+ .l1_retst_mask = AM43XX_MPU_L1_RETSTATE_MASK,
+ .l1_retst_shift = AM43XX_MPU_L1_RETSTATE_SHIFT,
+ .lpstchg_mask = AM43XX_MPU_LOWPOWERSTATECHANGE_MASK,
+ .lpstchg_shift = AM43XX_MPU_LOWPOWERSTATECHANGE_SHIFT,
+ .logicretst_mask = AM43XX_MPU_LOGICRETSTATE_MASK,
+ .logicretst_shift = AM43XX_MPU_LOGICRETSTATE_SHIFT,
+ .pwrst_mask = AM43XX_MPU_POWERSTATE_MASK,
+ .pwrst_shift = AM43XX_MPU_POWERSTATE_SHIFT,
+};
+
+/* PRM_PER bits */
+static const struct pd_per_bits am335x_per_bits = {
+ .per_retst_mask = AM335X_PER_MEM_RETSTATE_MASK,
+ .per_retst_shift = AM335X_PER_MEM_RETSTATE_SHIFT,
+ .ram1_retst_mask = AM335X_PER_RAM_MEM_RETSTATE_MASK,
+ .ram1_retst_shift = AM335X_PER_RAM_MEM_RETSTATE_SHIFT,
+ .icss_retst_mask = AM335X_PER_ICSS_MEM_RETSTATE_MASK,
+ .icss_retst_shift = AM335X_PER_ICSS_MEM_RETSTATE_SHIFT,
+ .lpstchg_mask = AM335X_PER_LOWPOWERSTATECHANGE_MASK,
+ .lpstchg_shift = AM335X_PER_LOWPOWERSTATECHANGE_SHIFT,
+ .logicretst_mask = AM335X_PER_LOGICRETSTATE_MASK,
+ .logicretst_shift = AM335X_PER_LOGICRETSTATE_SHIFT,
+ .pwrst_mask = AM335X_PER_POWERSTATE_MASK,
+ .pwrst_shift = AM335X_PER_POWERSTATE_SHIFT,
+};
+
+/* PRM_PER bits */
+static const struct pd_per_bits am43xx_per_bits = {
+ .per_retst_mask = AM43XX_PER_MEM_RETSTATE_MASK,
+ .per_retst_shift = AM43XX_PER_MEM_RETSTATE_SHIFT,
+ .ram1_retst_mask = AM43XX_PER_RAM1_MEM_RETSTATE_MASK,
+ .ram1_retst_shift = AM43XX_PER_RAM1_MEM_RETSTATE_SHIFT,
+ .ram2_retst_mask = AM43XX_PER_RAM2_MEM_RETSTATE_MASK,
+ .ram2_retst_shift = AM43XX_PER_RAM2_MEM_RETSTATE_SHIFT,
+ .icss_retst_mask = AM43XX_PER_ICSS_MEM_RETSTATE_MASK,
+ .icss_retst_shift = AM43XX_PER_ICSS_MEM_RETSTATE_SHIFT,
+ .lpstchg_mask = AM43XX_PER_LOWPOWERSTATECHANGE_MASK,
+ .lpstchg_shift = AM43XX_PER_LOWPOWERSTATECHANGE_SHIFT,
+ .logicretst_mask = AM43XX_PER_LOGICRETSTATE_MASK,
+ .logicretst_shift = AM43XX_PER_LOGICRETSTATE_SHIFT,
+ .pwrst_mask = AM43XX_PER_POWERSTATE_MASK,
+ .pwrst_shift = AM43XX_PER_POWERSTATE_SHIFT,
+};
+
+struct powerdomain_regs {
+ unsigned int stctrl;
+ unsigned int pwrstst;
+};
+
+struct powerdomain_state {
+ unsigned int stctrl_next_val;
+ unsigned int stctrl_prev_val;
+ unsigned int pwrstst_prev_val;
+};
+
+static const struct powerdomain_regs am335x_pd_regs[] = {
+ [PD_MPU] = {
+ .stctrl = AM335X_PM_MPU_PWRSTCTRL,
+ .pwrstst = AM335X_PM_MPU_PWRSTST,
+ },
+ [PD_PER] = {
+ .stctrl = AM335X_PM_PER_PWRSTCTRL,
+ .pwrstst = AM335X_PM_PER_PWRSTST,
+ },
+};
+
+static const struct powerdomain_regs am43xx_pd_regs[] = {
+ [PD_MPU] = {
+ .stctrl = AM43XX_PM_MPU_PWRSTCTRL,
+ .pwrstst = AM43XX_PM_MPU_PWRSTST,
+ },
+ [PD_PER] = {
+ .stctrl = AM43XX_PM_PER_PWRSTCTRL,
+ .pwrstst = AM43XX_PM_PER_PWRSTST,
+ },
+};
+
+static const struct pd_mpu_bits *mpu_bits;
+static const struct pd_per_bits *per_bits;
+static const struct powerdomain_regs *pd_regs;
+
+static struct powerdomain_state pd_states[] = {
+ [PD_MPU] = {},
+ [PD_PER] = {},
+};
+
+
+/* Clear out the global variables here */
+void powerdomain_reset(void)
+{
+ pd_states[PD_MPU].stctrl_next_val = 0;
+ pd_states[PD_MPU].stctrl_prev_val = 0;
+ pd_states[PD_MPU].pwrstst_prev_val = 0;
+ pd_states[PD_PER].stctrl_next_val = 0;
+ pd_states[PD_PER].stctrl_prev_val = 0;
+ pd_states[PD_PER].pwrstst_prev_val = 0;
+}
+
+void powerdomain_init(void)
+{
+ if (soc_id == AM335X_SOC_ID) {
+ mpu_bits = &am335x_mpu_bits;
+ per_bits = &am335x_per_bits;
+ pd_regs = am335x_pd_regs;
+ } else if (soc_id == AM43XX_SOC_ID) {
+ mpu_bits = &am43xx_mpu_bits;
+ per_bits = &am43xx_per_bits;
+ pd_regs = am43xx_pd_regs;
+ }
+}
+
+/* PD related */
+int pd_state_change(int val, int pd)
+{
+ pd_states[pd].stctrl_next_val = val;
+ pd_states[pd].stctrl_prev_val = __raw_readl(pd_regs[pd].stctrl);
+ pd_states[pd].pwrstst_prev_val = __raw_readl(pd_regs[pd].pwrstst);
+ __raw_writel(val, pd_regs[pd].stctrl);
+
+ return 0;
+}
+
+int mpu_ram_ret_state_change(int val, int var)
+{
+ var = var_mod(var, mpu_bits->ram_retst_mask,
+ (val << mpu_bits->ram_retst_shift));
+
+ return var;
+}
+
+int mpu_l1_ret_state_change(int val, int var)
+{
+ var = var_mod(var, mpu_bits->l1_retst_mask,
+ (val << mpu_bits->l1_retst_shift));
+
+ return var;
+}
+
+int mpu_l2_ret_state_change(int val, int var)
+{
+ var = var_mod(var, mpu_bits->l2_retst_mask,
+ (val << mpu_bits->l2_retst_shift));
+
+ return var;
+}
+
+int icss_mem_ret_state_change(int val, int var)
+{
+ var = var_mod(var, per_bits->icss_retst_mask,
+ (val << per_bits->icss_retst_shift));
+
+ return var;
+}
+
+int per_mem_ret_state_change(int val, int var)
+{
+ var = var_mod(var, per_bits->per_retst_mask,
+ (val << per_bits->per_retst_shift));
+
+ return var;
+}
+
+int ocmc_mem_ret_state_change(int val, int var)
+{
+ var = var_mod(var, per_bits->ram1_retst_mask,
+ (val << per_bits->ram1_retst_shift));
+
+ if (per_bits->ram2_retst_mask)
+ var = var_mod(var, per_bits->ram2_retst_mask,
+ (val << per_bits->ram2_retst_shift));
+
+ return var;
+}
+
+int per_powerst_change(int val, int var)
+{
+ var = var_mod(var, per_bits->pwrst_mask,
+ (val << per_bits->pwrst_shift));
+
+ return var;
+}
+
+int mpu_powerst_change(int val, int var)
+{
+ var = var_mod(var, mpu_bits->pwrst_mask,
+ (val << mpu_bits->pwrst_shift));
+
+ return var;
+}
+
+int get_pd_per_stctrl_val(struct deep_sleep_data *data)
+{
+ int v = 0;
+
+ v = per_powerst_change(data->pd_per_state, v);
+ v = icss_mem_ret_state_change(data->pd_per_icss_mem_ret_state, v);
+ v = per_mem_ret_state_change(data->pd_per_mem_ret_state, v);
+ v = ocmc_mem_ret_state_change(data->pd_per_ocmc_ret_state, v);
+
+ return v;
+}
+
+int get_pd_mpu_stctrl_val(struct deep_sleep_data *data)
+{
+ int v = 0;
+
+ v = mpu_powerst_change(data->pd_mpu_state, v);
+ v = mpu_ram_ret_state_change(data->pd_mpu_ram_ret_state, v);
+ v = mpu_l1_ret_state_change(data->pd_mpu_l1_ret_state, v);
+ v = mpu_l2_ret_state_change(data->pd_mpu_l2_ret_state, v);
+
+ return v;
+}
+
+void pd_state_restore(int pd)
+{
+ __raw_writel(pd_states[pd].stctrl_prev_val, pd_regs[pd].stctrl);
+}
+
+/* Checking only the stst bits for now */
+static int verify_pd_transition(int pd)
+{
+ unsigned int ctrl;
+ unsigned int stst;
+
+ ctrl = __raw_readl(pd_regs[pd].stctrl);
+ stst = __raw_readl(pd_regs[pd].pwrstst);
+
+ if ((ctrl & 0x3) == (stst & 0x3))
+ return CMD_STAT_PASS;
+ else
+ return CMD_STAT_FAIL;
+}
+
+int verify_pd_transitions(void)
+{
+ int result;
+
+ result = verify_pd_transition(PD_MPU);
+ if (result == CMD_STAT_FAIL)
+ return result;
+
+ return verify_pd_transition(PD_PER);
+}
+
index 09dd2288fe7fc972fbd8ff4dbd1751bd00bfbd23..8376176be03b3fe8ab46306b44388d8af6a53cfd 100644 (file)
#include <system_am335.h>
#include <clockdomain.h>
#include <hwmod.h>
+#include <powerdomain.h>
union state_data rtc_mode_data = {
.rtc = {
},
};
-/* PRM_MPU bits */
-static const struct pd_mpu_bits am335x_mpu_bits = {
- .ram_retst_mask = AM335X_MPU_RAM_RETSTATE_MASK,
- .ram_retst_shift = AM335X_MPU_RAM_RETSTATE_SHIFT,
- .l2_retst_mask = AM335X_MPU_L2_RETSTATE_MASK,
- .l2_retst_shift = AM335X_MPU_L2_RETSTATE_SHIFT,
- .l1_retst_mask = AM335X_MPU_L1_RETSTATE_MASK,
- .l1_retst_shift = AM335X_MPU_L1_RETSTATE_SHIFT,
- .lpstchg_mask = AM335X_MPU_LOWPOWERSTATECHANGE_MASK,
- .lpstchg_shift = AM335X_MPU_LOWPOWERSTATECHANGE_SHIFT,
- .logicretst_mask = AM335X_MPU_LOGICRETSTATE_MASK,
- .logicretst_shift = AM335X_MPU_LOGICRETSTATE_SHIFT,
- .pwrst_mask = AM335X_MPU_POWERSTATE_MASK,
- .pwrst_shift = AM335X_MPU_POWERSTATE_SHIFT,
-};
-
-/* PRM_MPU bits */
-static const struct pd_mpu_bits am43xx_mpu_bits = {
- .ram_retst_mask = AM43XX_MPU_RAM_RETSTATE_MASK,
- .ram_retst_shift = AM43XX_MPU_RAM_RETSTATE_SHIFT,
- .l2_retst_mask = AM43XX_MPU_L2_RETSTATE_MASK,
- .l2_retst_shift = AM43XX_MPU_L2_RETSTATE_SHIFT,
- .l1_retst_mask = AM43XX_MPU_L1_RETSTATE_MASK,
- .l1_retst_shift = AM43XX_MPU_L1_RETSTATE_SHIFT,
- .lpstchg_mask = AM43XX_MPU_LOWPOWERSTATECHANGE_MASK,
- .lpstchg_shift = AM43XX_MPU_LOWPOWERSTATECHANGE_SHIFT,
- .logicretst_mask = AM43XX_MPU_LOGICRETSTATE_MASK,
- .logicretst_shift = AM43XX_MPU_LOGICRETSTATE_SHIFT,
- .pwrst_mask = AM43XX_MPU_POWERSTATE_MASK,
- .pwrst_shift = AM43XX_MPU_POWERSTATE_SHIFT,
-};
-
-/* PRM_PER bits */
-static const struct pd_per_bits am335x_per_bits = {
- .per_retst_mask = AM335X_PER_MEM_RETSTATE_MASK,
- .per_retst_shift = AM335X_PER_MEM_RETSTATE_SHIFT,
- .ram1_retst_mask = AM335X_PER_RAM_MEM_RETSTATE_MASK,
- .ram1_retst_shift = AM335X_PER_RAM_MEM_RETSTATE_SHIFT,
- .icss_retst_mask = AM335X_PER_ICSS_MEM_RETSTATE_MASK,
- .icss_retst_shift = AM335X_PER_ICSS_MEM_RETSTATE_SHIFT,
- .lpstchg_mask = AM335X_PER_LOWPOWERSTATECHANGE_MASK,
- .lpstchg_shift = AM335X_PER_LOWPOWERSTATECHANGE_SHIFT,
- .logicretst_mask = AM335X_PER_LOGICRETSTATE_MASK,
- .logicretst_shift = AM335X_PER_LOGICRETSTATE_SHIFT,
- .pwrst_mask = AM335X_PER_POWERSTATE_MASK,
- .pwrst_shift = AM335X_PER_POWERSTATE_SHIFT,
-};
-
-/* PRM_PER bits */
-static const struct pd_per_bits am43xx_per_bits = {
- .per_retst_mask = AM43XX_PER_MEM_RETSTATE_MASK,
- .per_retst_shift = AM43XX_PER_MEM_RETSTATE_SHIFT,
- .ram1_retst_mask = AM43XX_PER_RAM1_MEM_RETSTATE_MASK,
- .ram1_retst_shift = AM43XX_PER_RAM1_MEM_RETSTATE_SHIFT,
- .ram2_retst_mask = AM43XX_PER_RAM2_MEM_RETSTATE_MASK,
- .ram2_retst_shift = AM43XX_PER_RAM2_MEM_RETSTATE_SHIFT,
- .icss_retst_mask = AM43XX_PER_ICSS_MEM_RETSTATE_MASK,
- .icss_retst_shift = AM43XX_PER_ICSS_MEM_RETSTATE_SHIFT,
- .lpstchg_mask = AM43XX_PER_LOWPOWERSTATECHANGE_MASK,
- .lpstchg_shift = AM43XX_PER_LOWPOWERSTATECHANGE_SHIFT,
- .logicretst_mask = AM43XX_PER_LOGICRETSTATE_MASK,
- .logicretst_shift = AM43XX_PER_LOGICRETSTATE_SHIFT,
- .pwrst_mask = AM43XX_PER_POWERSTATE_MASK,
- .pwrst_shift = AM43XX_PER_POWERSTATE_SHIFT,
-};
-
-struct powerdomain_regs {
- unsigned int stctrl;
- unsigned int pwrstst;
-};
-
-struct powerdomain_state {
- unsigned int stctrl_next_val;
- unsigned int stctrl_prev_val;
- unsigned int pwrstst_prev_val;
-};
-
-static const struct powerdomain_regs am335x_pd_regs[] = {
- [PD_MPU] = {
- .stctrl = AM335X_PM_MPU_PWRSTCTRL,
- .pwrstst = AM335X_PM_MPU_PWRSTST,
- },
- [PD_PER] = {
- .stctrl = AM335X_PM_PER_PWRSTCTRL,
- .pwrstst = AM335X_PM_PER_PWRSTST,
- },
-};
-
-static const struct powerdomain_regs am43xx_pd_regs[] = {
- [PD_MPU] = {
- .stctrl = AM43XX_PM_MPU_PWRSTCTRL,
- .pwrstst = AM43XX_PM_MPU_PWRSTST,
- },
- [PD_PER] = {
- .stctrl = AM43XX_PM_PER_PWRSTCTRL,
- .pwrstst = AM43XX_PM_PER_PWRSTST,
- },
-};
-
-static const struct pd_mpu_bits *mpu_bits;
-static const struct pd_per_bits *per_bits;
-static const struct powerdomain_regs *pd_regs;
-
-static struct powerdomain_state pd_states[] = {
- [PD_MPU] = {},
- [PD_PER] = {},
-};
-
/* Clear out the global variables here */
void pm_init(void)
{
cmd_global_data.cmd_id = CMD_ID_INVALID;
cmd_global_data.data = NULL;
- pd_states[PD_MPU].stctrl_next_val = 0;
- pd_states[PD_MPU].stctrl_prev_val = 0;
- pd_states[PD_MPU].pwrstst_prev_val = 0;
- pd_states[PD_PER].stctrl_next_val = 0;
- pd_states[PD_PER].stctrl_prev_val = 0;
- pd_states[PD_PER].pwrstst_prev_val = 0;
+ powerdomain_reset();
}
void setup_soc(void)
var = __raw_readl(CONTROL_STATUS);
soc_type = (var & CONTROL_STATUS_DEVTYPE_MASK) >> CONTROL_STATUS_DEVTYPE_SHIFT;
- /* yes this is ugly */
- if (soc_id == AM335X_SOC_ID) {
- mpu_bits = &am335x_mpu_bits;
- per_bits = &am335x_per_bits;
- pd_regs = am335x_pd_regs;
- } else if (soc_id == AM43XX_SOC_ID) {
- mpu_bits = &am43xx_mpu_bits;
- per_bits = &am43xx_per_bits;
- pd_regs = am43xx_pd_regs;
- }
-
clockdomain_init();
hwmod_init();
-}
-
-/* PD related */
-int pd_state_change(int val, int pd)
-{
- pd_states[pd].stctrl_next_val = val;
- pd_states[pd].stctrl_prev_val = __raw_readl(pd_regs[pd].stctrl);
- pd_states[pd].pwrstst_prev_val = __raw_readl(pd_regs[pd].pwrstst);
- __raw_writel(val, pd_regs[pd].stctrl);
-
- return 0;
-}
-
-int mpu_ram_ret_state_change(int val, int var)
-{
- var = var_mod(var, mpu_bits->ram_retst_mask,
- (val << mpu_bits->ram_retst_shift));
-
- return var;
-}
-
-int mpu_l1_ret_state_change(int val, int var)
-{
- var = var_mod(var, mpu_bits->l1_retst_mask,
- (val << mpu_bits->l1_retst_shift));
-
- return var;
-}
-
-int mpu_l2_ret_state_change(int val, int var)
-{
- var = var_mod(var, mpu_bits->l2_retst_mask,
- (val << mpu_bits->l2_retst_shift));
-
- return var;
-}
-
-int icss_mem_ret_state_change(int val, int var)
-{
- var = var_mod(var, per_bits->icss_retst_mask,
- (val << per_bits->icss_retst_shift));
-
- return var;
-}
-
-int per_mem_ret_state_change(int val, int var)
-{
- var = var_mod(var, per_bits->per_retst_mask,
- (val << per_bits->per_retst_shift));
-
- return var;
-}
-
-int ocmc_mem_ret_state_change(int val, int var)
-{
- var = var_mod(var, per_bits->ram1_retst_mask,
- (val << per_bits->ram1_retst_shift));
-
- if (per_bits->ram2_retst_mask)
- var = var_mod(var, per_bits->ram2_retst_mask,
- (val << per_bits->ram2_retst_shift));
-
- return var;
-}
-
-int per_powerst_change(int val, int var)
-{
- var = var_mod(var, per_bits->pwrst_mask,
- (val << per_bits->pwrst_shift));
-
- return var;
-}
-
-int mpu_powerst_change(int val, int var)
-{
- var = var_mod(var, mpu_bits->pwrst_mask,
- (val << mpu_bits->pwrst_shift));
-
- return var;
-}
-
-int get_pd_per_stctrl_val(struct deep_sleep_data *data)
-{
- int v = 0;
-
- v = per_powerst_change(data->pd_per_state, v);
- v = icss_mem_ret_state_change(data->pd_per_icss_mem_ret_state, v);
- v = per_mem_ret_state_change(data->pd_per_mem_ret_state, v);
- v = ocmc_mem_ret_state_change(data->pd_per_ocmc_ret_state, v);
-
- return v;
-}
-
-int get_pd_mpu_stctrl_val(struct deep_sleep_data *data)
-{
- int v = 0;
-
- v = mpu_powerst_change(data->pd_mpu_state, v);
- v = mpu_ram_ret_state_change(data->pd_mpu_ram_ret_state, v);
- v = mpu_l1_ret_state_change(data->pd_mpu_l1_ret_state, v);
- v = mpu_l2_ret_state_change(data->pd_mpu_l2_ret_state, v);
-
- return v;
+ powerdomain_init();
}
/* DeepSleep related */
/* TODO: Clear all the pending interrupts */
}
-void pd_state_restore(int pd)
-{
- __raw_writel(pd_states[pd].stctrl_prev_val, pd_regs[pd].stctrl);
-}
-
-/* Checking only the stst bits for now */
-static int verify_pd_transition(int pd)
-{
- unsigned int ctrl;
- unsigned int stst;
-
- ctrl = __raw_readl(pd_regs[pd].stctrl);
- stst = __raw_readl(pd_regs[pd].pwrstst);
-
- if ((ctrl & 0x3) == (stst & 0x3))
- return CMD_STAT_PASS;
- else
- return CMD_STAT_FAIL;
-}
-
-int verify_pd_transitions(void)
-{
- int result;
-
- result = verify_pd_transition(PD_MPU);
- if (result == CMD_STAT_FAIL)
- return result;
-
- return verify_pd_transition(PD_PER);
-}
-
struct dpll_pd_data {
int dpll_reg;
int sw_ctrl_dpll_bit;