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raw | patch | inline | side by side (parent: a560c62)
raw | patch | inline | side by side (parent: a560c62)
author | Dave Gerlach <d-gerlach@ti.com> | |
Fri, 6 Dec 2013 21:09:58 +0000 (15:09 -0600) | ||
committer | Russ Dill <Russ.Dill@ti.com> | |
Wed, 11 Dec 2013 16:12:00 +0000 (08:12 -0800) |
Add proper data to allow for power down and bypass of AM43xx plls.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
src/include/dpll_43xx.h | patch | blob | history | |
src/pm_services/dpll.c | patch | blob | history | |
src/pm_services/dpll_43xx.c | patch | blob | history |
index 9e0c7e5df27c44eea2b5100a1ddb313043ac3878..f1458f9c74701c66499ce39a0c60c51b364bc9d8 100644 (file)
--- a/src/include/dpll_43xx.h
+++ b/src/include/dpll_43xx.h
struct dpll_regs;
extern const struct dpll_regs am43xx_dpll_regs[];
+extern const enum dpll_id am43xx_power_down_plls[];
#endif
diff --git a/src/pm_services/dpll.c b/src/pm_services/dpll.c
index 1e2da56c1a0913eec80baebecf25cfdec6a4acfb..e3690353a264613bc86c886da83ef9b48583a012 100644 (file)
--- a/src/pm_services/dpll.c
+++ b/src/pm_services/dpll.c
if (soc_rev > AM335X_REV_ES1_0)
power_down_plls = am335x_pg2_power_down_plls;
- } else if (soc_id == AM43XX_SOC_ID)
+ } else if (soc_id == AM43XX_SOC_ID) {
dpll_regs = am43xx_dpll_regs;
+ power_down_plls = am43xx_power_down_plls;
+ }
}
index 31be75b6394eb1e965eead91bcb29d82d156187d..72610e73c7e5bff46d5f65d58e4433d50f63c6ac 100644 (file)
* software download.
*/
+#include <device_common.h>
+#include <cm43xx.h>
#include <dpll.h>
#include <dpll_43xx.h>
+const struct dpll_regs am43xx_dpll_regs[DPLL_COUNT] = {
+ [DPLL_PER] = {
+ .dpll_pwr_sw_ctrl_reg = DPLL_PWR_SW_CTRL,
+ .sw_ctrl_dpll_bit = SW_CTRL_PER_DPLL,
+ .isoscan_bit = ISOSCAN_PER,
+ .ret_bit = RET_PER,
+ .reset_bit = RESET_PER,
+ .iso_bit = ISO_PER,
+ .pgoodin_bit = PGOODIN_PER,
+ .ponin_bit = PONIN_PER,
+ .dpll_pwr_sw_status_reg = DPLL_PWR_SW_STATUS,
+ .pgoodout_status_bit = PGOODOUT_PER_STATUS,
+ .ponout_status_bit = PONOUT_PER_STATUS,
+ .clkmode_reg = AM43XX_CM_CLKMODE_DPLL_PER,
+ .idlest_reg = AM43XX_CM_IDLEST_DPLL_PER,
+ .clksel_reg = AM43XX_CM_CLKSEL_DPLL_PER,
+ },
+ [DPLL_DISP] = {
+ .dpll_pwr_sw_ctrl_reg = DPLL_PWR_SW_CTRL,
+ .sw_ctrl_dpll_bit = SW_CTRL_DISP_DPLL,
+ .isoscan_bit = ISOSCAN_DISP,
+ .ret_bit = RET_DISP,
+ .reset_bit = RESET_DISP,
+ .iso_bit = ISO_DISP,
+ .pgoodin_bit = PGOODIN_DISP,
+ .ponin_bit = PONIN_DISP,
+ .dpll_pwr_sw_status_reg = DPLL_PWR_SW_STATUS,
+ .pgoodout_status_bit = PGOODOUT_DISP_STATUS,
+ .ponout_status_bit = PONOUT_DISP_STATUS,
+ .clkmode_reg = AM43XX_CM_CLKMODE_DPLL_DISP,
+ .idlest_reg = AM43XX_CM_IDLEST_DPLL_DISP,
+ .clksel_reg = AM43XX_CM_CLKSEL_DPLL_DISP,
+ },
+ [DPLL_DDR] = {
+ .dpll_pwr_sw_ctrl_reg = DPLL_PWR_SW_CTRL,
+ .sw_ctrl_dpll_bit = SW_CTRL_DDR_DPLL,
+ .isoscan_bit = ISOSCAN_DDR,
+ .ret_bit = RET_DDR,
+ .reset_bit = RESET_DDR,
+ .iso_bit = ISO_DDR,
+ .pgoodin_bit = PGOODIN_DDR,
+ .ponin_bit = PONIN_DDR,
+ .dpll_pwr_sw_status_reg = DPLL_PWR_SW_STATUS,
+ .pgoodout_status_bit = PGOODOUT_DDR_STATUS,
+ .ponout_status_bit = PONOUT_DDR_STATUS,
+ .clkmode_reg = AM43XX_CM_CLKMODE_DPLL_DDR,
+ .idlest_reg = AM43XX_CM_IDLEST_DPLL_DDR,
+ .clksel_reg = AM43XX_CM_CLKSEL_DPLL_DDR,
+ },
+ [DPLL_MPU] = {
+ .clkmode_reg = AM43XX_CM_CLKMODE_DPLL_MPU,
+ .idlest_reg = AM43XX_CM_IDLEST_DPLL_MPU,
+ .clksel_reg = AM43XX_CM_CLKSEL_DPLL_MPU,
+ },
+ [DPLL_CORE] = {
+ .clkmode_reg = AM43XX_CM_CLKMODE_DPLL_CORE,
+ .idlest_reg = AM43XX_CM_IDLEST_DPLL_CORE,
+ .clksel_reg = AM43XX_CM_CLKSEL_DPLL_CORE,
+ },
+};
-/* TODO */
-const struct dpll_regs am43xx_dpll_regs[DPLL_COUNT];
-
+const enum dpll_id am43xx_power_down_plls[] = {
+ DPLL_DDR,
+ DPLL_DISP,
+ DPLL_PER,
+ DPLL_END,
+};