03bc1c6f99bf13d69d6c2b60704754fe0abd42a5
1 /******************************************************************************
2 * Copyright (c) 2012-16 Texas Instruments Incorporated - http://www.ti.com
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
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9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 *****************************************************************************
33 *
34 * Filename: evmk2g.gel
35 * Description: Galileo system initialization GEL for use with the Galileo
36 * EVM. This GEL has functions that handle the Main PLL
37 * initialization.
38 *
39 * More functions may be added as needed at a later date.
40 *
41 * Author: Nitin Sakhuja
42 * Revision History:
43 *
44 * Rev 0.1 - 02/06/2012
45 * - Initial file creation - based on latest Appleton PLL init sequnce
46 * + Updated MAINPLLCTL0 and MAINPLLCTL1 MMR addresses for Keystone-2
47 * Rev 1.0 - 02/10/2012
48 * - Updates for Kepler
49 * + Changed CLKIN_val and PLLM_val values according to 1GHz and 1.3GHz clock options.
50 * + Removed non-relevat PLL init combinations.
51 * + Clean-up and formattting improvements.
52 * - Kepler QT specific Workarounds.
53 * + Added dummy reads between all Write->Read sequences to make them Write->Read->Read
54 * as a workaround for a potential Kepler QT PLL model bug, where the first Read following
55 * a Write to a PLL controller MMR seems to return the pre-write value of the MMR.
56 * Rev 4.0 - 01/21/2014
57 * - Updates for Galileo (Mark McKeown)
58 * + Changed CLKIN_val and PLLM_val values for 400, 600, 800, & 1000MHz clocks
59 * + Moved RESET assert from step 9 to step 3 where it belongs according to 6.4.4.3 PLL
60 * Initialization Sequences in clock_arch_galileo_v0.93.pdf
61 * Rev 5.0 - 08/07/2014
62 * - Set_Pll1: fixed hotmenu function names, GEL_TextOut for 50MHz ref clk instead of 100MHz
63 * - Set_Tetris_Pll: Changed Multiplier values for 50MHz ref clk instead of 100Mhz, updated hotmenu function names
64 * DONE 1) try moving reset (step 3) between steps 2 and 4
65 * 2) remove extra steps 2b, 2c, 2d after "step 3"
66 * 3) add step 8c
67 * 4) check values for PLLDIV2 & PLLDIV3 - only SYSCLK2 and SYSCLK3 are programmable.
68 * Rev 6.0 - 08/29/2014 (Sunil K)
69 * - Added NSS PLL definitions & setup function (SET_NSS_PLL)
70 * - Added Hot menu (SET NSS PLL for 50MHz -> 1000MHz) to setup NSS PLL for 50MHZ sysclkp/n input for QT
71 * Rev 7.0 - 04/30/2015 (Uday G)
72 * - Modified PLLM, PLLD, OD values to correspond to 24MHZ reference clock
73 * - Added DSS, DDR, UART PLL definitions & setup function
74 * - Added ability to output all PLLs on OBSCLK
75 * - Verified GEL on Galileo Silicon
76 * Rev 8.0 - 11/25/2015 (Pratap)
77 * - Added Configurations for enabling PSC
78 * - Added clock configurations for DSS 9MHz and 25MHz
79 * Rev 9.0 -
80 * - Added DSP out-of-reset routine 01/20/2016 (Lalindra J)
81 * - Changed the DDR PLL settings as per DPO analysis 01/22/2016 (SenthilKumar S)
82 ---------------------------------------------------------------------------*/
84 //******************************************************
85 // BOOT and CONFIG dsp system modules Definitions
86 #define CHIP_LEVEL_REG 0x02620000
87 #define DEVSTAT *(unsigned int*)(CHIP_LEVEL_REG + 0x0020)
89 // Boot cfg registers
90 #define KICK0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0038)
91 #define KICK1 *(unsigned int*)(CHIP_LEVEL_REG + 0x003C)
92 #define KICK0_UNLOCK (0x83E70B13)
93 #define KICK1_UNLOCK (0x95A4F1E0)
94 #define KICK_LOCK 0
95 #define TINPSEL *(unsigned int*)(CHIP_LEVEL_REG + 0x0300)
96 #define TOUTPSEL *(unsigned int*)(CHIP_LEVEL_REG + 0x0304)
97 #define MAINPLLCTL0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0350) //0x0328)
98 #define MAINPLLCTL1 *(unsigned int*)(CHIP_LEVEL_REG + 0x0354) //0x032C)
99 #define MAIN_PLLD_OFFSET 0
100 #define MAIN_PLLD_MASK 0xFFFFFFC0
101 #define MAIN_PLLM_OFFSET 12
102 #define MAIN_PLLM_MASK 0xFFF80FFF
103 #define MAIN_BWADJ0_OFFSET 24
104 #define MAIN_BWADJ0_MASK 0x00FFFFFF
105 #define MAIN_ENSAT_OFFSET 6
106 #define MAIN_ENSAT_MASK 0xFFFFFFBF
107 #define MAIN_BWADJ1_OFFSET 0
108 #define MAIN_BWADJ1_MASK 0xFFFFFFF0
110 #define CHIP_MISC1 *(unsigned int*)(CHIP_LEVEL_REG + 0x0C7C)
111 #define ARMPLL_ENABLE_OFFSET 13
113 #define DDR3PLLCTL0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0360)
114 #define DDR3PLLCTL1 *(unsigned int*)(CHIP_LEVEL_REG + 0x0364)
115 #define DDR3MUX *(unsigned int*)(CHIP_LEVEL_REG + 0x0690)
116 #define OBSCLKCTL *(unsigned int*)(CHIP_LEVEL_REG + 0x0C80)
118 #define TETRIS_BASE 0x01E80000
120 #define TETRIS_CPU0_PDSTAT *(unsigned int*)(TETRIS_BASE + 0x0404)
121 // Tetris-UL subsystem and A15 core are in a single common power domain and fully controlled by the SoC level PSC.
122 // As per design team (BTS_SPEC.538 WEBS) we should not access the Tetris DPSC registers for Galileo
123 // By default the Tetris power domain is ON and no need to write to any registers
124 // Based on above commenting out the following and any relevant code that attempts to set the same
125 //#define TETRIS_CPU0_PDCTL *(unsigned int*)(TETRIS_BASE + 0x0408)
126 //#define TETRIS_CPU0_PTCMD *(unsigned int*)(TETRIS_BASE + 0x0400)
128 // Commented following lines since Galileo has only one A15 core
129 //#define TETRIS_CPU1_PTCMD *(unsigned int*)(TETRIS_BASE + 0x040C)
130 //#define TETRIS_CPU1_PDSTAT *(unsigned int*)(TETRIS_BASE + 0x0410)
131 //#define TETRIS_CPU1_PDCTL *(unsigned int*)(TETRIS_BASE + 0x0414)
133 //#define TETRIS_CPU2_PTCMD *(unsigned int*)(TETRIS_BASE + 0x0418)
134 //#define TETRIS_CPU2_PDSTAT *(unsigned int*)(TETRIS_BASE + 0x041C)
135 //#define TETRIS_CPU2_PDCTL *(unsigned int*)(TETRIS_BASE + 0x0420)
137 //#define TETRIS_CPU3_PTCMD *(unsigned int*)(TETRIS_BASE + 0x0424)
138 //#define TETRIS_CPU3_PDSTAT *(unsigned int*)(TETRIS_BASE + 0x0428)
139 //#define TETRIS_CPU3_PDCTL *(unsigned int*)(TETRIS_BASE + 0x042C)
141 #define SECPLLCTL0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0370)
142 #define SECPLLCTL1 *(unsigned int*)(CHIP_LEVEL_REG + 0x0374)
144 #define ICSSPLLCTL0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0388)
145 #define ICSSPLLCTL1 *(unsigned int*)(CHIP_LEVEL_REG + 0x038C)
147 #define NSSPLLCTL0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0358)
148 #define NSSPLLCTL1 *(unsigned int*)(CHIP_LEVEL_REG + 0x035C)
150 #define UARTPLLCTL0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0390)
151 #define UARTPLLCTL1 *(unsigned int*)(CHIP_LEVEL_REG + 0x0394)
153 //******************************************************
154 //Boot CFG DDR Registers
156 // DDR3 tuning registers
157 #define DATA0_GTLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x043C))
158 #define DATA1_GTLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x0440))
159 #define DATA2_GTLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x0444))
160 #define DATA3_GTLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x0448))
161 #define DATA4_GTLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x044C))
162 #define DATA5_GTLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x0450))
163 #define DATA6_GTLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x0454))
164 #define DATA7_GTLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x0458))
165 #define DATA8_GTLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x045C))
167 #define DATA0_WRLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x040C))
168 #define DATA1_WRLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x0410))
169 #define DATA2_WRLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x0414))
170 #define DATA3_WRLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x0418))
171 #define DATA4_WRLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x041C))
172 #define DATA5_WRLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x0420))
173 #define DATA6_WRLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x0424))
174 #define DATA7_WRLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x0428))
175 #define DATA8_WRLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x042C))
177 #define DDR3_CONFIG_REG_0 (*(unsigned int*)(CHIP_LEVEL_REG + 0x0404))
178 #define DDR3_CONFIG_REG_12 (*(unsigned int*)(CHIP_LEVEL_REG + 0x0434))
179 #define DDR3_CONFIG_REG_13 (*(unsigned int*)(CHIP_LEVEL_REG + 0x0438))
181 #define DDR3_CONFIG_REG_52 (*(unsigned int*)(CHIP_LEVEL_REG + 0x04D4))
182 #define DDR3_CONFIG_REG_53 (*(unsigned int*)(CHIP_LEVEL_REG + 0x04D8))
183 #define DDR3_CONFIG_REG_54 (*(unsigned int*)(CHIP_LEVEL_REG + 0x04DC))
184 #define DDR3_CONFIG_REG_55 (*(unsigned int*)(CHIP_LEVEL_REG + 0x04E0))
185 #define DDR3_CONFIG_REG_56 (*(unsigned int*)(CHIP_LEVEL_REG + 0x04E4))
186 #define DDR3_CONFIG_REG_57 (*(unsigned int*)(CHIP_LEVEL_REG + 0x04E8))
187 #define DDR3_CONFIG_REG_58 (*(unsigned int*)(CHIP_LEVEL_REG + 0x04EC))
188 #define DDR3_CONFIG_REG_59 (*(unsigned int*)(CHIP_LEVEL_REG + 0x04F0))
189 #define DDR3_CONFIG_REG_60 (*(unsigned int*)(CHIP_LEVEL_REG + 0x04F4))
192 //******************************************************
193 // PLL 1 definitions (DSP and ARM clock and subsystems)
194 #define PLL1_BASE 0x02310000
195 #define PLL1_PLLCTL (*(unsigned int*)(PLL1_BASE + 0x100)) // PLL1 Control
196 #define PLL1_OCSEL (*(unsigned int*)(PLL1_BASE + 0x104)) // PLL1 OCSEL for Observation clock
197 #define PLL1_SECCTL (*(unsigned int*)(PLL1_BASE + 0x108)) // PLL1 Secondary Control
198 #define PLL1_PLLM (*(unsigned int*)(PLL1_BASE + 0x110)) // PLL1 Multiplier
199 #define PLL1_DIV1 (*(unsigned int*)(PLL1_BASE + 0x118)) // DIV1 divider
200 #define PLL1_DIV2 (*(unsigned int*)(PLL1_BASE + 0x11C)) // DIV2 divider
201 #define PLL1_DIV3 (*(unsigned int*)(PLL1_BASE + 0x120)) // DIV3 divider
202 #define PLL1_CMD (*(unsigned int*)(PLL1_BASE + 0x138)) // CMD control
203 #define PLL1_STAT (*(unsigned int*)(PLL1_BASE + 0x13C)) // STAT control
204 #define PLL1_ALNCTL (*(unsigned int*)(PLL1_BASE + 0x140)) // ALNCTL control
205 #define PLL1_DCHANGE (*(unsigned int*)(PLL1_BASE + 0x144)) // DCHANGE status
206 #define PLL1_CKEN (*(unsigned int*)(PLL1_BASE + 0x148)) // CKEN control
207 #define PLL1_CKSTAT (*(unsigned int*)(PLL1_BASE + 0x14C)) // CKSTAT status
208 #define PLL1_SYSTAT (*(unsigned int*)(PLL1_BASE + 0x150)) // SYSTAT status
209 #define PLL1_DIV4 (*(unsigned int*)(PLL1_BASE + 0x160)) // DIV4 divider
210 #define PLL1_DIV5 (*(unsigned int*)(PLL1_BASE + 0x164)) // DIV5 divider
211 #define PLL1_DIV6 (*(unsigned int*)(PLL1_BASE + 0x168)) // DIV6 divider
212 #define PLL1_DIV7 (*(unsigned int*)(PLL1_BASE + 0x16C)) // DIV7 divider
213 #define PLL1_DIV8 (*(unsigned int*)(PLL1_BASE + 0x170)) // DIV8 divider
214 #define PLL1_DIV9 (*(unsigned int*)(PLL1_BASE + 0x174)) // DIV9 divider
215 #define PLL1_DIV10 (*(unsigned int*)(PLL1_BASE + 0x178)) // DIV10 divider
216 #define PLL1_DIV11 (*(unsigned int*)(PLL1_BASE + 0x17C)) // DIV11 divider
217 #define PLL1_DIV12 (*(unsigned int*)(PLL1_BASE + 0x180)) // DIV12 divider
218 #define PLL1_DIV13 (*(unsigned int*)(PLL1_BASE + 0x184)) // DIV13 divider
219 #define PLL1_DIV14 (*(unsigned int*)(PLL1_BASE + 0x188)) // DIV14 divider
220 #define PLL1_DIV15 (*(unsigned int*)(PLL1_BASE + 0x18C)) // DIV15 divider
221 #define PLL1_DIV16 (*(unsigned int*)(PLL1_BASE + 0x190)) // DIV16 divider
222 #define PLLPWRDN_OFFSET 1
223 #define PLLPWRDN_MASK 0xFFFFFFFD
224 #define PLLRST_OFFSET 3
225 #define PLLRST_MASK 0xFFFFFFF7
226 #define PLLENSRC_OFFSET 5
227 #define PLLENSRC_MASK 0xFFFFFFDF
228 #define PLLEN_OFFSET 0
229 #define PLLEN_MASK 0xFFFFFFFE
230 #define OUTPUT_DIVIDE_OFFSET 19
231 #define OUTPUT_DIVIDE_MASK 0xFF87FFFF
232 #define BYPASS_OFFSET 23
233 #define BYPASS_MASK 0xFF7FFFFF
234 #define PLLM_OFFSET 0
235 #define PLLM_MASK 0xFFFFFFC0
236 #define GOSET_OFFSET 0
237 #define GOSET_MASK 0xFFFFFFFE
238 #define GOSTAT_OFFSET 0
239 #define GOSTAT_MASK 0xFFFFFFFE
241 // ARMPLL definitions
242 #define SEC_PLLCTL0_PLLD_OFFSET 0
243 #define SEC_PLLCTL0_PLLD_MASK 0xFFFFFFC0
244 #define SEC_PLLCTL0_PLLM_OFFSET 6
245 #define SEC_PLLCTL0_PLLM_MASK 0xFFFF003F
246 #define SEC_PLLCTL0_BWADJ_OFFSET 24
247 #define SEC_PLLCTL0_BWADJ_MASK 0x00FFFFFF
248 #define SEC_PLLCTL0_OD_OFFSET 19
249 #define SEC_PLLCTL0_OD_MASK 0xFF87FFFF
250 #define SEC_PLLCTL0_BYPASS_OFFSET 23
251 #define SEC_PLLCTL0_BYPASS_MASK 0xFF7FFFFF
252 #define SEC_PLLCTL1_RESET_OFFSET 14
253 #define SEC_PLLCTL1_RESET_MASK 0xFFFFBFFF
254 #define SEC_PLLCTL1_PWRDWN_OFFSET 15
255 #define SEC_PLLCTL1_PWRDWN_MASK 0xFFFF7FFF
256 #define SEC_PLLCTL1_ENSTAT_OFFSET 6
257 #define SEC_PLLCTL1_ENSTAT_MASK 0xFFFFFFBF
259 //******************************************************
260 // DDR3 definitions
261 #define DDR_BASE_ADDR 0x21000000
263 #define DDR_MIDR (*(unsigned int*)(DDR_BASE_ADDR + 0x00000000))
264 #define DDR_SDCFG (*(unsigned int*)(DDR_BASE_ADDR + 0x00000008))
265 #define DDR_SDRFC (*(unsigned int*)(DDR_BASE_ADDR + 0x00000010))
266 #define DDR_SDTIM1 (*(unsigned int*)(DDR_BASE_ADDR + 0x00000018))
267 #define DDR_SDTIM2 (*(unsigned int*)(DDR_BASE_ADDR + 0x00000020))
268 #define DDR_SDTIM3 (*(unsigned int*)(DDR_BASE_ADDR + 0x00000028))
269 #define DDR_PMCTL (*(unsigned int*)(DDR_BASE_ADDR + 0x00000038))
270 #define DDR_ZQCFG (*(unsigned int*)(DDR_BASE_ADDR + 0x000000C8))
271 #define DDR_TMPALRT (*(unsigned int*)(DDR_BASE_ADDR + 0x000000CC))
272 #define DDR_RDWR_LVL_RMP_CTRL (*(unsigned int*)(DDR_BASE_ADDR + 0x000000D8))
273 #define DDR_RDWR_LVL_CTRL (*(unsigned int*)(DDR_BASE_ADDR + 0x000000DC))
274 #define DDR_DDRPHYC (*(unsigned int*)(DDR_BASE_ADDR + 0x000000E4))
276 //******************************************************
277 // XMC Register Definitions
278 #define XMC_BASE_ADDR (0x08000000)
279 #define XMPAX2_L (*(int*)(XMC_BASE_ADDR + 0x00000010))
280 #define XMPAX2_H (*(int*)(XMC_BASE_ADDR + 0x00000014))
282 //******************************************************
283 // MSMC Register Definitions
284 #define MSMC_CFG_BASE (0x0BC00000)
285 #define SMS_MPAXH_0_0 (MSMC_CFG_BASE + 0x00000204)
286 #define SES_MPAXH_0_0 (MSMC_CFG_BASE + 0x00000604)
288 //******************************************************
289 // PSC Register Definitions
291 #define PSC_CFG_BASE (0x02350000)
293 #define PSC_MDCTL00 (0xA00)
294 #define PSC_MDSTAT00 (0x800)
295 #define PSC_PDCTL00 (0x300)
296 #define PSC_PDSTAT00 (0x200)
298 #define PSC_MDCTL_BASE PSC_CFG_BASE + PSC_MDCTL00
299 #define PSC_MDSTAT_BASE PSC_CFG_BASE + PSC_MDSTAT00
300 #define PSC_PDCTL_BASE PSC_CFG_BASE + PSC_PDCTL00
301 #define PSC_PDSTAT_BASE PSC_CFG_BASE + PSC_PDSTAT00
303 #define PMMC_PDCTL (*(unsigned int*)(PSC_PDCTL_BASE + 0x000))
304 #define PMMC_MDCTL (*(unsigned int*)(PSC_MDCTL_BASE + 0x004))
306 #define PSC_PTCMD (*(unsigned int*)(PSC_CFG_BASE + 0x120))
307 #define PSC_PTCMD_H (*(unsigned int*)(PSC_CFG_BASE + 0x124))
308 #define PSC_PTSTAT (*(unsigned int*)(PSC_CFG_BASE + 0x128))
309 #define PSC_PTSTAT_H (*(unsigned int*)(PSC_CFG_BASE + 0x12C))
311 /* BB register field read macro */
312 #define BB_REG_FIELD_READ(reg_addr) (unsigned int)((*((unsigned int*)reg_addr)))
314 #define MAIN_PLL_CTL0_ADDR 0x02620350
315 #define MAIN_PLL_CTL1_ADDR 0x02620354
316 #define PLLCTL_ADDR 0x02310100
317 #define SECCTL_ADDR 0x02310108
318 #define PLLM_ADDR 0x02310110
319 #define PLLDIV1_ADDR 0x02310118
320 #define PLLDIV2_ADDR 0x0231011C
321 #define PLLDIV3_ADDR 0x02310120
322 #define PLLCMD_ADDR 0x02310138
323 #define PLLSTAT_ADDR 0x0231013C
324 #define PLLDIV4_ADDR 0x02310160
325 #define PLLDIV5_ADDR 0x02310164
326 #define PLLDIV6_ADDR 0x02310168
327 #define PLLDIV7_ADDR 0x0231016C
328 #define PLLDIV8_ADDR 0x02310170
330 /* DSS-UL PLL definitions */
331 #define DSS_PLL_CTL0 *(unsigned int*)(CHIP_LEVEL_REG + 0x380)
332 #define DSS_PLL_CTL1 *(unsigned int*)(CHIP_LEVEL_REG + 0x384)
333 #define DSS_PLL_CTL0_BYPASS_EN (1)
334 #define DSS_PLL_CTL0_BYPASS_SHIFT (23)
335 #define DSS_PLL_CTL0_BYPASS_MASK (0x00000000)
336 #define DSS_PLL_CTL0_CLKOD_SHIFT (19)
337 #define DSS_PLL_CTL0_CLKOD_MASK (0x00780000)
338 #define DSS_PLL_CTL0_PLLM_SHIFT (6)
339 #define DSS_PLL_CTL0_PLLM_MASK (0x0007FFC0)
340 #define DSS_PLL_CTL0_PLLD_SHIFT (0)
341 #define DSS_PLL_CTL0_PLLD_MASK (0x0000003F)
342 #define DSS_PLL_MULTIPLIER_MAX (512) //The max is really 4096 but recommended to stay below 512 for low jitter
343 #define DSS_PLL_REF_DIVIDER_MAX (64)
344 #define DSS_PLL_OUTPUT_DIVIDER_MAX (16)
347 #define PD0 (0) // Power Domain-0
348 #define PD1 (1) // Power Domain-1
349 #define PD2 (2) // Power Domain-2
350 #define PD3 (3) // Power Domain-3
351 #define PD4 (4) // Power Domain-4
352 #define PD5 (5) // Power Domain-5
353 #define PD6 (6) // Power Domain-6
354 #define PD7 (7) // Power Domain-7
355 #define PD8 (8) // Power Domain-8
356 #define PD9 (9) // Power Domain-9
357 #define PD10 (10) // Power Domain-10
358 #define PD11 (11) // Power Domain-11
359 #define PD12 (12) // Power Domain-12
360 #define PD13 (13) // Power Domain-13
361 #define PD14 (14) // Power Domain-14
362 #define PD15 (15) // Power Domain-15
364 // Modules on power domain 0
365 #define LPSC_ALWAYSON (0)
367 // Modules on power domain 1
368 #define LPSC_PMMC (1)
369 #define LPSC_DEBUG (2)
371 // Modules on power domain 2
372 #define LPSC_NSS (3)
374 // Modules on power domain 3
375 #define LPSC_SA (4)
377 // Modules on power domain 4
378 #define LPSC_TERANET (5)
380 // Modules on power domain 5
381 #define LPSC_SYS_COMP (6)
382 #define LPSC_QSPI (7)
383 #define LPSC_MMC (8)
384 #define LPSC_GPMC (9)
385 #define LPSC_MLB (11)
386 #define LPSC_EHRPWM (12)
387 #define LPSC_EQEP (13)
388 #define LPSC_ECAP (14)
389 #define LPSC_MCASP (15)
391 // Modules on power domain 7
392 #define LPSC_MSMC (17)
394 // Modules on power domain 8
395 #define LPSC_C66X_COREPAC_0 (18)
397 // Modules on power domain 9
398 #define LPSC_ARM (19)
400 // Modules on power domain 11
401 #define LPSC_ICSS (21)
403 // Modules on power domain 12
404 #define LPSC_DSS (23)
406 // Modules on power domain 13
407 #define LPSC_PCIE (24)
409 // Modules on power domain 14
410 #define LPSC_USB_0 (25)
411 #define LPSC_USB_1 (26)
413 // Modules on power domain 15
414 #define LPSC_DDR3 (27)
416 #define PSC_DISABLE (0x2)
417 #define PSC_ENABLE (0x3)
418 // Global timeout value
419 #define GTIMEOUT 2000
421 #define TIMEOUT_ID 10
423 // Timeout definitions
424 int _GEL_Global_Timeout1 = 0;
426 /*----------Out-of-reset definitions-----------*/
427 #define WR_MEM_32(addr, data) *(unsigned int*)(addr) =(unsigned int)(data)
428 #define RD_MEM_32(addr) *(unsigned int*)(addr)
429 #define uint32_t unsigned int
431 /*******************************************************************************
432 KS2 Registers Map Defines
433 *******************************************************************************/
434 /***** Power Domain Definitions *****/
435 #define KS2_PDCTL5 0x02350314
436 #define KS2_PDCTL8 0x02350320
437 #define KS2_PDCTL9 0x02350324
438 #define KS2_PDCTL10 0x02350328
439 #define KS2_PDCTL11 0x0235032C
440 #define KS2_PDCTL12 0x02350330
441 #define KS2_PDCTL13 0x02350334
442 #define KS2_PDCTL14 0x02350338
443 #define KS2_PDCTL15 0x0235033C
445 /***** Module Control Register Definitions *****/
446 #define KS2_MDCTL5 0x02350A14
447 #define KS2_MDCTL15 0x02350A3C
448 #define KS2_MDCTL16 0x02350A40
449 #define KS2_MDCTL17 0x02350A44
450 #define KS2_MDCTL18 0x02350A48
451 #define KS2_MDCTL19 0x02350A4C
452 #define KS2_MDCTL20 0x02350A50
453 #define KS2_MDCTL21 0x02350A54
454 #define KS2_MDCTL22 0x02350A58
456 /****************************************************************************
457 *
458 * NAME
459 * Global_Default_Setup_Silent
460 *
461 * PURPOSE:
462 * Setup almost everything ready for a new debug session:
463 * DSP modules and EVM board modules.
464 *
465 * USAGE
466 * This routine can be called as:
467 *
468 * Global_Default_Setup_Silent()
469 *
470 * RETURN VALUE
471 * NONE
472 *
473 * REFERENCE
474 *
475 ****************************************************************************/
476 Global_Default_Setup_Silent()
477 {
478 // Only core 0 can set these
479 if (DNUM == 0)
480 {
481 CORE_PLL_INIT_24MHz_to_600MHz();
482 TETRIS_PLL_INIT_24MHZ_to_600MHz();
483 Set_Psc_All_On();
484 UART_PLL_INIT_24MHz_TO_384MHz();
485 NSS_PLL_INIT_24MHz_TO_1000MHz();
486 ICSS_POWERUP_AND_PLL_INIT_24MHz_to_200MHz();
487 DSS_PLL_INIT_24MHZ_to_25MHz();
488 DDR_PLL_INIT_24MHZ_to_200MHz();
489 InitXMC();
490 InitEmif_DDR3A_NO_ECC();
491 }
492 }
494 OnTargetConnect()
495 {
496 Global_Default_Setup_Silent();
497 }
499 Read_PLL_Reg()
500 {
501 unsigned int reg_value = 0xFFFFFFFF;
503 reg_value = BB_REG_FIELD_READ(MAIN_PLL_CTL0_ADDR);
504 GEL_TextOut(" The value of MAIN_PLL_CTL0_ADDR is %x \n",,,,,reg_value);
506 reg_value = BB_REG_FIELD_READ(MAIN_PLL_CTL1_ADDR);
507 GEL_TextOut(" The value of MAIN_PLL_CTL1_ADDR is %x \n",,,,,reg_value);
509 reg_value = BB_REG_FIELD_READ(PLLCTL_ADDR);
510 GEL_TextOut(" The value of PLLCTL_ADDR is %x \n",,,,,reg_value);
512 reg_value = BB_REG_FIELD_READ(SECCTL_ADDR);
513 GEL_TextOut(" The value of SECCTL_ADDR is %x \n",,,,,reg_value);
515 reg_value = BB_REG_FIELD_READ(PLLM_ADDR);
516 GEL_TextOut(" The value of PLLM_ADDR is %x \n",,,,,reg_value);
518 reg_value = BB_REG_FIELD_READ(PLLDIV1_ADDR);
519 GEL_TextOut(" The value of PLLDIV1_ADDR is %x \n",,,,,reg_value);
521 reg_value = BB_REG_FIELD_READ(PLLDIV2_ADDR);
522 GEL_TextOut(" The value of PLLDIV2_ADDR is %x \n",,,,,reg_value);
524 reg_value = BB_REG_FIELD_READ(PLLDIV3_ADDR);
525 GEL_TextOut(" The value of PLLDIV3_ADDR is %x \n",,,,,reg_value);
527 reg_value = BB_REG_FIELD_READ(PLLCMD_ADDR);
528 GEL_TextOut(" The value of PLLCMD_ADDR is %x \n",,,,,reg_value);
530 reg_value = BB_REG_FIELD_READ(PLLSTAT_ADDR);
531 GEL_TextOut(" The value of PLLSTAT_ADDR is %x \n",,,,,reg_value);
533 reg_value = BB_REG_FIELD_READ(PLLDIV4_ADDR);
534 GEL_TextOut(" The value of PLLDIV4_ADDR is %x \n",,,,,reg_value);
536 reg_value = BB_REG_FIELD_READ(PLLDIV5_ADDR);
537 GEL_TextOut(" The value of PLLDIV5_ADDR is %x \n",,,,,reg_value);
539 reg_value = BB_REG_FIELD_READ(PLLDIV6_ADDR);
540 GEL_TextOut(" The value of PLLDIV6_ADDR is %x \n",,,,,reg_value);
542 reg_value = BB_REG_FIELD_READ(PLLDIV7_ADDR);
543 GEL_TextOut(" The value of PLLDIV7_ADDR is %x \n",,,,,reg_value);
545 reg_value = BB_REG_FIELD_READ(PLLDIV8_ADDR);
546 GEL_TextOut(" The value of PLLDIV8_ADDR is %x \n",,,,,reg_value);
547 }
550 //********************************************************************************************************************************
551 //********************************************************************************************************************************
552 //********************************************************************************************************************************
553 //********************************************************************************************************************************
554 /*
555 Set_Pll1() - This function executes the main PLL initialization
556 sequence needed to get the main PLL up after coming out of an initial power up
557 before it is locked or after it is already locked.
559 Index value determines multiplier, divier used and clock reference assumed for
560 output display.
561 */
562 Set_Pll1(int index)
563 {
564 int i, TEMP;
565 unsigned int BYPASS_val;
566 unsigned int BWADJ_val;
567 unsigned int OD_val;
569 float CLKIN_val;
570 unsigned int PLLM_val;
571 unsigned int PLLD_val;
572 unsigned int PLLDIV3_val; //example value for SYSCLK2 (from 6614 spec) Default /2 - Fast Peripherals, (L2, MSMC, DDR3 EMIF, EDMA0...)
573 unsigned int PLLDIV4_val; //example value for SYSCLK3 (from 6614 spec) Default /3 - Switch Fabric
574 unsigned int PLLDIV7_val; //example value for SYSCLK6 (from 6614 spec) Defualt /6 - Slow Peripherals (UART, SPI, I2C, GPIO...)
576 unsigned int debug_info_on;
577 unsigned int delay;
579 if(index == 400){ // 24MHz -> 400 MHz
580 CLKIN_val = 24; // setup CLKIN to 24.00 MHz
581 PLLM_val = 100; // setup PLLM (PLL multiplier)
582 PLLD_val = 1; // setup PLLD (reference divider)
583 OD_val = 6; // setup OD
584 }
585 else if(index == 600){ // 24MHz -> 600 MHz
586 CLKIN_val = 24; // setup CLKIN to 24.00 MHz
587 PLLM_val = 100; // setup PLLM (PLL multiplier)
588 PLLD_val = 1; // setup PLLD (reference divider)
589 OD_val = 4; // setup OD
590 }
591 else if(index == 100){ // 24MHz -> 100 MHz
592 CLKIN_val = 24; // setup CLKIN to 24.00 MHz
593 PLLM_val = 100; // setup PLLM (PLL multiplier)
594 PLLD_val = 2; // setup PLLD (reference divider)
595 OD_val = 12; // setup OD
596 }
597 else if(index == 200){ // 24MHz -> 200 MHz
598 CLKIN_val = 24; // setup CLKIN to 24.00 MHz
599 PLLM_val = 100; // setup PLLM (PLL multiplier)
600 PLLD_val = 1; // setup PLLD (reference divider)
601 OD_val = 12; // setup OD
602 }
604 PLLDIV3_val = 2; // setup PLL output divider 3 to /2
605 PLLDIV4_val = 5; // setup PLL output divider 4 to /3
606 PLLDIV7_val = 6; // setup PLL output divider 7 to /6
608 BYPASS_val = PLL1_SECCTL & ~BYPASS_MASK; // get value of the BYPASS field
609 BWADJ_val = (PLLM_val-1) >> 1; // setup BWADJ to be 1/2 the value of PLLM
611 debug_info_on = 0;
612 delay = 1000; // fix this!
614 /* Step 1: Unlock Boot Config Registers */
615 KICK0 = KICK0_UNLOCK;
616 KICK1 = KICK1_UNLOCK;
618 /* Step 2: Check if SECCTL bypass is low or high indicating what state the Main PLL is currently in. if
619 the Main PLL is in bypass still (not yet setup) execute the following steps. */
621 //Step 1 - pretend to wait 100uS for "PLL to become stable"
623 //Step 2 - Check the status of BYPASS
624 if(BYPASS_val != 0x00000000){ // PLL bypass enabled - Execute PLL setup for PLL fresh out of power on reset
625 if(debug_info_on){
626 GEL_TextOut("Detected PLL bypass enabled: SECCTL[BYPASS] = %x\n",,,,, BYPASS_val);
627 }
629 /* Step 2a: Set MAINPLLCTL1[ENSAT] = 1 - This enables proper biasing of PLL analog circuitry */
630 // MAIN_ENSAT_OFFSET = 6
631 //Step 2a - In MAINPLLCTL1, write ENSAT
632 MAINPLLCTL1 |= (1 << MAIN_ENSAT_OFFSET);
633 if(debug_info_on){
634 GEL_TextOut("(2a) MAINPLLCTL1 = %x\n",,,,, MAINPLLCTL1);
635 }
637 /* Step 2b: Set PLLCTL[PLLEN] = 0 This enables bypass in PLL controller MUX *///PLLEN_OFFSET = 0
638 //Step 2c - In PLLCTL, write PLLEN = 0
639 PLL1_PLLCTL &= ~(1 << PLLEN_OFFSET);
640 if(debug_info_on){
641 GEL_TextOut("(2b) PLLCTL = %x\n",,,,, PLL1_PLLCTL);
642 }
644 /* Step 2c: Set PLLCTL[PLLENSRC] = 0 - This enables PLLEN to control PLL controller MUX */
645 //PLLENSRC_OFFSET = 5
646 //Step 2b - In PLLCTL, write PLLENSRC = 0
647 PLL1_PLLCTL &= ~(1 << PLLENSRC_OFFSET);
648 if(debug_info_on){
649 GEL_TextOut("(2c) PLLCTL = %x\n",,,,, PLL1_PLLCTL);
650 }
652 /* Step 2d: Wait 4 reference clock cycles (slowest of ALTCORE or SYSCLK) to make sure
653 that the PLL controller MUX switches properly to bypass. */
654 if(debug_info_on){
655 GEL_TextOut("(2d) Delay...\n",,,,,);
656 }
657 //Step 2d - Wait 4 cycles of the reference clock (to make sure the PLL controller mux switches properly to the bypass)
658 for(i = 0; i < delay; i++); // this delay is much more than required
660 /* Step 2e: Set SECCTL[BYPASS] = 1 - enables bypass in PLL MUX */
661 //BYPASS_OFFSET = 23
662 //Step 2e - In SECCTL, write BYPASS = 1
663 PLL1_SECCTL |= (1 << BYPASS_OFFSET);
664 if(debug_info_on){
665 GEL_TextOut("(2e) SECCTL = %x\n",,,,, PLL1_SECCTL);
666 }
668 /* Step 2f: Set PLLCTL[PLLPWRDN] = 1 - power down the PLL */
669 //PLLPWRDN_OFFSET = 1
670 //Step 2f - In PLLCTL, write PLLPWRDN = 1
671 PLL1_PLLCTL |= (1 << PLLPWRDN_OFFSET);
672 if(debug_info_on){
673 GEL_TextOut("(2f) PLLCTL = %x\n",,,,, PLL1_PLLCTL);
674 }
676 /* Step 2g: Wait for at least 5us for the PLL to power down */
677 if(debug_info_on){
678 GEL_TextOut("(2g) Delay...\n",,,,,);
679 }
680 //Step 2g - Wait for at least 5 us
681 for(i = 0; i < delay; i++); // this delay is much more than required
683 /* Step 2h: Set PLLCTL[PLLPWRDN] = 0 - Power the PLL back up */
684 //PLLPWRDN_OFFSET = 1
685 //Step 2h - In PLLCTL, write PLLPWRDN = 0
686 PLL1_PLLCTL &= ~(1 << PLLPWRDN_OFFSET);
687 if(debug_info_on){
688 GEL_TextOut("(2h) PLLCTL = %x\n",,,,, PLL1_PLLCTL);
689 }
691 }
692 else{ // PLL bypass disabled - Execute PLL setup for PLL that has previously been locked (skip to Step 3)
694 if(debug_info_on){
695 GEL_TextOut("Detected PLL bypass disabled: SECCTL[BYPASS] = %x\n",,,,, BYPASS_val);
696 }
698 /* Step 3a: Set PLLCTL[PLLEN] = 0 This enables bypass in PLL controller MUX *///PLLEN_OFFSET = 0
700 //!!!Extra Step 2c - In PLLCTL, write PLLEN = 0
701 PLL1_PLLCTL &= ~(1 << PLLEN_OFFSET);
702 if(debug_info_on){
703 GEL_TextOut("(3a) PLLCTL = %x\n",,,,, PLL1_PLLCTL);
704 }
706 /* Step 3b: Set PLLCTL[PLLENSRC] = 0 - This enables PLLEN to control PLL controller MUX */
707 //PLLENSRC_OFFSET = 5
708 //!!!Extra Step 2b - In PLLCTL, write PLLENSRC = 0
709 PLL1_PLLCTL &= ~(1 << PLLENSRC_OFFSET);
710 if(debug_info_on){
711 GEL_TextOut("(3b) PLLCTL = %x\n",,,,, PLL1_PLLCTL);
712 }
714 /* Step 3c: Wait 4 reference clock cycles (slowest of ALTCORE or SYSCLK) to make sure that the PLL controller MUX switches properly to bypass. */
715 //!!!Extra Step 2d - Wait 4 cycles of the reference clock (to make sure the PLL controller mux switches properly to the bypass)
717 if(debug_info_on){
718 GEL_TextOut("(3c) Delay...\n",,,,,);
719 }
720 for(i = 0; i < delay; i++); // this delay is much more than required
722 }
724 //!!!Why was Step 3 MOVED to "STEP 9"? - In PLLCTL, write PLLRST = 1 (PLL is reset)
725 //MM Step 3 PLLCTL, write PLLRST = 1 (PLL is reset) - moved to its correct place from between Step 8e and Step 9 below
726 //Step 3 - PLLCTL, write PLLRST = 1 (PLL is reset)
727 PLL1_PLLCTL |= (1 << PLLRST_OFFSET);
729 /* Step 4: Programming PLLM[5:0] in the PLLM register of the PLL controller and
730 programming PLLM[12:6] in the MAINPLLCTL0 register */
731 //PLLM_val = 52; (1000)
732 PLL1_PLLM &= PLLM_MASK; // clear the PLLM[5:0] bit field
733 //MM 0xFFFFFFC0
734 // 0x0000003F
735 // 0x0000003F 38
736 // 0x3F 26
737 // & 0x33
738 // 0x33
739 //PLL1_PLLM |= 0x26 = 0x00000033
740 //0x33 = 0011 0011 ... 0x33 = 51 decimal (= 52 - 1)
741 //Step 4a - PLLM in PLLM
742 PLL1_PLLM |= ~PLLM_MASK & (PLLM_val - 1); // set the PLLM[5:0] bit field to the 6 LSB of PLLM_val
744 if(debug_info_on){
745 GEL_TextOut("(4)PLLM[PLLM] = %x\n",,,,, PLL1_PLLM);
746 }
747 //MM 0x33 gets wiped away by >>6 - MAINPLLCTL0 cleared PLLM[12:6]
748 //MAIN_PLLM_MASK = 0xFFF80FFF
749 //MAIN_PLLM_OFFSET = 12
753 MAINPLLCTL0 &= MAIN_PLLM_MASK; // clear the PLLM[12:6] bit field
754 //Step 4b - PLLM in MAINPLLCTL0
755 MAINPLLCTL0 |= ~MAIN_PLLM_MASK & (( (PLLM_val - 1) >> 6) << MAIN_PLLM_OFFSET); // set the PLLM[12:6] bit field to the 7 MSB of PLL_val
757 if(debug_info_on){
758 GEL_TextOut("MAINPLLCTL0 = %x\n",,,,, MAINPLLCTL0);
759 }
761 /* Step 5: Programming BWADJ[7:0] in the MAINPLLCTL0 register and BWADJ[11:8] in MAINPLLCTL1 register */
762 MAINPLLCTL0 &= MAIN_BWADJ0_MASK; // clear the MAIN_BWADJ0 bit field
763 //BWADJ_val = (PLLM_val) >> 1;
764 // if PLLM_val = 52: BWADJ_val = 26 >>1 = 0x1A (52/2 = 26)
765 //MAIN_BWADJ0_MASK = 0x00FFFFFF
766 //~MAIN_BWADJ0_MASK = 0xFF000000 0x19 24
767 //Step 5a - BWADJ in MAINPLLCTL0
768 MAINPLLCTL0 |= ~MAIN_BWADJ0_MASK & ((BWADJ_val - 1) << MAIN_BWADJ0_OFFSET); // set the MAIN_BWADJ[7:0] bit field to the 8 LSB of BWADJ_val
769 //~MAIN_BWADJ0_MASK = 0xFF000000
770 if(debug_info_on){
771 GEL_TextOut("(5) MAINPLLCTL0 = %x\n",,,,, MAINPLLCTL0);
772 }
774 MAINPLLCTL1 &= MAIN_BWADJ1_MASK; // clear the MAIN_BWADJ1 bit field
775 //MAIN_BWADJ1_MASK = 0xFFFFFFF0
776 //0x19 wiped away by >> 8 - MAINPLLCTL1 cleared MAIN_BWADJ[11:8] to 4 MSB of BWADJ_val
777 //Step 5b - BWADJ in MAINPLLCTL1
778 MAINPLLCTL1 |= ~MAIN_BWADJ1_MASK & (( (BWADJ_val - 1) >> 8) << MAIN_BWADJ1_OFFSET); // set the MAIN_BWADJ[11:8] bit field to the 4 MSB of BWADJ_val
780 if(debug_info_on){
781 GEL_TextOut("(5) MAINPLLCTL1 = %x\n",,,,, MAINPLLCTL1);
782 }
784 /* Step 6: Programming PLLD[5:0] in the MAINPLLCTL0 register */
785 MAINPLLCTL0 &= MAIN_PLLD_MASK; // clear the PLLD bit field
786 //MAIN_PLLD_MASK = 0xFFFFFFC0
787 //PLLD_val = 1; globally - MAINPLLCTL0 cleared PLLD[5:0]
789 //Step 6 - Program PLLD in MAINPLLCTL0
790 MAINPLLCTL0 |= ~MAIN_PLLD_MASK & (PLLD_val - 1); // set the PLLD[5:0] bit field of PLLD to PLLD_val
792 if(debug_info_on){
793 GEL_TextOut("(6) MAINPLLCTL0 = %x\n",,,,, MAINPLLCTL0);
794 }
796 /* Step 7: Programming OD[3:0] in the SECCTL register */
797 PLL1_SECCTL &= OUTPUT_DIVIDE_MASK; // clear the OD bit field
798 //OD_val = 2; globally
799 //OUTPUT_DIVIDE_OFFSET = 19
800 // OUTPUT_DIVIDE_MASK = 0xFF87FFFF
801 //~OUTPUT_DIVIDE_MASK = 0x00780000
802 //0x00810000 & 0xFF87FFFF = 0x00810000
803 //Step 7 - In SECCTL, write OD = 1 (divide by 2)
804 PLL1_SECCTL |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET; // set the OD[3:0] bit field of PLLD to OD_val
806 if(debug_info_on){
807 GEL_TextOut("(7) SECCTL = %x\n",,,,, PLL1_SECCTL);
808 }
810 /* Step 8: Following steps are needed to change the default output dividers */
812 /* Step 8a: Check that the GOSTAT bit in PLLSTAT is cleared to show that no GO
813 operation is currently in progress*/
814 if(debug_info_on){
815 GEL_TextOut("(8a) Delay...\n",,,,,);
816 }
817 //Step 8a - Check that the GOSTAT bit in PLLSTAT
818 while((PLL1_STAT) & 0x00000001);
820 /* Step 8b: Program the RATIO field in PLLDIVn to the desired new divide-down rate.
821 If RATIO field is changed, the PLL controller will flag the change in the
822 corresponding bit of DCHANGE*/
823 //PLLDIV3_val = 2; // setup PLL output divider 3 to /2
824 //Step 8b - Program the RATIO field in PLLDIVn
825 //PLL1_DIV3 = (PLLDIV3_val-1) | 0x8000; //Set PLLDIV3 //UDAY-TODO: Confirm
826 //In Galileo, only SYSCLK2 and SYSCLK3 are programmable
827 //PLLDIV4_val = 5; // setup PLL output divider 4 to /3
828 //PLL1_DIV4 = (PLLDIV4_val-1) | 0x8000; //Set PLLDIV4
829 //PLLDIV7_val = 6; // setup PLL output divider 7 to /6
830 //PLL1_DIV7 = (PLLDIV7_val-1) | 0x8000; //Set PLLDIV7
831 //MM how come PLL1_DIV7 = 0x00000000 instead of PLLDIV7_val = 0x00008005 ... ??
832 //!!!
834 if(debug_info_on){
835 GEL_TextOut("PLL1_DIV3 = %x\n",,,,, PLL1_DIV3);
836 //GEL_TextOut("PLL1_DIV4 = %x\n",,,,, PLL1_DIV4);
837 GEL_TextOut("PLL1_DIV4 skipped - not programmable in Galileo\n");
838 //GEL_TextOut("PLL1_DIV7 = %x\n",,,,, PLL1_DIV7); //!!!
839 GEL_TextOut("PLL1_DIV7 skipped - not programmable in Galileo\n");
840 }
843 //Step 8c MISSING - Set the respective ALNn bits in ALNCTL to align any SYSCLKs after the GO operation.
845 /* Step 8c: Set GOSET bit in PLLCMD to initiate the GO operation to change the divide
846 values and align the SYSCLKs as programmed */
848 //Step 8d - Set the GOSET bit in PLLCMD
849 PLL1_CMD |= 0x00000001;
851 /*Step 8d/e: Read the GOSTAT bit in PLLSTAT to make sure the bit returns to 0 to
852 indicate that the GO operation has completed */
853 if(debug_info_on){
854 GEL_TextOut("(8d/e) Delay...\n",,,,,);
855 }
856 //Step 8e - Read the GOSTAT bit in PLLSTAT to make sure the bit returns to 0 to indicate that the GO operation has completed.
857 while((PLL1_STAT) & 0x00000001);
859 /* Step 9: Set PLLCTL[PLLRST] = 1 - Assert PLL reset (Previously Step 3)*/
860 //MM woah what? Previously step 3?!
861 //PLLRST_OFFSET = 3
863 //!!!Step 3 - In PLLCTL, write PLLRST = 1 (PLL is reset)
864 //!!!
865 //MM - moved RESET from here to Step 3 above
866 //PLL1_PLLCTL |= (1 << PLLRST_OFFSET);
868 /* Step 10: Wait for the at least 7us for the PLL reset properly (128 CLKIN1 cycles) */
869 if(debug_info_on){
870 GEL_TextOut("(10) Delay...\n",,,,,);
871 }
873 //Step 9 - Wait for at least 7 us
874 for(i=0;i<delay;i++);
876 /* Step 11: Set PLLCTL[PLLRST] = 0 - De-Assert PLL reset */
878 //Step 10 - In PLLCTL, write PLLRST = 0 (PLL reset is released)
879 PLL1_PLLCTL &= ~(1 << PLLRST_OFFSET);
881 /* Step 12: Wait for PLL to lock (2000 CLKIN1 cycles) */
882 if(debug_info_on){
883 GEL_TextOut("(12) Delay...\n",,,,,);
884 }
886 //Step 11 - Wait for at least 500 * CLKIN cycles * (PLLD + 1) (PLL lock time)
887 for(i=0;i<delay;i++);
889 /* Step 13: In SECCTL, write BYPASS = 0 (enable PLL mux to switch to PLL mode) */
890 //BYPASS_OFFSET = 23
894 //Step 12 - In SECCTL, write BYPASS = 0 (enable PLL mux to switch to PLL mode)
895 PLL1_SECCTL &= ~(1 << BYPASS_OFFSET);
896 if(debug_info_on){
897 GEL_TextOut("(13) SECCTL = %x\n",,,,, PLL1_SECCTL);
898 }
900 /* Step 14: In PLLCTL, write PLLEN = 1 to enable PLL mode */
901 //Step 13 - In PLLCTL, write PLLEN = 1 (enable PLL controller mux to switch to PLL mode)
902 PLL1_PLLCTL |= (1 << PLLEN_OFFSET);
903 if(debug_info_on){
904 GEL_TextOut("(14) PLLCTL = %x\n",,,,, PLL1_PLLCTL);
905 }
907 /* Step 15: Lock Boot Config Registers */
908 KICK0 = 0x00000000;
909 KICK1 = 0x00000000;
911 //GEL_TextOut("PLL has been configured (CLKIN * PLLM / PLLD / PLLOD = PLLOUT):\n",,,,,);
912 GEL_TextOut("PLL has been configured (%f MHz * %d / %d / %d = %f MHz)\n",,,,, CLKIN_val, PLLM_val, PLLD_val, OD_val,(CLKIN_val * PLLM_val / PLLD_val / OD_val) );
914 if(index == 400){ // 24MHz -> 400 MHz
915 //GEL_TextOut("PLL has been configured to 400MHz (with ref clock 24MHz, -sysclkp_period 41.6666)\n");
916 }
917 else if(index == 600){ // 24MHz -> 600 MHz
918 //GEL_TextOut("PLL has been configured to 600MHz (with ref clock 24MHz, -sysclkp_period 41.6666)\n");
919 }
921 //By default, Tetris domain is ON
922 //GEL_TextOut("Switching on ARM Core 0\n",,,,,);
923 //TETRIS_CPU0_PDCTL = 0x00000000;
924 //TETRIS_CPU0_PTCMD = 0x00000001;
926 // GEL_TextOut("Switching on ARM Core 1\n",,,,,);
927 // TETRIS_CPU1_PDCTL = 0x00000000;
928 // TETRIS_CPU1_PTCMD = 0x00000001;
930 // GEL_TextOut("Switching on ARM Core 2\n",,,,,);
931 // TETRIS_CPU2_PDCTL = 0x00000000;
932 // TETRIS_CPU2_PTCMD = 0x00000001;
934 // GEL_TextOut("Switching on ARM Core 3\n",,,,,);
935 // TETRIS_CPU3_PDCTL = 0x00000000;
936 // TETRIS_CPU3_PTCMD = 0x00000001;
937 }
939 Set_Tetris_Pll(int index)
940 {
941 unsigned int BWADJ_val;
942 unsigned int OD_val;
943 unsigned int PLLM_val;
944 unsigned int PLLD_val;
945 float CLKIN_val;
946 int i;
948 //By default, Tetris domain is ON
949 //GEL_TextOut("Switching on ARM Core 0\n",,,,,);
950 //TETRIS_CPU0_PDCTL = 0x00000000;
951 //TETRIS_CPU0_PTCMD = 0x00000001;
953 // GEL_TextOut("Switching on ARM Core 1\n",,,,,);
954 // TETRIS_CPU1_PDCTL = 0x00000000;
955 // TETRIS_CPU1_PTCMD = 0x00000001;
957 // GEL_TextOut("Switching on ARM Core 2\n",,,,,);
958 // TETRIS_CPU2_PDCTL = 0x00000000;
959 // TETRIS_CPU2_PTCMD = 0x00000001;
961 // GEL_TextOut("Switching on ARM Core 3\n",,,,,);
962 // TETRIS_CPU3_PDCTL = 0x00000000;
963 // TETRIS_CPU3_PTCMD = 0x00000001;
965 if(index == 200){ // 24 MHz -> 200 MHz
966 CLKIN_val = 24; // setup CLKIN to 24 MHz
967 PLLM_val = 100; // setup PLLM (PLL multiplier)
968 OD_val = 12; // setup OD
969 PLLD_val = 1;
970 }
971 else if(index == 400){ // 24 MHz -> 400 MHz
972 CLKIN_val = 24; // setup CLKIN to 24 MHz
973 PLLM_val = 100; // setup PLLM (PLL multiplier)
974 OD_val = 6; // setup OD
975 PLLD_val = 1;
976 }
977 else if(index == 600){ // 24 MHz -> 600 MHz
978 CLKIN_val = 24; // setup CLKIN to 24 MHz
979 PLLM_val = 100; // setup PLLM (PLL multiplier)
980 OD_val = 4; // setup OD
981 PLLD_val = 1;
982 }
984 BWADJ_val = (PLLM_val-1) >> 1; // setup BWADJ to be 1/2 the value of PLLM
986 /* Step 1: Unlock Boot Config Registers */
987 KICK0 = KICK0_UNLOCK;
988 KICK1 = KICK1_UNLOCK;
990 //Step 1 : Assert SEC PLL Reset
991 SECPLLCTL1 = ((1 << SEC_PLLCTL1_RESET_OFFSET) | (1 << SEC_PLLCTL1_ENSTAT_OFFSET));
993 //Step 2 : Change CLKF/OD/BWADJ etc. for SEC PLL
994 SECPLLCTL0 = ((BWADJ_val << SEC_PLLCTL0_BWADJ_OFFSET) |
995 ((OD_val-1) << SEC_PLLCTL0_OD_OFFSET)|
996 ((PLLM_val-1) << SEC_PLLCTL0_PLLM_OFFSET) |
997 ((PLLD_val-1) << SEC_PLLCTL0_PLLD_OFFSET)
998 );
1000 //Step 3 : Make sure the resets are held for 5us
1001 for(i = 0; i < 200000; i++);
1003 //Step 4 : Remove SEC PLL reset
1004 SECPLLCTL1 = (1 << SEC_PLLCTL1_ENSTAT_OFFSET);
1006 //Step 5 : Wait for PLL to lock (4000 CLKIN1 cycles)
1007 for(i = 0; i < 4000; i++);
1009 //Step 6 : Get the PLL out of Bypass
1010 SECPLLCTL0 &= ~(1 << SEC_PLLCTL0_BYPASS_OFFSET);
1011 //CHIP_MISC1 |= (1 << ARMPLL_ENABLE_OFFSET);
1014 //Step 6 : Lock Boot Config Registers
1015 KICK0 = 0x00000000;
1016 KICK1 = 0x00000000;
1018 GEL_TextOut("ARM PLL has been configured with ref clock 24MHz, -sysclkp_period 41.6666 (%f MHz * %d / %d / %d = %f MHz)\n",,,,, CLKIN_val, PLLM_val, PLLD_val, OD_val, (CLKIN_val * PLLM_val)/OD_val);
1020 }
1022 Set_ICSS_Pll(int index)
1023 {
1025 unsigned int BWADJ_val;
1026 unsigned int OD_val;
1027 unsigned int PLLM_val;
1028 unsigned int PLLD_val;
1029 float CLKIN_val;
1030 int i;
1032 if(index == 200){ // 24 MHz -> 200 MHz
1033 CLKIN_val = 24; // setup CLKIN to 200 MHz
1034 PLLM_val = 250; // setup PLLM (PLL multiplier)
1035 PLLD_val = 3; // setup PLLD (PLL divider)
1036 OD_val = 10; // setup OD
1037 }
1039 BWADJ_val = (PLLM_val-1) >> 1; // setup BWADJ to be 1/2 the value of PLLM
1040 //OD_val = 2; // setup OD to a fixed /2
1042 /* Step 1: Unlock Boot Config Registers */
1043 KICK0 = KICK0_UNLOCK;
1044 KICK1 = KICK1_UNLOCK;
1046 //Step 1 : Assert SEC PLL Reset
1047 ICSSPLLCTL1 = ((1 << SEC_PLLCTL1_RESET_OFFSET) | (1 << SEC_PLLCTL1_ENSTAT_OFFSET));
1049 //Step 2 : Change CLKF/OD/BWADJ etc. for SEC PLL
1050 ICSSPLLCTL0 = ((BWADJ_val << SEC_PLLCTL0_BWADJ_OFFSET) |
1051 ((OD_val-1) << SEC_PLLCTL0_OD_OFFSET)|
1052 ((PLLM_val-1) << SEC_PLLCTL0_PLLM_OFFSET)|
1053 (PLLD_val-1));
1055 //Step 3 : Make sure the resets are held for 5us
1056 for(i = 0; i < 200000; i++);
1058 //Step 4 : Remove SEC PLL reset
1059 ICSSPLLCTL1 &= ~(1 << SEC_PLLCTL1_RESET_OFFSET);
1061 //Step 5 : Wait for PLL to lock (4000 CLKIN1 cycles)
1062 for(i = 0; i < 4000; i++);
1064 //Step 6 : Get the PLL out of Bypass
1065 ICSSPLLCTL0 &= ~(1 << SEC_PLLCTL0_BYPASS_OFFSET);
1068 //Step 6 : Lock Boot Config Registers
1069 //KICK0 = 0x00000000;
1070 // KICK1 = 0x00000000;
1072 GEL_TextOut("ICSS PLL has been configured (%f MHz * %d / %d / %d = %f MHz)\n",,,,, CLKIN_val, PLLM_val, PLLD_val, OD_val, (CLKIN_val * PLLM_val)/(PLLD_val*OD_val));
1074 }
1076 Set_DDR_Pll(int index)
1077 {
1078 unsigned int BWADJ_val;
1079 unsigned int OD_val;
1080 unsigned int PLLM_val;
1081 unsigned int PLLD_val;
1082 float CLKIN_val;
1083 int i;
1085 if(index == 200){ // 24 MHz -> 200 MHz
1086 CLKIN_val = 24; // setup CLKIN to 200 MHz
1087 PLLM_val = 133; // setup PLLM (PLL multiplier)
1088 PLLD_val = 1; // setup PLLD (PLL divider)
1089 OD_val = 16; // setup OD
1090 }
1092 BWADJ_val = (PLLM_val-1) >> 1; // setup BWADJ to be 1/2 the value of PLLM
1094 /* Step 1: Unlock Boot Config Registers */
1095 KICK0 = KICK0_UNLOCK;
1096 KICK1 = KICK1_UNLOCK;
1098 //Step 1 : Assert SEC PLL Reset
1099 DDR3PLLCTL1 = ((1 << SEC_PLLCTL1_RESET_OFFSET) | (1 << SEC_PLLCTL1_ENSTAT_OFFSET));
1101 //Step 2 : Change CLKF/OD/BWADJ etc. for SEC PLL
1102 DDR3PLLCTL0 = ((BWADJ_val << SEC_PLLCTL0_BWADJ_OFFSET) |
1103 ((OD_val-1) << SEC_PLLCTL0_OD_OFFSET)|
1104 ((PLLM_val-1) << SEC_PLLCTL0_PLLM_OFFSET)|
1105 (PLLD_val-1));
1107 //Step 3 : Make sure the resets are held for 5us
1108 for(i = 0; i < 200000; i++);
1110 //Step 4 : Remove SEC PLL reset
1111 DDR3PLLCTL1 &= ~(1 << SEC_PLLCTL1_RESET_OFFSET);
1113 //Step 5 : Wait for PLL to lock (4000 CLKIN1 cycles)
1114 for(i = 0; i < 4000; i++);
1116 //Step 6 : Get the PLL out of Bypass
1117 DDR3PLLCTL0 &= ~(1 << SEC_PLLCTL0_BYPASS_OFFSET);
1119 DDR3MUX = 0x0;
1121 //Step 6 : Lock Boot Config Registers
1122 KICK0 = 0x00000000;
1123 KICK1 = 0x00000000;
1125 GEL_TextOut("DDR PLL has been configured (%f MHz * %d / %d / %d = %f MHz)\n",,,,, CLKIN_val, PLLM_val, PLLD_val, OD_val, (CLKIN_val * PLLM_val)/(PLLD_val*OD_val));
1127 }
1129 Set_UART_Pll(int index)
1130 {
1132 unsigned int BWADJ_val;
1133 unsigned int OD_val;
1134 unsigned int PLLM_val;
1135 unsigned int PLLD_val;
1136 float CLKIN_val;
1137 int i;
1139 if(index == 384){ // 24 MHz -> 200 MHz
1140 CLKIN_val = 24; // setup CLKIN to 200 MHz
1141 PLLM_val = 128; // setup PLLM (PLL multiplier)
1142 PLLD_val = 1; // setup PLLD (PLL divider)
1143 OD_val = 8; // setup OD
1144 }
1146 BWADJ_val = (PLLM_val-1) >> 1; // setup BWADJ to be 1/2 the value of PLLM
1148 /* Step 1: Unlock Boot Config Registers */
1149 KICK0 = KICK0_UNLOCK;
1150 KICK1 = KICK1_UNLOCK;
1152 //Step 1 : Assert SEC PLL Reset
1153 UARTPLLCTL1 = ((1 << SEC_PLLCTL1_RESET_OFFSET) | (1 << SEC_PLLCTL1_ENSTAT_OFFSET));
1155 //Step 2 : Change CLKF/OD/BWADJ etc. for SEC PLL
1156 UARTPLLCTL0 = ((BWADJ_val << SEC_PLLCTL0_BWADJ_OFFSET) |
1157 ((OD_val-1) << SEC_PLLCTL0_OD_OFFSET)|
1158 ((PLLM_val-1) << SEC_PLLCTL0_PLLM_OFFSET)|
1159 (PLLD_val-1));
1161 //Step 3 : Make sure the resets are held for 5us
1162 for(i = 0; i < 200000; i++);
1164 //Step 4 : Remove SEC PLL reset
1165 UARTPLLCTL1 &= ~(1 << SEC_PLLCTL1_RESET_OFFSET);
1167 //Step 5 : Wait for PLL to lock (4000 CLKIN1 cycles)
1168 for(i = 0; i < 4000; i++);
1170 //Step 6 : Get the PLL out of Bypass
1171 UARTPLLCTL0 &= ~(1 << SEC_PLLCTL0_BYPASS_OFFSET);
1173 //Step 6 : Lock Boot Config Registers
1174 //KICK0 = 0x00000000;
1175 // KICK1 = 0x00000000;
1177 GEL_TextOut("UART PLL has been configured (%f MHz * %d / %d / %d = %f MHz)\n",,,,, CLKIN_val, PLLM_val, PLLD_val, OD_val, (CLKIN_val * PLLM_val)/(PLLD_val*OD_val));
1179 }
1181 Set_Msmc_Non_Shared()
1182 {
1183 unsigned int privid;
1185 for (privid = 0; privid < 16; privid++)
1186 {
1187 *(unsigned int*)(SMS_MPAXH_0_0 + (0x40 * privid)) |= 0x00000080;
1188 *(unsigned int*)(SES_MPAXH_0_0 + (0x40 * privid)) |= 0x00000080;
1189 }
1190 }
1191 Set_NSS_Pll(int index)
1192 {
1194 unsigned int BWADJ_val;
1195 unsigned int OD_val;
1196 unsigned int PLLM_val;
1197 unsigned int PLLD_val;
1198 float CLKIN_val;
1199 int i;
1201 if (index == 1000) {
1202 CLKIN_val = 24; // sysclk input is 24 MHz
1203 PLLM_val = 250; // setup PLLM (PLL multiplier)
1204 PLLD_val = 3; // setup PLLD (PLL divider)
1205 OD_val = 2; // setup OD
1206 }
1208 /* Step 1: Unlock Boot Config Registers */
1209 KICK0 = KICK0_UNLOCK;
1210 KICK1 = KICK1_UNLOCK;
1212 //Step 1 : Assert SEC PLL Reset
1213 NSSPLLCTL1 = ((1 << SEC_PLLCTL1_RESET_OFFSET) | (1 << SEC_PLLCTL1_ENSTAT_OFFSET));
1215 BWADJ_val = (PLLM_val-1) >> 1; // setup BWADJ to be 1/2 the value of PLLM
1217 //Step 2 : Change CLKF/OD/BWADJ etc. for SEC PLL
1218 NSSPLLCTL0 = ((BWADJ_val << SEC_PLLCTL0_BWADJ_OFFSET) |
1219 ((OD_val-1) << SEC_PLLCTL0_OD_OFFSET)|
1220 ((PLLM_val-1) << SEC_PLLCTL0_PLLM_OFFSET)|
1221 (PLLD_val-1));
1223 //Step 3 : Make sure the resets are held for 5us
1224 for(i = 0; i < 200000; i++);
1226 //Step 4 : Remove SEC PLL reset
1227 NSSPLLCTL1 &= ~(1 << SEC_PLLCTL1_RESET_OFFSET);
1229 //Step 5 : Wait for PLL to lock (4000 CLKIN1 cycles)
1230 for(i = 0; i < 4000; i++);
1232 //Step 6 : Get the PLL out of Bypass
1233 NSSPLLCTL0 &= ~(1 << SEC_PLLCTL0_BYPASS_OFFSET);
1236 //Step 6 : Lock Boot Config Registers
1237 KICK0 = 0x00000000;
1238 KICK1 = 0x00000000;
1240 GEL_TextOut("NSS PLL has been configured (%f MHz * %d / %d / %d = %f MHz)\n",,,,, CLKIN_val, PLLM_val, PLLD_val, OD_val, (CLKIN_val * PLLM_val)/PLLD_val/OD_val);
1242 }
1244 /*
1245 * Configures the DSS PLL
1246 *
1247 * REFCLK = 24MHz
1248 */
1249 Set_DSS_Pll(int freq)
1250 {
1251 unsigned int PLLM_val = 0; //Reference Multiplier
1252 unsigned int PLLD_val = 0; //Reference Divider
1253 unsigned int OD_val = 0; //Output Divider
1254 unsigned int BWADJ_val, i;
1255 float CLKIN_val;
1256 //unsigned int temp = 0;
1258 if (freq == 148)
1259 {
1260 //148.5 MHz PLL
1261 CLKIN_val = 24; // sysclk input is 24 MHz
1262 PLLM_val = 198;
1263 PLLD_val = 4;
1264 OD_val = 8;
1265 }
1266 if (freq == 74)
1267 {
1268 //74.25 MHz PLL
1269 CLKIN_val = 24; // sysclk input is 24 MHz
1270 PLLM_val = 198;
1271 PLLD_val = 4;
1272 OD_val = 16;
1273 }
1274 if (freq == 9)
1275 { //9 MHz PLL
1276 CLKIN_val = 24; // sysclk input is 24 MHz
1277 PLLM_val = 12;
1278 PLLD_val = 4;
1279 OD_val = 8;
1280 }
1281 if (freq == 25)
1282 { //24.75 MHz PLL (HDMI)
1283 CLKIN_val = 24; // sysclk input is 24 MHz
1284 PLLM_val = 198;
1285 PLLD_val = 12;
1286 OD_val = 16;
1287 }
1289 /* Step 1: Unlock Boot Config Registers */
1290 KICK0 = KICK0_UNLOCK;
1291 KICK1 = KICK1_UNLOCK;
1293 /* Get current CTL0 register contents */
1294 //temp = DSS_PLL_CTL0;
1295 /* Clear settings for the PLL */
1296 //temp &= ~(DSS_PLL_CTL0_BYPASS_MASK | DSS_PLL_CTL0_CLKOD_MASK | DSS_PLL_CTL0_PLLM_MASK | DSS_PLL_CTL0_PLLD_MASK);
1297 /* Set PLL settings */
1298 //temp |= (pllMult << DSS_PLL_CTL0_PLLM_SHIFT) | (pllDiv << DSS_PLL_CTL0_PLLD_SHIFT) | (clkOutDiv << DSS_PLL_CTL0_CLKOD_SHIFT) | (DSS_PLL_CTL0_BYPASS_EN << DSS_PLL_CTL0_BYPASS_SHIFT);
1299 /* Write settings to register */
1300 //DSS_PLL_CTL0 = temp;
1302 //Step 1 : Assert SEC PLL Reset
1303 DSS_PLL_CTL1 = ((1 << SEC_PLLCTL1_RESET_OFFSET) | (1 << SEC_PLLCTL1_ENSTAT_OFFSET));
1305 BWADJ_val = (PLLM_val-1) >> 1; // setup BWADJ to be 1/2 the value of PLLM
1307 //Step 2 : Change CLKF/OD/BWADJ etc. for SEC PLL
1308 DSS_PLL_CTL0 = ((BWADJ_val << SEC_PLLCTL0_BWADJ_OFFSET) |
1309 ((OD_val-1) << SEC_PLLCTL0_OD_OFFSET)|
1310 ((PLLM_val-1) << SEC_PLLCTL0_PLLM_OFFSET)|
1311 (PLLD_val-1));
1313 //Step 3 : Make sure the resets are held for 5us
1314 for(i = 0; i < 200000; i++);
1316 //Step 4 : Remove SEC PLL reset
1317 DSS_PLL_CTL1 &= ~(1 << SEC_PLLCTL1_RESET_OFFSET);
1319 //Step 5 : Wait for PLL to lock (4000 CLKIN1 cycles)
1320 for(i = 0; i < 4000; i++);
1322 //Step 6 : Get the PLL out of Bypass
1323 DSS_PLL_CTL0 &= ~(1 << SEC_PLLCTL0_BYPASS_OFFSET);
1325 //Step 6 : Lock Boot Config Registers
1326 KICK0 = 0x00000000;
1327 KICK1 = 0x00000000;
1329 GEL_TextOut("DSS PLL has been configured (%f MHz * %d / %d / %d = %f MHz)\n",,,,, CLKIN_val, PLLM_val, PLLD_val, OD_val, (CLKIN_val * PLLM_val)/PLLD_val/OD_val);
1331 KICK0 = 0x00000000;
1332 KICK1 = 0x00000000;
1333 }
1337 //*************************************************************************************************
1338 //*************************************************************************************************
1339 //*************************************************************************************************
1340 //*************************************************************************************************
1341 //*************************************************************************************************
1342 //*************************************************************************************************
1345 ///*--------------------------------------------------------------*///
1346 ///* Galileo VDB Function Menu *///
1347 ///*--------------------------------------------------------------*///
1349 ///* Galileo PLL Function *///
1350 menuitem "Galileo PLL Functions";
1352 hotmenu CORE_PLL_INIT_24MHz_to_400MHz()
1353 {
1354 Set_Pll1(400); // call Set_Pll1 with index = 1 -> 24 MHz to 400 MHz operation
1355 }
1357 hotmenu CORE_PLL_INIT_24MHz_to_600MHz()
1358 {
1359 Set_Pll1(600); // call Set_Pll1 with index = 2 -> 24 MHz to 600 MHz operation
1361 }
1363 hotmenu TETRIS_PLL_INIT_24MHZ_to_200MHz()
1364 {
1365 Set_Tetris_Pll(200); // 24 MHz to 200 MHz operation
1366 }
1368 hotmenu TETRIS_PLL_INIT_24MHZ_to_400MHz()
1369 {
1370 Set_Tetris_Pll(400); // 24 MHz to 400 MHz operation
1371 }
1373 hotmenu TETRIS_PLL_INIT_24MHZ_to_600MHz()
1374 {
1375 Set_Tetris_Pll(600); // 24 MHz to 600 MHz operation
1376 }
1378 hotmenu DDR_PLL_INIT_24MHZ_to_200MHz()
1379 {
1380 Set_DDR_Pll(200);
1381 }
1383 hotmenu ICSS_POWERUP_AND_PLL_INIT_24MHz_to_200MHz()
1384 {
1385 Set_ICSS_Pll(200);
1386 }
1388 hotmenu DSS_PLL_INIT_24MHZ_to_148_5MHz()
1389 {
1390 Set_DSS_Pll(148);
1391 }
1393 hotmenu DSS_PLL_INIT_24MHZ_to_74_25MHz()
1394 {
1395 Set_DSS_Pll(74);
1396 }
1398 hotmenu DSS_PLL_INIT_24MHZ_to_9MHz()
1399 {
1400 Set_DSS_Pll(9);
1401 }
1403 hotmenu DSS_PLL_INIT_24MHZ_to_25MHz()
1404 {
1405 Set_DSS_Pll(25);
1406 }
1408 /* Function to program NSS PLL to 1000MHZ from 24MHz input sysclkp */
1409 hotmenu NSS_PLL_INIT_24MHz_TO_1000MHz()
1410 {
1411 Set_NSS_Pll(1000);
1412 }
1414 /* Function to program UART PLL to 384MHZ from 24MHz input sysclkp */
1415 hotmenu UART_PLL_INIT_24MHz_TO_384MHz()
1416 {
1417 Set_UART_Pll(384);
1418 }
1420 hotmenu SET_MSMC_NONSHARED()
1421 {
1422 Set_Msmc_Non_Shared();
1423 }
1425 hotmenu CORE_PLL_READ_REGISTER_VALUES()
1426 {
1427 Read_PLL_Reg();
1428 }
1430 ///* Function to enable CORE PLL observation clock for PLL output *///
1431 hotmenu ENABLE_CORE_PLL_OBSCLK()
1432 {
1433 /* Unlock Chip Level Registers */
1434 KICK0 = KICK0_UNLOCK;
1435 KICK1 = KICK1_UNLOCK;
1437 /* set bit 1 to enable power to the CORE PLL observation clock, clear bit 0 to view the CORE PLL observation (output) clock */
1438 //OBSCLKCTL |= (1 << 1); /* set bit 1 to enable power to the observation clock */
1439 //OBSCLKCTL &= ~(1 << 0); /* clear bit 0 to view the CORE PLL clock */
1440 OBSCLKCTL = 0x201;
1441 PLL1_OCSEL = 0x11;
1443 /* Lock Chip Level Registers */
1444 KICK0 = 0x00000000;
1445 KICK1 = 0x00000000;
1447 GEL_TextOut("CORE PLL observation clock enabled and configured to show CORE PLL output\n");
1448 }
1450 hotmenu ENABLE_TETRIS_PLL_OBSCLK()
1451 {
1452 /* Unlock Chip Level Registers */
1453 KICK0 = KICK0_UNLOCK;
1454 KICK1 = KICK1_UNLOCK;
1455 OBSCLKCTL = 0x803;
1456 /* Lock Chip Level Registers */
1457 KICK0 = 0x00000000;
1458 KICK1 = 0x00000000;
1459 GEL_TextOut("Observation clock enabled and configured to show ARM PLL output\n");
1460 }
1462 hotmenu ENABLE_ICSS_PLL_OBSCLK()
1463 {
1464 /* Unlock Chip Level Registers */
1465 KICK0 = KICK0_UNLOCK;
1466 KICK1 = KICK1_UNLOCK;
1467 OBSCLKCTL = 0x2005;
1468 /* Lock Chip Level Registers */
1469 KICK0 = 0x00000000;
1470 KICK1 = 0x00000000;
1471 GEL_TextOut("Observation clock enabled and configured to show ARM PLL output\n");
1472 }
1474 hotmenu ENABLE_NSS_PLL_OBSCLK()
1475 {
1476 /* Unlock Chip Level Registers */
1477 KICK0 = KICK0_UNLOCK;
1478 KICK1 = KICK1_UNLOCK;
1479 OBSCLKCTL = 0x10008;
1480 /* Lock Chip Level Registers */
1481 KICK0 = 0x00000000;
1482 KICK1 = 0x00000000;
1483 GEL_TextOut("Observation clock enabled and configured to show ARM PLL output\n");
1484 }
1486 hotmenu ENABLE_UART_PLL_OBSCLK()
1487 {
1488 /* Unlock Chip Level Registers */
1489 KICK0 = KICK0_UNLOCK;
1490 KICK1 = KICK1_UNLOCK;
1491 OBSCLKCTL = 0x1004;
1492 /* Lock Chip Level Registers */
1493 KICK0 = 0x00000000;
1494 KICK1 = 0x00000000;
1495 GEL_TextOut("Observation clock enabled and configured to show ARM PLL output\n");
1496 }
1499 /* Function to enable DDR PLL observation clock for PLL output */
1500 hotmenu ENABLE_DSS_PLL_OBSCLK ()
1501 {
1502 /* Unlock Chip Level Registers */
1503 KICK0 = KICK0_UNLOCK;
1504 KICK1 = KICK1_UNLOCK;
1506 /* set bit 1 to enable power to the CORE PLL observation clock, clear bit 0 to view the CORE PLL observation (output) clock */
1507 OBSCLKCTL = 0x402;
1509 /* Lock Chip Level Registers */
1510 KICK0 = 0x00000000;
1511 KICK1 = 0x00000000;
1513 GEL_TextOut("Observation clock enabled and configured to show DSS-UL PLL output\n");
1514 }
1517 /* Function to enable DDR PLL observation clock for PLL output */
1518 hotmenu ENABLE_DDR_PLL_OBSCLK ()
1519 {
1520 /* Unlock Chip Level Registers */
1521 KICK0 = KICK0_UNLOCK;
1522 KICK1 = KICK1_UNLOCK;
1524 /* set bit 1 to enable power to the CORE PLL observation clock, clear bit 0 to view the CORE PLL observation (output) clock */
1525 //OBSCLKCTL |= (1 << 3); /* set bit 3 to enable power to the observation clock */
1526 //OBSCLKCTL |= (1 << 2); /* set bit 2 to view the DDR PLL clock */
1527 OBSCLKCTL = 0x4006;
1529 /* Lock Chip Level Registers */
1530 KICK0 = 0x00000000;
1531 KICK1 = 0x00000000;
1533 GEL_TextOut("DDR PLL observation clock enabled and configured to show DDR PLL output\n");
1534 }
1536 /* Function to release Cortex M3 from reset */
1537 hotmenu RELEASE_CORTEX_M3_RESET ()
1538 {
1539 PMMC_PDCTL |= 0x1;
1540 PMMC_MDCTL = (1 << 8) | 0x3;
1541 PSC_PTCMD = 0x1;
1542 GEL_TextOut("Cortex M3 is released from reset\n");
1543 }
1544 hotmenu UNLOCK_BOOT_CFG_REG ()
1545 {
1546 /* Unlock Chip Level Registers */
1547 KICK0 = KICK0_UNLOCK;
1548 KICK1 = KICK1_UNLOCK;
1549 GEL_TextOut("Unlocked Boot CFG Registers \n");
1550 }
1552 hotmenu LOCK_BOOT_CFG_REG ()
1553 {
1554 KICK0 = 0x00000000;
1555 KICK1 = 0x00000000;
1556 GEL_TextOut("Locked Boot CFG Registers \n");
1557 }
1559 #define XMC_BASE_ADDR (0x08000000)
1560 #define XMPAX2_L (*(int*)(XMC_BASE_ADDR + 0x00000010))
1561 #define XMPAX2_H (*(int*)(XMC_BASE_ADDR + 0x00000014))
1563 xmc_setup()
1564 {
1565 /* mapping for ddr emif registers XMPAX*2 */
1567 XMPAX2_L = 0x121010FF; /* replacement addr + perm */
1568 XMPAX2_H = 0x2101000B; /* base addr + seg size (64KB)*/ //"1B"-->"B" by xj
1569 GEL_TextOut("XMC setup complete.\n");
1570 }
1572 /* DDR3A_BASE_ADDR corresponds to DDR3A_SLV.CONFIG:MSMC_SES.CONFIG
1573 /*--------------------------------------------------------------*/
1574 /* ddr3_setup() */
1575 /* DDR3 initialization */
1576 /*--------------------------------------------------------------*/
1578 #define CHIP_LEVEL_REG 0x02620000
1580 /******************* PLL registers **********************************/
1581 /*Boot cfg registers*/
1582 #define KICK0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0038)
1583 #define KICK1 *(unsigned int*)(CHIP_LEVEL_REG + 0x003C)
1584 #define KICK0_UNLOCK (0x83E70B13)
1585 #define KICK1_UNLOCK (0x95A4F1E0)
1586 #define KICK_LOCK 0
1587 #define TINPSEL *(unsigned int*)(CHIP_LEVEL_REG + 0x0300)
1588 #define TOUTPSEL *(unsigned int*)(CHIP_LEVEL_REG + 0x0304)
1589 #define MAINPLLCTL0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0350) //0x0328)
1590 #define MAINPLLCTL1 *(unsigned int*)(CHIP_LEVEL_REG + 0x0354) //0x032C)
1591 #define MAIN_PLLD_OFFSET 0
1592 #define MAIN_PLLD_MASK 0xFFFFFFC0
1593 #define MAIN_PLLM_OFFSET 12
1594 #define MAIN_PLLM_MASK 0xFFF80FFF
1595 #define MAIN_BWADJ0_OFFSET 24
1596 #define MAIN_BWADJ0_MASK 0x00FFFFFF
1597 #define MAIN_ENSAT_OFFSET 6
1598 #define MAIN_ENSAT_MASK 0xFFFFFFBF
1599 #define MAIN_BWADJ1_OFFSET 0
1600 #define MAIN_BWADJ1_MASK 0xFFFFFFF0
1602 #define OBSCLKCTL *(unsigned int*)(CHIP_LEVEL_REG + 0x0C80)
1604 /* PA PLL Registers */
1605 #define BYPASS_BIT_SHIFT 23
1606 #define CLKF_BIT_SHIFT 6
1607 #define CLKR_BIT_SHIFT 0
1608 #define DEVSTAT (*((unsigned int *) 0x02620020))
1609 #define PAPLLCTL0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0358)
1610 #define PAPLLCTL1 *(unsigned int*)(CHIP_LEVEL_REG + 0x035C)
1611 #define PASSCLKSEL_MASK (1 << 17) /* Tells the configuration of the PASSCLKSEL pin */
1612 #define PA_PLL_BYPASS_MASK (1 << BYPASS_BIT_SHIFT) /* Tells whether the PA PLL is in BYPASS mode or not */
1613 #define PA_PLL_CLKOD_MASK (0x00780000) /* Tells the output divider value for the PA PLL */
1614 #define PA_PLL_CLKF_MASK (0x0007FFC0) /* Tells the multiplier value for the PA PLL */
1615 #define PA_PLL_CLKR_MASK (0x0000003F) /* Tells the divider value for the PA PLL */
1616 #define PA_PLL_RESET_MASK (0x00004000)
1619 #define CHIP_MISC1 *(unsigned int*)(CHIP_LEVEL_REG + 0x0C7C)
1620 #define ARMPLL_ENABLE_OFFSET 13
1623 #define DDR3APLLCTL0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0360)
1624 #define DDR3APLLCTL1 *(unsigned int*)(CHIP_LEVEL_REG + 0x0364)
1625 #define DDR3BPLLCTL0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0368)
1626 #define DDR3BPLLCTL1 *(unsigned int*)(CHIP_LEVEL_REG + 0x036C)
1628 //******************************************************
1629 // PLL 1 definitions (DSP and ARM clock and subsystems)
1630 #define PLL1_BASE 0x02310000
1631 #define PLL1_PLLCTL (*(unsigned int*)(PLL1_BASE + 0x100)) // PLL1 Control
1632 #define PLL1_SECCTL (*(unsigned int*)(PLL1_BASE + 0x108)) // PLL1 Secondary Control
1633 #define PLL1_PLLM (*(unsigned int*)(PLL1_BASE + 0x110)) // PLL1 Multiplier
1634 #define PLL1_DIV1 (*(unsigned int*)(PLL1_BASE + 0x118)) // DIV1 divider
1635 #define PLL1_DIV2 (*(unsigned int*)(PLL1_BASE + 0x11C)) // DIV2 divider
1636 #define PLL1_DIV3 (*(unsigned int*)(PLL1_BASE + 0x120)) // DIV3 divider
1637 #define PLL1_CMD (*(unsigned int*)(PLL1_BASE + 0x138)) // CMD control
1638 #define PLL1_STAT (*(unsigned int*)(PLL1_BASE + 0x13C)) // STAT control
1639 #define PLL1_ALNCTL (*(unsigned int*)(PLL1_BASE + 0x140)) // ALNCTL control
1640 #define PLL1_DCHANGE (*(unsigned int*)(PLL1_BASE + 0x144)) // DCHANGE status
1641 #define PLL1_CKEN (*(unsigned int*)(PLL1_BASE + 0x148)) // CKEN control
1642 #define PLL1_CKSTAT (*(unsigned int*)(PLL1_BASE + 0x14C)) // CKSTAT status
1643 #define PLL1_SYSTAT (*(unsigned int*)(PLL1_BASE + 0x150)) // SYSTAT status
1644 #define PLL1_DIV4 (*(unsigned int*)(PLL1_BASE + 0x160)) // DIV4 divider
1645 #define PLL1_DIV5 (*(unsigned int*)(PLL1_BASE + 0x164)) // DIV5 divider
1646 #define PLL1_DIV6 (*(unsigned int*)(PLL1_BASE + 0x168)) // DIV6 divider
1647 #define PLL1_DIV7 (*(unsigned int*)(PLL1_BASE + 0x16C)) // DIV7 divider
1648 #define PLL1_DIV8 (*(unsigned int*)(PLL1_BASE + 0x170)) // DIV8 divider
1649 #define PLL1_DIV9 (*(unsigned int*)(PLL1_BASE + 0x174)) // DIV9 divider
1650 #define PLL1_DIV10 (*(unsigned int*)(PLL1_BASE + 0x178)) // DIV10 divider
1651 #define PLL1_DIV11 (*(unsigned int*)(PLL1_BASE + 0x17C)) // DIV11 divider
1652 #define PLL1_DIV12 (*(unsigned int*)(PLL1_BASE + 0x180)) // DIV12 divider
1653 #define PLL1_DIV13 (*(unsigned int*)(PLL1_BASE + 0x184)) // DIV13 divider
1654 #define PLL1_DIV14 (*(unsigned int*)(PLL1_BASE + 0x188)) // DIV14 divider
1655 #define PLL1_DIV15 (*(unsigned int*)(PLL1_BASE + 0x18C)) // DIV15 divider
1656 #define PLL1_DIV16 (*(unsigned int*)(PLL1_BASE + 0x190)) // DIV16 divider
1657 #define PLLPWRDN_OFFSET 1
1658 #define PLLPWRDN_MASK 0xFFFFFFFD
1659 #define PLLRST_OFFSET 3
1660 #define PLLRST_MASK 0xFFFFFFF7
1661 #define PLLENSRC_OFFSET 5
1662 #define PLLENSRC_MASK 0xFFFFFFDF
1663 #define PLLEN_OFFSET 0
1664 #define PLLEN_MASK 0xFFFFFFFE
1665 #define OUTPUT_DIVIDE_OFFSET 19
1666 #define OUTPUT_DIVIDE_MASK 0xFF87FFFF
1667 #define BYPASS_OFFSET 23
1668 #define BYPASS_MASK 0xFF7FFFFF
1669 #define PLLM_OFFSET 0
1670 #define PLLM_MASK 0xFFFFFFC0
1671 #define GOSET_OFFSET 0
1672 #define GOSET_MASK 0xFFFFFFFE
1673 #define GOSTAT_OFFSET 0
1674 #define GOSTAT_MASK 0xFFFFFFFE
1676 #define OUTPUT_DIVIDE_OFFSET 19
1677 #define OUTPUT_DIVIDE_MASK 0xFF87FFFF
1679 // ARMPLL definitions
1680 #define SEC_PLLCTL0_PLLM_OFFSET 6
1681 #define SEC_PLLCTL0_PLLM_MASK 0xFFFF003F
1682 #define SEC_PLLCTL0_BWADJ_OFFSET 24
1683 #define SEC_PLLCTL0_BWADJ_MASK 0x00FFFFFF
1684 #define SEC_PLLCTL0_OD_OFFSET 19
1685 #define SEC_PLLCTL0_OD_MASK 0xFF87FFFF
1686 #define SEC_PLLCTL0_BYPASS_OFFSET 23
1687 #define SEC_PLLCTL0_BYPASS_MASK 0xFF7FFFFF
1688 #define SEC_PLLCTL1_RESET_OFFSET 14
1689 #define SEC_PLLCTL1_RESET_MASK 0xFFFFBFFF
1690 #define SEC_PLLCTL1_PWRDWN_OFFSET 15
1691 #define SEC_PLLCTL1_PWRDWN_MASK 0xFFFF7FFF
1692 #define SEC_PLLCTL1_ENSTAT_OFFSET 6
1693 #define SEC_PLLCTL1_ENSTAT_MASK 0xFFFFFFBF
1695 /*----------------DDR3A Register definition---------------------*/
1697 #define DDR3A_BASE_ADDR (0x21010000)
1698 #define DDR3A_STATUS (*(int*)(DDR3A_BASE_ADDR + 0x00000004))
1699 #define DDR3A_SDCFG (*(int*)(DDR3A_BASE_ADDR + 0x00000008))
1700 #define DDR3A_SDRFC (*(int*)(DDR3A_BASE_ADDR + 0x00000010))
1701 #define DDR3A_SDTIM1 (*(int*)(DDR3A_BASE_ADDR + 0x00000018))
1702 #define DDR3A_SDTIM2 (*(int*)(DDR3A_BASE_ADDR + 0x0000001C))
1703 #define DDR3A_SDTIM3 (*(int*)(DDR3A_BASE_ADDR + 0x00000020))
1704 #define DDR3A_SDTIM4 (*(int*)(DDR3A_BASE_ADDR + 0x00000028))
1705 #define DDR3A_ZQCFG (*(int*)(DDR3A_BASE_ADDR + 0x000000C8))
1706 #define DDR3A_TMPALRT (*(int*)(DDR3A_BASE_ADDR + 0x000000CC))
1707 #define DDR3A_DDRPHYC (*(int*)(DDR3A_BASE_ADDR + 0x000000E4))
1708 #define DDR3A_ECC_CTRL (*(int*)(DDR3A_BASE_ADDR + 0x00000110))
1710 #define DDR3A_PHY_CFG_BASE (0x02329000)
1711 #define DDR3A_PIR (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000004))
1712 #define DDR3A_PGCR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000008))
1713 #define DDR3A_PGCR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000000C))
1714 #define DDR3A_PGCR2 (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000008C))
1715 #define DDR3A_PGSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000010))
1716 #define DDR3A_PGSR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000014))
1717 #define DDR3A_PLLCR (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000018))
1718 #define DDR3A_PTR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000001C))
1719 #define DDR3A_PTR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000020))
1720 #define DDR3A_PTR2 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000024))
1721 #define DDR3A_PTR3 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000028))
1722 #define DDR3A_PTR4 (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000002C))
1723 #define DDR3A_DSGCR (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000040))
1724 #define DDR3A_DCR (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000044))
1725 #define DDR3A_MR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000054))
1726 #define DDR3A_MR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000058))
1727 #define DDR3A_MR2 (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000005C))
1728 #define DDR3A_DTCR (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000068))
1729 #define DDR3A_DTPR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000048))
1730 #define DDR3A_DTPR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x0000004C))
1731 #define DDR3A_DTPR2 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000050))
1733 #define DDR3A_ZQ0CR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000184))
1734 #define DDR3A_ZQ1CR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000194))
1735 #define DDR3A_ZQ2CR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x000001A4))
1736 #define DDR3A_ZQ3CR1 (*(int*)(DDR3A_PHY_CFG_BASE + 0x000001B4))
1738 #define DDR3A_DATX8_4 (*(int*)(DDR3A_PHY_CFG_BASE + 0x000002C0))
1739 #define DDR3A_DATX8_5 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000300))
1740 #define DDR3A_DATX8_6 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000340))
1741 #define DDR3A_DATX8_7 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000380))
1742 #define DDR3A_DATX8_8 (*(int*)(DDR3A_PHY_CFG_BASE + 0x000003C0))
1744 #define DDR3_TEST_START_ADDRESS (*(int*)(0x80000000))
1746 #define IODDRM_MASK 0x00000180
1747 #define ZCKSEL_MASK 0x01800000
1748 #define CL_MASK 0x00000072
1749 #define WR_MASK 0x00000E00
1750 #define BL_MASK 0x00000003
1751 #define RRMODE_MASK 0x00040000
1752 #define UDIMM_MASK 0x20000000
1753 #define BYTEMASK_MASK 0x0000FC00
1754 #define MPRDQ_MASK 0x00000080
1755 #define PDQ_MASK 0x00000070
1756 #define NOSRA_MASK 0x08000000
1757 #define ECC_MASK 0x00000001
1758 #define RRMODE_MASK 0x00040000
1760 #define DDR3A_DX0GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x000001C4)) //0x71
1761 #define DDR3A_DX1GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000204)) //0x81
1762 #define DDR3A_DX2GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000244)) //0x91
1763 #define DDR3A_DX3GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000284)) //0xA1
1764 #define DDR3A_DX4GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x000002C4)) //0xB1
1765 #define DDR3A_DX5GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000304)) //0xC1
1766 #define DDR3A_DX6GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000344)) //0xD1
1767 #define DDR3A_DX7GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x00000384)) //0xE1
1768 #define DDR3A_DX8GSR0 (*(int*)(DDR3A_PHY_CFG_BASE + 0x000003C4)) //0xF1
1770 #define TETRIS_BASE 0x01E80000
1772 #define TETRIS_CPU0_PTCMD *(unsigned int*)(TETRIS_BASE + 0x0400)
1773 #define TETRIS_CPU0_PDSTAT *(unsigned int*)(TETRIS_BASE + 0x0404)
1774 #define TETRIS_CPU0_PDCTL *(unsigned int*)(TETRIS_BASE + 0x0408)
1776 #define TETRIS_CPU1_PTCMD *(unsigned int*)(TETRIS_BASE + 0x040C)
1777 #define TETRIS_CPU1_PDSTAT *(unsigned int*)(TETRIS_BASE + 0x0410)
1778 #define TETRIS_CPU1_PDCTL *(unsigned int*)(TETRIS_BASE + 0x0414)
1780 #define TETRIS_CPU2_PTCMD *(unsigned int*)(TETRIS_BASE + 0x0418)
1781 #define TETRIS_CPU2_PDSTAT *(unsigned int*)(TETRIS_BASE + 0x041C)
1782 #define TETRIS_CPU2_PDCTL *(unsigned int*)(TETRIS_BASE + 0x0420)
1784 #define TETRIS_CPU3_PTCMD *(unsigned int*)(TETRIS_BASE + 0x0424)
1785 #define TETRIS_CPU3_PDSTAT *(unsigned int*)(TETRIS_BASE + 0x0428)
1786 #define TETRIS_CPU3_PDCTL *(unsigned int*)(TETRIS_BASE + 0x042C)
1788 #define SECPLLCTL0 *(unsigned int*)(CHIP_LEVEL_REG + 0x0370)
1789 #define SECPLLCTL1 *(unsigned int*)(CHIP_LEVEL_REG + 0x0374)
1790 unsigned int read_val;
1795 //*************************************************************************************************
1796 //*************************************************************************************************
1797 //*************************************************************************************************
1798 //*************************************************************************************************
1799 //*************************************************************************************************
1800 //*************************************************************************************************
1804 ddr3_memory_test ()
1805 {
1806 unsigned int temp;
1807 int i,j;
1809 int *ptr;
1810 unsigned int PATTERN1 = 0xA5A5A5A5;
1811 int TEST_NUM_WORDS = 1000;
1813 int flag = 0;
1815 ptr = (int *)0x80000000;
1817 for (j = 0; j < TEST_NUM_WORDS; j++)
1818 {
1819 ptr[j] = PATTERN1;
1820 }
1822 GEL_TextOut( "DDR3 memory test... starting at 0x80000000\n" );
1824 for (i = 0; i < TEST_NUM_WORDS; i++)
1825 {
1826 temp=ptr[i];
1827 GEL_TextOut("Addr offset: %x Expected: 0xA5A5A5A5 Read: %x \n",,,,, i*4, temp);
1828 if (temp != PATTERN1) {
1829 GEL_TextOut("ERROR!ERROR!ERROR!\n");
1830 flag = 1;
1831 }
1832 }
1834 if (flag)
1835 {
1836 GEL_TextOut("Errors found during memory test.\n");
1837 }
1838 else
1839 {
1840 GEL_TextOut("No errors found during memory test.\n");
1841 }
1842 }
1846 /*----------------------------------------------------- DDR3A only --------------------------------------------------------------------------*/
1847 ddr3A_setup(int ECC_Enable, int DUAL_RANK)
1848 {
1849 unsigned int multiplier = 133;
1850 unsigned int divider = 0;
1851 unsigned int OD_val = 16;
1853 int temp,i;
1854 int delay = 2000;
1855 KICK0 = 0x83E70B13;
1856 KICK1 = 0x95A4F1E0;
1858 // Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
1859 do {
1860 read_val = DDR3A_PGSR0;
1861 } while ((read_val&0x00000001) != 0x00000001);
1863 // Clocks are enabled and frequency is stable---------------------------------------
1865 //DDR3A PLL setup
1866 GEL_TextOut ( "DDR3 PLL Setup ... \n");
1867 //DDR3APLLCTL0 = DDR3APLLCTL0 & 0xFF7FFFFF;
1868 // Set ENSAT = 1
1869 DDR3APLLCTL1 |= 0x00000040;
1870 // Put the PLL in PLL Mode
1871 DDR3APLLCTL0 |= 0x00800000;
1873 // Program the necessary multipliers/dividers and BW adjustments
1874 // Set the divider values
1875 DDR3APLLCTL0 &= ~(0x0000003F);
1876 DDR3APLLCTL0 |= (divider & 0x0000003F);
1878 // Program OD[3:0] in the SECCTL register
1879 DDR3APLLCTL0 &= OUTPUT_DIVIDE_MASK; // clear the OD bit field
1880 DDR3APLLCTL0 |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET; // set the OD[3:0] bit field of PLLD to OD_val
1882 // Set the Multipler values
1883 DDR3APLLCTL0 &= ~(0x0007FFC0);
1884 DDR3APLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );
1885 temp = ((multiplier + 1) >> 1) - 1;
1886 DDR3APLLCTL0 &= ~(0xFF000000);
1887 DDR3APLLCTL0 |= ((temp << 24) & 0xFF000000);
1888 DDR3APLLCTL1 &= ~(0x0000000F);
1889 DDR3APLLCTL1 |= ((temp >> 8) & 0x0000000F);
1891 // In PLL Controller, reset the PLL (bit 13 in DDR3APLLCTL1 register)
1892 DDR3APLLCTL1 |= 0x00004000;
1893 for(i=0;i<delay;i++);
1894 // In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset
1895 DDR3APLLCTL1 &= ~(0x00004000);
1896 for(i=0;i<delay;i++);
1898 // Put the PLL in PLL Mode
1899 DDR3APLLCTL0 &= ~(0x00800000); // ReSet the Bit 23
1900 GEL_TextOut( "DDR3 PLL Setup complete, DDR3A clock now running at 400MHz.\n" );
1901 //DDR3A PLL setup complete ---------------------------------------
1904 /*------------------------------- ECO FIX -----------------------------------------*/
1905 // DDR3 write leveling ECO - Assert & release DDR PHY RESET after DDR PLL setup...
1906 DDR3APLLCTL1 = DDR3APLLCTL1 | 0x80000000; //Assert DDR PHY reset after PLL enabled
1907 for(i=0;i<delay;i++);
1908 DDR3APLLCTL1 = DDR3APLLCTL1 & 0x7FFFFFFF; //Release DDR PHY reset
1910 do { // Poll IDONE after resetting PHY
1911 read_val = DDR3A_PGSR0;
1912 } while ((read_val&0x00000001) != 0x00000001);
1913 /*------------------------- Start PHY Configuration -------------------------------*/
1915 //DDR3A_PGCR1 = 0x0280C487;
1916 //MM from xls - 0x0080C507
1917 //MM - from xls - 0x0080C507
1920 // Program FRQSEL in the PLL Control Register (address offset 0x018).
1921 DDR3A_PLLCR = 0xDC000; //Set FRQSEL=11, for ctl_clk between 166-275MHz
1923 // Program WLSTEP=1, IODDRM=2(DDR3L), and ZCKSEL in the PHY General Configuration Register 1 (address offset 0x00C).
1924 DDR3A_PGCR1 |= (1 << 2); //WLSTEP = 1
1925 DDR3A_PGCR1 &= ~(IODDRM_MASK);
1926 DDR3A_PGCR1 |= (( 2 << 7) & IODDRM_MASK); //MM - changed for DDR3L (changed to 2)
1927 DDR3A_PGCR1 &= ~(ZCKSEL_MASK);
1928 DDR3A_PGCR1 |= (( 1 << 23) & ZCKSEL_MASK);
1931 // Program PHY Timing Parameters Register 0-4 (address offset 0x01C - 0x02C).
1933 DDR3A_PTR0 = 0x42C21590;
1934 DDR3A_PTR1 = 0xD05612C0;
1936 // Maintain default values of Phy Timing Parameters Register 2 in PUB
1938 DDR3A_PTR3 = 0x06C30D40; //0x18061A80;
1939 DDR3A_PTR4 = 0x6413880; //0x0AAE7100;
1941 // Program PDQ, MPRDQ, and BYTEMASK in the DRAM Configuration Register (address offset 0x044).
1942 // All other fields must be left at their default values.
1944 DDR3A_DCR &= ~(PDQ_MASK); //PDQ = 0
1945 DDR3A_DCR &= ~(MPRDQ_MASK); //MPRDQ = 0
1946 DDR3A_DCR &= ~(BYTEMASK_MASK);
1947 DDR3A_DCR |= (( 1 << 10) & BYTEMASK_MASK);
1949 if(DUAL_RANK==1){
1950 //Assumes Address Mirrored DIMM
1951 DDR3A_DCR &= ~(NOSRA_MASK);
1952 DDR3A_DCR |= (( 1 << 27) & NOSRA_MASK);
1953 DDR3A_DCR &= ~(UDIMM_MASK);
1954 DDR3A_DCR |= (( 1 << 29) & UDIMM_MASK);
1955 }
1957 // Program DRAM Timing Parameters Register 0-2 (address offset 0x048 - 0x050).
1958 DDR3A_DTPR0 = 0x550F6644; //MM - calculated: 0x550F6644, orig: 0x50CE6644
1959 DDR3A_DTPR1 = 0x328341E0; //MM - calculated: 0x328341E0, orig: 0x32834180 //Increase tWLO to 12
1960 DDR3A_DTPR2 = 0x50022A00;
1963 // Program BL=0, CL, WR, and PD=1 in the Mode Register 0 (address offset 0x054).
1964 // All other fields must be left at their default values.
1965 DDR3A_MR0 = 0x00001430; //MM - calculated: 0x00001430, orig: 0x00001420 //-CL - 6, CWL - 5
1968 // Program DIC, RTT, and TDQS in the Mode Register 1 (address offset 0x058).
1969 // All other fields must be left at their default values.
1971 DDR3A_MR1 = 0x00000006;
1973 // Program Mode Register 2 (address offset 0x05C).
1974 // Maintaining default values of Program Mode Register 2
1975 //DDR3A_MR2 = 0x00000018;
1977 // Program DTMPR=1, DTEXD, DTEXG, RANKEN=1 or 3, and RFSHDT=7 in the Data Training Configuration Register (address offset 0x068).
1978 // All other fields must be left at their default values.
1979 if(DUAL_RANK==1){
1980 DDR3A_DTCR = 0x730035C7; //Dual-rank
1981 }
1982 else{
1983 DDR3A_DTCR = 0x710035C7; //Single-rank
1984 }
1985 // Program tREFPRD=(5*tREFI/ddr_clk_period) in the PHY General Configuration Register 2 (address offset 0x08C).
1986 //All other fields must be left at their default values.
1988 DDR3A_PGCR2 = 0x00F03D09; //NOBUB = 0, FXDLAT = 0
1989 //DDR3A_PGCR2 = 0x00F83D09; //NOBUB = 0, FXDLAT = 1
1991 //Set Impedence Register and DFIPU0=1
1992 DDR3A_ZQ0CR1 = 0x0001005D;
1993 DDR3A_ZQ1CR1 = 0x0001005B;
1994 DDR3A_ZQ2CR1 = 0x0001005B;
1997 // Re-trigger PHY initialization in DDR PHY through the VBUSP interface.
1998 // Program 0x00000033 to the PHY Initialization Register (address offset 0x004) to re-trigger PLL, ZCAL, and DCAL initialization.
2000 DDR3A_PIR = 0x00000033;
2002 // Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
2003 do {
2004 read_val = DDR3A_PGSR0;
2005 } while ((read_val&0x00000001) != 0x00000001);
2007 //---------------------------------------------------------------------------------------------------------
2009 if(ECC_Enable == 0)
2010 {
2011 read_val = DDR3A_DATX8_4;
2012 DDR3A_DATX8_4 = read_val & 0xFFFFFFFE; //Disable ECC byte lane
2013 }
2015 read_val = DDR3A_DATX8_5;
2016 DDR3A_DATX8_5 = read_val & 0xFFFFFFFE; //Disable BL5 byte lane - not present in K2G
2018 read_val = DDR3A_DATX8_6;
2019 DDR3A_DATX8_6 = read_val & 0xFFFFFFFE; //Disable BL6 byte lane - not present in K2G
2021 read_val = DDR3A_DATX8_7;
2022 DDR3A_DATX8_7 = read_val & 0xFFFFFFFE; //Disable BL7 byte lane - not present in K2G
2024 read_val = DDR3A_DATX8_8;
2025 DDR3A_DATX8_8 = read_val & 0xFFFFFFFE; //Disable BL8 byte lane - not present in K2G
2027 // Trigger DDR3 initialization and leveling/training in DDR PHY through the VBUSP interface.
2028 // If using a 16-bit wide DDR interface, program DXEN=0 in the DATX8 2-7 General Configuration Registers (address offsets 0x240, 0x280, 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
2029 // If using a 32-bit wide DDR interface, program DXEN=0 in the DATX8 4-7 General Configuration Registers (address offsets 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
2030 // If ECC is not required, program DXEN=0 in the DATX8 8 General Configuration Register (address offset 0x3C0) to disable the leveling/training for the ECC byte lane.
2031 // NOTE: Setup supports 64-bit by default, ECC enable by default.
2033 // Program 0x0000XF81 to the PHY Initialization Register (address offset 0x004) to trigger DDR3 initialization and leveling/training sequences
2034 //DDR3A_PIR = 0x0000FF81; //WLADJ - ON
2035 DDR3A_PIR = 0x00000F81; //WLADJ - ON
2036 //DDR3A_PIR = 0x00000781; //WLADJ - OFF
2039 //---------------------------------------------------------------------------------------------------------
2041 // Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
2042 do {
2043 read_val = DDR3A_PGSR0;
2044 } while ((read_val&0x00000001) != 0x00000001);
2047 /* End PHY Configuration */
2049 if(ECC_Enable==1)
2050 {
2051 //Enable ECC
2052 //0xB0000000: ECC_EN=1, ECC_VERIFY_EN=1, RMW_EN=1
2053 //0x50000000: ECC_EN=1, ECC_VERIFY_EN=0, RMW_EN=1
2054 DDR3A_ECC_CTRL = 0xB0000000;
2055 read_val = DDR3A_ECC_CTRL;
2056 if(read_val!=0xB0000000){
2057 GEL_TextOut("\nIncorrect data written to DDR3A_ECC_CTRL..");
2058 }
2059 }
2061 //---------------------------------------------------------------------------------------------------------
2062 /* START EMIF INITIALIZATION
2063 ++++++++++++++++++SDCFG Register Calculation+++++++++++++++++++
2064 | 31 - 29 | 28 |27 - 25 | 24 | 23 - 22| 21 - 17 |
2065 |SDRAM_TYPE|Rsvd|DDR_TERM| DDQS | DYN_ODT| Rsvd |
2066 | 0x011 | 0 | 0x011 | 0x1 | 0x00 | 0x0 |
2068 | 16-14 |13 - 12 | 11 - 8 | 7 |6 - 5 | 4 | 3 | 2 | 1 - 0 |
2069 | CWL | NM | CL | Rsvd |IBANK | Rsvd|EBANK| Rsvd|PAGE_SIZE|
2070 | 0x11 | 0x01 | 0x1110 | 0x0 | 0x11 | 0x0 | 0 | 0 | 0x10 |
2071 SDCFG = 0x0110 0011 0010 0010 0011 0011 1011 0010
2072 SDCFG = 0x6700486A;//0x63223332
2074 SDRAM_TYPE = 3
2075 DDR_TERM = 3 (RZQ/4 = 1; RZQ/6=3)
2076 DDQS = 1
2077 DYN_ODT = 0
2079 CWL = 3 (CWL5=0; CWL6=1; CWL7=2; CWL8=3)
2080 NM = 1 (64-bit=0, 32-bit=1, 16-bit=2)
2081 CL = 14 (CL5=2; CL6=4; CL7=6; CL8=8; CL9=10; CL10=12; CL11=14)
2082 IBANK = 3 (8bank)
2083 EBANK = 0 (0 - pad_cs_o_n[0] , 1 - pad_cs_o_n[1:0])
2084 PAGE_SIZE = 2 (1024page-size=2; 2048page-size=3)
2085 */
2086 /* Start DDR3A EMIF Configuration */
2087 // Configure the EMIF through the VBUSM interface.
2088 // Program all EMIF MMRs.
2090 if(DUAL_RANK==1){
2091 DDR3A_SDCFG = 0x6200046A; //Dual-rank
2092 }
2093 else{
2094 DDR3A_SDCFG = 0x62005662; //Single-rank, 32-bit //MM - calculated: 0x62005662, orig: 0x62000462 (orig,NM=01:62001462)
2095 }
2097 DDR3A_SDTIM1 = 0x0A385033; //MM - calculated: 0x0A385033, orig: 0x0A384C23
2098 DDR3A_SDTIM2 = 0x00001CA5;
2099 DDR3A_SDTIM3 = 0x21ADFF32;
2100 DDR3A_SDTIM4 = 0x533F067F;
2102 if(DUAL_RANK==1){
2103 DDR3A_ZQCFG = 0xF0073200; //Dual-rank
2104 }
2105 else{
2106 DDR3A_ZQCFG = 0x70073200; //Single-rank
2107 }
2109 //8.b. Program reg_initref_dis=0 in the SDRAM Refresh Control Register (address offset 0x10).
2110 DDR3A_SDRFC = 0x00000C34;
2112 GEL_TextOut("DDR3A initialization complete \n");
2113 /* End DDR3A EMIF Configuration */
2115 }
2120 /*--------------------------------------------------------------*/
2121 /* TCI66x MENU */
2122 /*--------------------------------------------------------------*/
2124 menuitem "Generic Functions";
2126 /****************************************************************************
2127 *
2128 * NAME
2129 * Global_Default_Setup
2130 *
2131 * PURPOSE:
2132 * Setup almost everything ready for a new debug session:
2133 * DSP modules and EVM board modules.
2134 *
2135 * USAGE
2136 * This routine can be called as:
2137 *
2138 * Global_Default_Setup()
2139 *
2140 * RETURN VALUE
2141 * NONE
2142 *
2143 * REFERENCE
2144 *
2145 ****************************************************************************/
2146 hotmenu Global_Default_Setup()
2147 {
2148 GEL_TextOut( "Global Default Setup...\n" );
2149 Global_Default_Setup_Silent();
2150 GEL_TextOut( "Global Default Setup... Done.\n" );
2151 }
2153 // hotmenu Reset()
2154 // {
2155 // GEL_Reset();
2156 // }
2158 hotmenu InitXMC()
2159 {
2160 xmc_setup();
2161 }
2163 hotmenu K2G_TakeDSPOutofReset()
2164 {
2165 K2G_out_of_reset();
2166 }
2168 menuitem "DDR3 Functions";
2171 // hotmenu InitEmif_DDR3A_ECC_DUAL_RANK(){
2172 // ddr3A_setup(1,1);
2173 // }
2175 // hotmenu InitEmif_DDR3A_NO_ECC_DUAL_RANK(){
2176 // ddr3A_setup(0,1);
2177 // }
2179 hotmenu InitEmif_DDR3A_ECC()
2180 {
2181 ddr3A_setup(1,0);
2182 }
2184 hotmenu InitEmif_DDR3A_NO_ECC()
2185 {
2186 ddr3A_setup(0,0);
2187 }
2189 menuitem "Tests";
2191 hotmenu ddr3_write_read_test()
2192 {
2193 ddr3_memory_test ();
2194 }
2196 /****************************************************************************
2197 *
2198 * NAME
2199 * Set_PSC_State
2200 *
2201 * PURPOSE:
2202 * Set a new power state for the specified domain id in a power controler
2203 * domain. Wait for the power transition to complete.
2204 *
2205 * USAGE
2206 * This routine can be called as:
2207 *
2208 * Set_PSC_State(unsigned int pd,unsigned int id,unsigned int state)
2209 *
2210 * pd - (i) power domain.
2211 *
2212 * id - (i) module id to use for module in the specified power domain
2213 *
2214 * state - (i) new state value to set
2215 * 0 = RESET
2216 * 1 = SYNC RESET
2217 * 2 = DISABLE
2218 * 3 = ENABLE
2219 *
2220 * RETURN VALUE
2221 * 0 if ok, !=0 for error
2222 *
2223 * REFERENCE
2224 *
2225 ****************************************************************************/
2226 Set_PSC_State(unsigned int pd,unsigned int id,unsigned int state)
2227 {
2228 unsigned int* mdctl;
2229 unsigned int* mdstat;
2230 unsigned int* pdctl;
2231 int ret=0;
2233 // Only core0 can set PSC
2234 if (DNUM == 0)
2235 {
2236 mdctl = ( unsigned int* )(PSC_MDCTL_BASE + ( 4 * id ));
2237 mdstat = ( unsigned int* )( PSC_MDSTAT_BASE + ( 4 * id ));
2238 pdctl = ( unsigned int* )(PSC_PDCTL_BASE + ( 4 * pd ));
2240 // If state is already set, do nothing
2241 if ( ( *mdstat & 0x1f ) == state )
2242 {
2243 return(0);
2244 }
2246 // Wait for GOSTAT to clear
2247 Set_Timeout(GTIMEOUT);
2248 while( Get_Timeout() && (PSC_PTSTAT & (0x1 << pd)) != 0 );
2250 // Check if we got timeout error while waiting
2251 if (!Get_Timeout())
2252 {
2253 GEL_TextOut( "Set_PSC_State... Timeout Error #01 pd=%d, md=%d!\n",,2,,,pd,id);
2254 ret=1;
2255 }
2256 else
2257 {
2258 // Set power domain control
2259 *pdctl = (*pdctl) | 0x00000001;
2261 // Set MDCTL NEXT to new state
2262 *mdctl = ((*mdctl) & ~(0x1f)) | state;
2264 // Start power transition by setting PTCMD GO to 1
2265 PSC_PTCMD = (PSC_PTCMD) | (0x1<<pd);
2267 // Wait for PTSTAT GOSTAT to clear
2268 Set_Timeout(GTIMEOUT);
2269 while( Get_Timeout() && (PSC_PTSTAT & (0x1 << pd)) != 0 );
2271 // Check if we got timeout error while waiting
2272 if (!Get_Timeout())
2273 {
2274 GEL_TextOut( "Set_PSC_State... Timeout Error #02 pd=%d, md=%d!\n",,2,,,pd,id);
2275 ret=2;
2276 }
2277 else
2278 {
2279 // Verify state changed
2280 Set_Timeout(GTIMEOUT);
2281 while(Get_Timeout() && ( *mdstat & 0x1f ) != state );
2283 // Check if we got timeout error while waiting
2284 if (!Get_Timeout())
2285 {
2286 GEL_TextOut( "Set_PSC_State... Timeout Error #03 pd=%d, md=%d!\n",,2,,,pd,id);
2287 ret=3;
2288 }
2289 }
2290 }
2292 // Kill the currently running timeout
2293 Kill_Timeout();
2294 }
2295 else
2296 {
2297 GEL_TextOut("DSP core #%d cannot set PSC.\n",,2,,,DNUM);
2298 }
2300 return(ret);
2301 }
2303 /****************************************************************************
2305 *
2306 * NAME
2307 * K2G_out_of_reset
2308 *
2309 * PURPOSE:
2310 * This routine brings the C66x core out of reset after booting Linux, or at the u-boot prompt.
2311 * These steps are necessary in to order to load an application on the C66x core,
2312 * without interfering with the operation of Linux running on the A15.
2313 *
2314 * USAGE
2315 * This routine can be called as:
2316 *
2317 * K2G_out_of_reset();
2318 *
2319 *
2320 * RETURN VALUE
2321 * NONE
2322 *
2323 * REFERENCE
2324 *
2326 ****************************************************************************/
2327 K2G_out_of_reset()
2328 {
2329 GEL_TextOut("\nTaking K2G DSP 0 out of reset\n");
2330 WR_MEM_32(KS2_PDCTL8, 0x1);
2331 WR_MEM_32(KS2_MDCTL18, 0x103);
2332 GEL_TextOut("\nDone taking K2G DSP 0 out of reset!\n");
2333 }
2335 /****************************************************************************
2336 *
2337 * NAME
2338 * Get_Timeout
2339 *
2340 * PURPOSE:
2341 * Query the running state of a timeout period started by Set_Timeout.
2342 * (see Set_Timeout for more info).
2343 *
2344 * USAGE
2345 * This routine can be called as:
2346 *
2347 * Get_Timeout()
2348 *
2349 * RETURN VALUE
2350 * 0:expired, 1:running
2351 *
2352 * REFERENCE
2353 *
2354 ****************************************************************************/
2355 Get_Timeout()
2356 {
2357 if (!_GEL_Global_Timeout1)
2358 {
2359 // Cancel the current timer
2360 GEL_CancelTimer(TIMEOUT_ID);
2361 }
2363 // Return the global timeout status 1=running, 0=expired
2364 return _GEL_Global_Timeout1;
2365 }
2367 /****************************************************************************
2368 *
2369 * NAME
2370 * Kill_Timeout
2371 *
2372 * PURPOSE:
2373 * Cancel a running timeout period before it expires
2374 * (see Set_Timeout for more info).
2375 *
2376 * USAGE
2377 * This routine can be called as:
2378 *
2379 * Kill_Timeout()
2380 *
2381 * RETURN VALUE
2382 * NONE
2383 *
2384 * REFERENCE
2385 *
2386 ****************************************************************************/
2387 Kill_Timeout()
2388 {
2389 // Cancel the current timer
2390 GEL_CancelTimer(TIMEOUT_ID);
2392 // The timeout period is expired
2393 _GEL_Global_Timeout1=0;
2394 }
2396 /****************************************************************************
2397 *
2398 * NAME
2399 * _Timeout_Callback
2400 *
2401 * PURPOSE:
2402 * Internal Callback function used by Set_timeout
2403 * (see Set_Timeout for more info).
2404 *
2405 * USAGE
2406 * This routine must not be called by itself.
2407 *
2408 * RETURN VALUE
2409 * NONE
2410 *
2411 * REFERENCE
2412 *
2413 ****************************************************************************/
2414 _Timeout_Callback()
2415 {
2416 // The timeout period is expired
2417 _GEL_Global_Timeout1=0;
2418 }
2419 /****************************************************************************
2420 *
2421 * NAME
2422 * Set_Timeout
2423 *
2424 * PURPOSE:
2425 * Starts a timeout period of msec. The running timeout period can be
2426 * query with Get_Timeout. To kill a running timeout before the end,
2427 * call Kill_Timeout. Only one timeout period can be used at any time.
2428 * A timeout period can be used to measure a period of time while doing
2429 * anything else. Not accurate, sets timer at least as big as desired.
2430 *
2431 * USAGE
2432 * This routine can be called as:
2433 *
2434 * Set_Timeout(msec)
2435 *
2436 * msec - (i) timeout period in msec (not very precise < sec range)
2437 *
2438 * RETURN VALUE
2439 * NONE
2440 *
2441 * REFERENCE
2442 *
2443 ****************************************************************************/
2444 Set_Timeout(msec)
2445 {
2446 // Cancel the current timer if not already expired
2447 GEL_CancelTimer(TIMEOUT_ID);
2449 // Starts the timeout period
2450 _GEL_Global_Timeout1=1;
2452 // Setup a callback routine with specified timeout
2453 GEL_SetTimer(msec, TIMEOUT_ID, "_Timeout_Callback()");
2454 }
2456 /****************************************************************************
2457 *
2458 * NAME
2459 * Set_Psc_All_On
2460 *
2461 * PURPOSE:
2462 * Enable all PSC modules and DSP power domains on ALWAYSON, and wait
2463 * for these power transitions to complete.
2464 *
2465 * USAGE
2466 * This routine can be called as:
2467 *
2468 * Set_Psc_All_On()
2469 *
2470 * RETURN VALUE
2471 * NONE
2472 *
2473 * REFERENCE
2474 *
2475 ****************************************************************************/
2476 hotmenu Set_Psc_All_On( )
2477 {
2478 unsigned int i=0;
2480 // Only core0 can set PSC
2481 if (DNUM == 0)
2482 {
2483 GEL_TextOut( "Power on all PSC modules and DSP domains... \n");
2484 Set_PSC_State(PD1, LPSC_PMMC, PSC_ENABLE);
2485 Set_PSC_State(PD1, LPSC_DEBUG, PSC_ENABLE);
2486 Set_PSC_State(PD2, LPSC_NSS, PSC_ENABLE);
2487 Set_PSC_State(PD3, LPSC_SA, PSC_ENABLE);
2488 Set_PSC_State(PD5, LPSC_SYS_COMP, PSC_ENABLE);
2489 Set_PSC_State(PD5, LPSC_QSPI, PSC_ENABLE);
2490 Set_PSC_State(PD5, LPSC_MMC, PSC_ENABLE);
2491 Set_PSC_State(PD5, LPSC_GPMC, PSC_ENABLE);
2492 Set_PSC_State(PD5, LPSC_MLB, PSC_ENABLE);
2493 Set_PSC_State(PD5, LPSC_EHRPWM, PSC_ENABLE);
2494 Set_PSC_State(PD5, LPSC_EQEP, PSC_ENABLE);
2495 Set_PSC_State(PD5, LPSC_ECAP, PSC_ENABLE);
2496 Set_PSC_State(PD5, LPSC_MCASP, PSC_ENABLE);
2497 Set_PSC_State(PD7, LPSC_MSMC, PSC_ENABLE);
2498 Set_PSC_State(PD11, LPSC_ICSS, PSC_ENABLE);
2499 Set_PSC_State(PD12, LPSC_DSS, PSC_ENABLE);
2500 Set_PSC_State(PD13, LPSC_PCIE, PSC_ENABLE);
2501 Set_PSC_State(PD14, LPSC_USB_0, PSC_ENABLE);
2502 Set_PSC_State(PD14, LPSC_USB_1, PSC_ENABLE);
2503 Set_PSC_State(PD15, LPSC_DDR3, PSC_ENABLE);
2505 GEL_TextOut( "Power on PCIE PSC modules and DSP domains... Done.\n" );
2506 }
2507 else
2508 {
2509 GEL_TextOut("DSP core #%d cannot set PSC.\n",,2,,,DNUM);
2510 }
2511 }
2514 #define MDIO_CTL *(unsigned int*)(0x4200F00 + 0x04)
2515 #define MDIO_PHY_REG *(unsigned int*)(0x4200F00 + 0x80)
2518 hotmenu MDIO_Init()
2519 {
2520 MDIO_CTL = 0x411400ff;
2521 GEL_TextOut( "MDIO is enabled\n");
2522 }
2524 hotmenu MDIO_Set_GB_Loopback()
2525 {
2526 MDIO_PHY_REG = 0xc0004140;
2527 GEL_TextOut( "PHY reg0 is set to 0x4140.\n");
2528 MDIO_PHY_REG = 0xc1201300;;
2529 GEL_TextOut( "PHY reg9 is set to 0x1300.\n");
2530 }
2535 /* GEL file to load microphone files */
2537 #define MIC1PATH "$(GEL_file_dir)/t8/y16L8g3m7090_1.pcm"
2538 #define MIC2PATH "$(GEL_file_dir)/t8/y16L8g3m7090_2.pcm"
2539 #define MIC3PATH "$(GEL_file_dir)/t8/y16L8g3m7090_3.pcm"
2540 #define MIC4PATH "$(GEL_file_dir)/t8/y16L8g3m7090_4.pcm"
2541 #define MIC5PATH "$(GEL_file_dir)/t8/y16L8g3m7090_5.pcm"
2542 #define MIC6PATH "$(GEL_file_dir)/t8/y16L8g3m7090_6.pcm"
2543 #define MIC7PATH "$(GEL_file_dir)/t8/y16L8g3m7090_7.pcm"
2544 #define MIC8PATH "$(GEL_file_dir)/t8/y16L8g3m7090_8.pcm"
2546 #define OUTPUTPATH "$(GEL_file_dir)/t8/fileOutput.bin"
2548 BFLoadMic(buffer,micpath)
2549 {
2550 GEL_MemoryLoad(buffer,0,160,micpath,32);
2551 }
2553 BFSaveMic(buffer,num, micpath)
2554 {
2555 GEL_MemorySave(buffer,0,num,micpath,8,0,32);
2556 }
2558 menuitem "Microphone Load Functions";
2560 dialog BFLoadOneMic(buffer "Buffer Address",micpath "Microphone File Path")
2561 {
2562 GEL_TextOut("Loading %s\n","",,,,micpath);
2563 BFLoadMic(buffer,micpath);
2564 }
2566 hotmenu BFLoadMic1()
2567 {
2568 GEL_TextOut("Loading %s\n","",,,,MIC1PATH);
2569 BFLoadMic(filBuf0,MIC1PATH);
2570 }
2572 hotmenu BFLoadMic2()
2573 {
2574 GEL_TextOut("Loading %s\n","",,,,MIC2PATH);
2575 BFLoadMic(filBuf1,MIC2PATH);
2576 }
2578 hotmenu BFLoadMic3()
2579 {
2580 GEL_TextOut("Loading %s\n","",,,,MIC3PATH);
2581 BFLoadMic(filBuf2,MIC3PATH);
2582 }
2584 hotmenu BFLoadMic4()
2585 {
2586 GEL_TextOut("Loading %s\n","",,,,MIC4PATH);
2587 BFLoadMic(filBuf3,MIC4PATH);
2588 }
2590 hotmenu BFLoadMic5()
2591 {
2592 GEL_TextOut("Loading %s\n","",,,,MIC5PATH);
2593 BFLoadMic(filBuf4,MIC5PATH);
2594 }
2596 hotmenu BFLoadMic6()
2597 {
2598 GEL_TextOut("Loading %s\n","",,,,MIC6PATH);
2599 BFLoadMic(filBuf5,MIC6PATH);
2600 }
2602 hotmenu BFLoadMic7()
2603 {
2604 GEL_TextOut("Loading %s\n","",,,,MIC7PATH);
2605 BFLoadMic(filBuf6,MIC7PATH);
2606 }
2608 hotmenu BFLoadMic8()
2609 {
2610 GEL_TextOut("Loading %s\n","",,,,MIC8PATH);
2611 BFLoadMic(filBuf7,MIC8PATH);
2612 }
2614 hotmenu BFLoadMicAll()
2615 {
2616 BFLoadMic1();
2617 BFLoadMic2();
2618 BFLoadMic3();
2619 BFLoadMic4();
2620 BFLoadMic5();
2621 BFLoadMic6();
2622 BFLoadMic7();
2623 BFLoadMic8();
2624 GEL_TextOut("Done Loading Microphones\n");
2625 }
2627 menuitem "Microphone Save Functions";
2629 hotmenu BFSaveOutput()
2630 {
2631 GEL_TextOut("Saving %s\n","",,,,OUTPUTPATH);
2632 BFSaveMic(filOutBuf0,filConfig.outlen/2,OUTPUTPATH);
2633 }