16186f925c3280c54c512b9ee0304936568f7d77
[processor-sdk/audio-preprocessing.git] / realtime_demo_bios / k2g / src / mcasp_osal.c
1 #include <mcasp_osal.h>\r
2 #include <mcasp_drv.h>\r
3 #include <ti/csl/cslr_device.h>\r
4 #include <include/McaspLocal.h>\r
5 extern Mcasp_Module_State Mcasp_module;\r
6 #ifdef _TMS320C6X\r
7 #include <ti/sysbios/family/c64p/Hwi.h>\r
8 #include <ti/sysbios/family/c66/tci66xx/CpIntc.h>\r
9 #include <ti/sysbios/family/c64p/EventCombiner.h>\r
10 #else\r
11 #include <ti/sysbios/hal/Hwi.h>\r
12 #endif\r
13 \r
14 #include <ti/sysbios/BIOS.h>\r
15 #include <ti/sysbios/hal/Cache.h>\r
16 \r
17 #include <ti/sysbios/knl/Queue.h>\r
18 #include <ti/sysbios/knl/Task.h>\r
19 #include <ti/sysbios/knl/Swi.h>\r
20 #include <ti/osal/osal.h>\r
21 \r
22 \r
23 void * osal_Queue_handle(void *structPtr)\r
24 {\r
25         return(Queue_handle(structPtr));\r
26 }\r
27 \r
28 void osal_Queue_construct(void * ptr, int32_t arg)\r
29 {\r
30         Queue_construct((Queue_Struct*)ptr, NULL);\r
31 }\r
32 \r
33 void osal_Task_sleep(int32_t msec)\r
34 {\r
35         int i,j;\r
36         //Task_sleep(msec);\r
37          for (i=0; i < msec; i++) {\r
38                 for (j=0; j < 1000; j++) {\r
39 #ifdef _TMS320C6X\r
40                         asm("* Comment to maintain loops through compiler optimization");\r
41 #endif\r
42                 }\r
43          }\r
44 }\r
45 int32_t osal_getThreadType()\r
46 {\r
47         return BIOS_getThreadType() == BIOS_ThreadType_Task;\r
48 \r
49 }\r
50 #ifdef _TMS320C6X\r
51 int hostintArr[6]={33,34,35,36,37,38};\r
52 int eventIdArr[6]={0x33,0x34,0x35,0x36,0x37,0x38};\r
53 void osal_EventCombiner_disableEvent(int32_t cpuEventNum)\r
54 {\r
55 \r
56         EventCombiner_disableEvent(eventIdArr[cpuEventNum- CSL_CIC_McASP_0_XINT]);\r
57 \r
58 \r
59 }\r
60 void osal_EventCombiner_enableEvent(int32_t cpuEventNum)\r
61 {\r
62 \r
63         EventCombiner_enableEvent(eventIdArr[cpuEventNum- CSL_CIC_McASP_0_XINT]);\r
64 \r
65 }\r
66 \r
67 void osal_EventCombiner_dispatchPlug(uint32_t evt, void * intIsr, void *arg, int32_t flag )\r
68 {\r
69         int hostint,eventId;\r
70           CpIntc_dispatchPlug(evt, (CpIntc_FuncPtr)intIsr, 0, TRUE);\r
71           hostint=hostintArr[evt- CSL_CIC_McASP_0_XINT];\r
72                                    /* The configuration is for CPINTC0. We map system interrupt 0x88 to Host Interrupt 32. */\r
73                                    CpIntc_mapSysIntToHostInt(0, evt, hostint);\r
74 \r
75                                    /* Enable the Host Interrupt. */\r
76                                    CpIntc_enableHostInt(0, hostint);\r
77 \r
78                                    /* Enable the System Interrupt */\r
79                                    CpIntc_enableSysInt(0, evt);\r
80 \r
81                                    /* Get the event id associated with the host interrupt. */\r
82                                    eventId = eventIdArr[evt- CSL_CIC_McASP_0_XINT];\r
83                                    /* enable the 'global' switch */\r
84 \r
85                                   /* Enable the Xfer Completion Event Interrupt */\r
86                                        EventCombiner_dispatchPlug(eventId,\r
87                                                                                 (EventCombiner_FuncPtr)(&CpIntc_dispatch),\r
88                                                                 hostint, 1);\r
89 \r
90 \r
91         //EventCombiner_dispatchPlug(evt, (EventCombiner_FuncPtr)intIsr, arg, flag);\r
92 }\r
93 #endif\r
94 \r
95 \r
96 #if 0\r
97 int gDebug=0;\r
98 \r
99 void assert(int in)\r
100 {\r
101 if(in <=0)\r
102         gDebug++;\r
103 }\r
104 #endif\r
105 \r
106 void osal_Swi_post(void * obj)\r
107 {\r
108         Swi_post((Swi_Handle)obj);\r
109 \r
110 }\r
111 int32_t osal_Queue_empty(void * handle)\r
112 {\r
113 return Queue_empty(Queue_handle(handle));\r
114 //      return ((Mcasp_QueueElem*)handle->next == &((Mcasp_QueueElem*)handle));\r
115 \r
116 }\r
117 \r
118 MCASP_Packet * osal_Queue_get(void * handle)\r
119 {\r
120 return Queue_get(Queue_handle(handle));\r
121 }\r
122 \r
123 void osal_Queue_put(void * handle,Ptr ptr)\r
124                 {\r
125         Queue_put(Queue_handle(handle),(Ptr)ptr);\r
126                 }\r
127 \r
128 \r
129 McaspOsal_IntrHandle McaspOsal_registerIntr(\r
130     uint32_t              intNum,\r
131     McaspOsal_IntrFuncPtr fxn,\r
132     const void         *arg0)\r
133 {\r
134     Hwi_Params hwiParams = {0};\r
135 \r
136     Hwi_Params_init(&hwiParams);\r
137     hwiParams.arg = (uint32_t) arg0;\r
138     return (McaspOsal_IntrHandle) Hwi_create(\r
139                (int32_t) intNum,\r
140                (Hwi_FuncPtr) fxn,\r
141                &hwiParams,\r
142                0U);\r
143 }\r
144 void McaspOsal_unRegisterIntr(McaspOsal_IntrHandle  handle)\r
145 {\r
146     Hwi_delete(handle);\r
147 }\r
148 \r
149 /* OSAL functions for Platform Library */\r
150 uint8_t *Osal_platformMalloc (uint32_t num_bytes, uint32_t alignment)\r
151 {\r
152         return malloc(num_bytes);\r
153 }\r
154 \r
155 void Osal_platformFree (uint8_t *dataPtr, uint32_t num_bytes)\r
156 {\r
157     /* Free up the memory */\r
158     if (dataPtr)\r
159     {\r
160         free(dataPtr);\r
161     }\r
162 }\r
163 \r
164 void Osal_platformSpiCsEnter(void)\r
165 {\r
166     /* Get the hardware semaphore.\r
167      *\r
168      * Acquire Multi core CPPI synchronization lock\r
169      */\r
170     //while ((CSL_semAcquireDirect (PLATFORM_SPI_HW_SEM)) == 0);\r
171 \r
172     return;\r
173 }\r
174 \r
175 void Osal_platformSpiCsExit (void)\r
176 {\r
177     /* Release the hardware semaphore\r
178      *\r
179      * Release multi-core lock.\r
180      */\r
181     //CSL_semReleaseSemaphore (PLATFORM_SPI_HW_SEM);\r
182 \r
183     return;\r
184 }\r