05677d9eeaf432febec5b120d2c7c7fa9066a11a
1 /*\r
2 * sample_tci616_cfg.c\r
3 *\r
4 * Platform specific EDMA3 hardware related information like number of transfer\r
5 * controllers, various interrupt ids etc. It is used while interrupts\r
6 * enabling / disabling. It needs to be ported for different SoCs.\r
7 *\r
8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
9 *\r
10 *\r
11 * Redistribution and use in source and binary forms, with or without\r
12 * modification, are permitted provided that the following conditions\r
13 * are met:\r
14 *\r
15 * Redistributions of source code must retain the above copyright\r
16 * notice, this list of conditions and the following disclaimer.\r
17 *\r
18 * Redistributions in binary form must reproduce the above copyright\r
19 * notice, this list of conditions and the following disclaimer in the\r
20 * documentation and/or other materials provided with the\r
21 * distribution.\r
22 *\r
23 * Neither the name of Texas Instruments Incorporated nor the names of\r
24 * its contributors may be used to endorse or promote products derived\r
25 * from this software without specific prior written permission.\r
26 *\r
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
38 *\r
39 */\r
40 \r
41 #include <ti/sdo/edma3/rm/edma3_rm.h>\r
42 \r
43 /* Number of EDMA3 controllers present in the system */\r
44 #define NUM_EDMA3_INSTANCES 2u\r
45 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;\r
46 \r
47 /* Number of DSPs present in the system */\r
48 #define NUM_DSPS 1u\r
49 //const unsigned int numDsps = NUM_DSPS;\r
50 \r
51 #define CGEM_REG_START (0x01800000)\r
52 \r
53 \r
54 extern cregister volatile unsigned int DNUM;\r
55 \r
56 #define MAP_LOCAL_TO_GLOBAL_ADDR(addr) ((1<<28)|(DNUM<<24)|(((unsigned int)addr)&0x00ffffff))\r
57 \r
58 \r
59 /* Determine the processor id by reading DNUM register. */\r
60 unsigned short determineProcId()\r
61 {\r
62 volatile unsigned int *addr;\r
63 unsigned int core_no;\r
64 \r
65 /* Identify the core number */\r
66 addr = (unsigned int *)(CGEM_REG_START+0x40000);\r
67 core_no = ((*addr) & 0x000F0000)>>16;\r
68 \r
69 return core_no;\r
70 }\r
71 \r
72 signed char* getGlobalAddr(signed char* addr)\r
73 {\r
74 if (((unsigned int)addr & (unsigned int)0xFF000000) != 0)\r
75 {\r
76 return (addr); /* The address is already a global address */\r
77 }\r
78 \r
79 return((signed char*)(MAP_LOCAL_TO_GLOBAL_ADDR(addr)));\r
80 }\r
81 /** Whether global configuration required for EDMA3 or not.\r
82 * This configuration should be done only once for the EDMA3 hardware by\r
83 * any one of the masters (i.e. DSPs).\r
84 * It can be changed depending on the use-case.\r
85 */\r
86 unsigned int gblCfgReqdArray [NUM_DSPS] = {\r
87 0, /* DSP#0 is Master, will do the global init */\r
88 \r
89 };\r
90 \r
91 unsigned short isGblConfigRequired(unsigned int dspNum)\r
92 {\r
93 return gblCfgReqdArray[dspNum];\r
94 }\r
95 \r
96 /* Semaphore handles */\r
97 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL};\r
98 \r
99 \r
100 /* Variable which will be used internally for referring number of Event Queues. */\r
101 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {2u, 2u};\r
102 \r
103 /* Variable which will be used internally for referring number of TCs. */\r
104 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 2u};\r
105 \r
106 /**\r
107 * Variable which will be used internally for referring transfer completion\r
108 * interrupt. Completion interrupts for all the shadow regions and all the\r
109 * EDMA3 controllers are captured since it is a multi-DSP platform.\r
110 */\r
111 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {\r
112 {\r
113 0x88, 0x89, 0x8a, 0x8b,\r
114 0x8c, 0x8d, 0x8e, 0x8f,\r
115 },\r
116 {\r
117 0x90, 0x91, 0x92, 0x93,\r
118 0x94, 0x95, 0x96, 0x97,\r
119 },\r
120 };\r
121 \r
122 /**\r
123 * Variable which will be used internally for referring channel controller's\r
124 * error interrupt.\r
125 */\r
126 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {0x99, 0x9c};\r
127 \r
128 /**\r
129 * Variable which will be used internally for referring transfer controllers'\r
130 * error interrupts.\r
131 */\r
132 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] = {\r
133 {\r
134 0xA0,0xA1, 0u, 0u,\r
135 0u, 0u, 0u, 0u,\r
136 },\r
137 {\r
138 0xA4, 0xA5, 0u, 0u,\r
139 0u, 0u, 0u, 0u,\r
140 },\r
141 };\r
142 \r
143 /* Driver Object Initialization Configuration */\r
144 EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =\r
145 {\r
146 {\r
147 /* EDMA3 INSTANCE# 0 */\r
148 /** Total number of DMA Channels supported by the EDMA3 Controller */\r
149 64u,\r
150 /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
151 8u,\r
152 /** Total number of TCCs supported by the EDMA3 Controller */\r
153 64u,\r
154 /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
155 512u,\r
156 /** Total number of Event Queues in the EDMA3 Controller */\r
157 2u,\r
158 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */\r
159 2u,\r
160 /** Number of Regions on this EDMA3 controller */\r
161 8u,\r
162 \r
163 /**\r
164 * \brief Channel mapping existence\r
165 * A value of 0 (No channel mapping) implies that there is fixed association\r
166 * for a channel number to a parameter entry number or, in other words,\r
167 * PaRAM entry n corresponds to channel n.\r
168 */\r
169 1u,\r
170 \r
171 /** Existence of memory protection feature */\r
172 1u,\r
173 \r
174 /** Global Register Region of CC Registers */\r
175 (void *)0x02700000u,\r
176 /** Transfer Controller (TC) Registers */\r
177 {\r
178 (void *)0x02760000u,\r
179 (void *)0x02768000u,\r
180 (void *)NULL,\r
181 (void *)NULL,\r
182 (void *)NULL,\r
183 (void *)NULL,\r
184 (void *)NULL,\r
185 (void *)NULL\r
186 },\r
187 /** Interrupt no. for Transfer Completion */\r
188 0x88,\r
189 /** Interrupt no. for CC Error */\r
190 0x99,\r
191 /** Interrupt no. for TCs Error */\r
192 {\r
193 0xA0,\r
194 0xA1,\r
195 0u,\r
196 0u,\r
197 0u,\r
198 0u,\r
199 0u,\r
200 0u,\r
201 },\r
202 \r
203 /**\r
204 * \brief EDMA3 TC priority setting\r
205 *\r
206 * User can program the priority of the Event Queues\r
207 * at a system-wide level. This means that the user can set the\r
208 * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
209 * relative to IO initiated by the other bus masters on the\r
210 * device (ARM, DSP, USB, etc)\r
211 */\r
212 {\r
213 0u,\r
214 1u,\r
215 0u,\r
216 0u,\r
217 0u,\r
218 0u,\r
219 0u,\r
220 0u\r
221 },\r
222 /**\r
223 * \brief To Configure the Threshold level of number of events\r
224 * that can be queued up in the Event queues. EDMA3CC error register\r
225 * (CCERR) will indicate whether or not at any instant of time the\r
226 * number of events queued up in any of the event queues exceeds\r
227 * or equals the threshold/watermark value that is set\r
228 * in the queue watermark threshold register (QWMTHRA).\r
229 */\r
230 {\r
231 16u,\r
232 16u,\r
233 0u,\r
234 0u,\r
235 0u,\r
236 0u,\r
237 0u,\r
238 0u\r
239 },\r
240 \r
241 /**\r
242 * \brief To Configure the Default Burst Size (DBS) of TCs.\r
243 * An optimally-sized command is defined by the transfer controller\r
244 * default burst size (DBS). Different TCs can have different\r
245 * DBS values. It is defined in Bytes.\r
246 */\r
247 {\r
248 128u,\r
249 128u,\r
250 0u,\r
251 0u,\r
252 0u,\r
253 0u,\r
254 0u,\r
255 0u\r
256 },\r
257 \r
258 /**\r
259 * \brief Mapping from each DMA channel to a Parameter RAM set,\r
260 * if it exists, otherwise of no use.\r
261 */\r
262 {\r
263 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
264 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,\r
265 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,\r
266 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,\r
267 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,\r
268 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,\r
269 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,\r
270 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u\r
271 },\r
272 \r
273 /**\r
274 * \brief Mapping from each DMA channel to a TCC. This specific\r
275 * TCC code will be returned when the transfer is completed\r
276 * on the mapped channel.\r
277 */\r
278 {\r
279 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
280 8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
281 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,\r
282 24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
283 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,\r
284 40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
285 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,\r
286 56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP\r
287 },\r
288 \r
289 /**\r
290 * \brief Mapping of DMA channels to Hardware Events from\r
291 * various peripherals, which use EDMA for data transfer.\r
292 * All channels need not be mapped, some can be free also.\r
293 */\r
294 {\r
295 0x03003333u,\r
296 0x0000000Fu\r
297 }\r
298 },\r
299 \r
300 {\r
301 /* EDMA3 INSTANCE# 1 */\r
302 /** Total number of DMA Channels supported by the EDMA3 Controller */\r
303 64u,\r
304 /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
305 8u,\r
306 /** Total number of TCCs supported by the EDMA3 Controller */\r
307 64u,\r
308 /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
309 512u,\r
310 /** Total number of Event Queues in the EDMA3 Controller */\r
311 2u,\r
312 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */\r
313 2u,\r
314 /** Number of Regions on this EDMA3 controller */\r
315 8u,\r
316 \r
317 /**\r
318 * \brief Channel mapping existence\r
319 * A value of 0 (No channel mapping) implies that there is fixed association\r
320 * for a channel number to a parameter entry number or, in other words,\r
321 * PaRAM entry n corresponds to channel n.\r
322 */\r
323 1u,\r
324 \r
325 /** Existence of memory protection feature */\r
326 1u,\r
327 \r
328 /** Global Register Region of CC Registers */\r
329 (void *)0x02728000U,\r
330 /** Transfer Controller (TC) Registers */\r
331 {\r
332 (void *)0x027b0000U,\r
333 (void *)0x027b8000U,\r
334 (void *)NULL,\r
335 (void *)NULL,\r
336 (void *)NULL,\r
337 (void *)NULL,\r
338 (void *)NULL,\r
339 (void *)NULL\r
340 },\r
341 /** Interrupt no. for Transfer Completion */\r
342 0x90,\r
343 /** Interrupt no. for CC Error */\r
344 0x9C,\r
345 /** Interrupt no. for TCs Error */\r
346 {\r
347 0xA4,\r
348 0xA5,\r
349 0u,\r
350 0u,\r
351 0u,\r
352 0u,\r
353 0u,\r
354 0u,\r
355 },\r
356 \r
357 /**\r
358 * \brief EDMA3 TC priority setting\r
359 *\r
360 * User can program the priority of the Event Queues\r
361 * at a system-wide level. This means that the user can set the\r
362 * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
363 * relative to IO initiated by the other bus masters on the\r
364 * device (ARM, DSP, USB, etc)\r
365 */\r
366 {\r
367 0u,\r
368 1u,\r
369 2u,\r
370 3u,\r
371 0u,\r
372 0u,\r
373 0u,\r
374 0u\r
375 },\r
376 /**\r
377 * \brief To Configure the Threshold level of number of events\r
378 * that can be queued up in the Event queues. EDMA3CC error register\r
379 * (CCERR) will indicate whether or not at any instant of time the\r
380 * number of events queued up in any of the event queues exceeds\r
381 * or equals the threshold/watermark value that is set\r
382 * in the queue watermark threshold register (QWMTHRA).\r
383 */\r
384 {\r
385 16u,\r
386 16u,\r
387 16u,\r
388 16u,\r
389 0u,\r
390 0u,\r
391 0u,\r
392 0u\r
393 },\r
394 \r
395 /**\r
396 * \brief To Configure the Default Burst Size (DBS) of TCs.\r
397 * An optimally-sized command is defined by the transfer controller\r
398 * default burst size (DBS). Different TCs can have different\r
399 * DBS values. It is defined in Bytes.\r
400 */\r
401 {\r
402 64u,\r
403 64u,\r
404 64u,\r
405 64u,\r
406 0u,\r
407 0u,\r
408 0u,\r
409 0u\r
410 },\r
411 \r
412 /**\r
413 * \brief Mapping from each DMA channel to a Parameter RAM set,\r
414 * if it exists, otherwise of no use.\r
415 */\r
416 {\r
417 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
418 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,\r
419 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,\r
420 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,\r
421 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,\r
422 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,\r
423 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,\r
424 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u\r
425 },\r
426 \r
427 /**\r
428 * \brief Mapping from each DMA channel to a TCC. This specific\r
429 * TCC code will be returned when the transfer is completed\r
430 * on the mapped channel.\r
431 */\r
432 {\r
433 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
434 8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
435 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,\r
436 24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
437 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,\r
438 40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
439 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,\r
440 56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP\r
441 },\r
442 \r
443 /**\r
444 * \brief Mapping of DMA channels to Hardware Events from\r
445 * various peripherals, which use EDMA for data transfer.\r
446 * All channels need not be mapped, some can be free also.\r
447 */\r
448 {\r
449 0x3FFF3FFFu,\r
450 0x3FFF3FFFu\r
451 }\r
452 },\r
453 \r
454 };\r
455 \r
456 EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
457 {\r
458 /* EDMA3 INSTANCE# 0 */\r
459 {\r
460 /* Resources owned/reserved by region 0 */\r
461 {\r
462 /* ownPaRAMSets */\r
463 /* 31 0 63 32 95 64 127 96 */\r
464 {0xFFFF000Fu, 0x00000FFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
465 /* 159 128 191 160 223 192 255 224 */\r
466 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,\r
467 /* 287 256 319 288 351 320 383 352 */\r
468 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
469 /* 415 384 447 416 479 448 511 480 */\r
470 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
471 \r
472 /* ownDmaChannels */\r
473 /* 31 0 63 32 */\r
474 {0x0f00000Fu, 0x0000000Fu},\r
475 \r
476 /* ownQdmaChannels */\r
477 /* 31 0 */\r
478 {0x00000003u},\r
479 \r
480 /* ownTccs */\r
481 /* 31 0 63 32 */\r
482 {0x0f00000Fu, 0x0000000Fu},\r
483 \r
484 /* resvdPaRAMSets */\r
485 /* 31 0 63 32 95 64 127 96 */\r
486 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
487 /* 159 128 191 160 223 192 255 224 */\r
488 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
489 /* 287 256 319 288 351 320 383 352 */\r
490 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
491 /* 415 384 447 416 479 448 511 480 */\r
492 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
493 \r
494 /* resvdDmaChannels */\r
495 /* 31 0 */\r
496 {0x00000000u, 0x00000000u},\r
497 \r
498 /* resvdQdmaChannels */\r
499 /* 31 0 */\r
500 {0x00000000u},\r
501 \r
502 /* resvdTccs */\r
503 /* 31 0 */\r
504 {0x00000000u, 0xFFF00000u},\r
505 },\r
506 \r
507 /* Resources owned/reserved by region 1 */\r
508 {\r
509 /* ownPaRAMSets */\r
510 /* 31 0 63 32 95 64 127 96 */\r
511 {0x000000F0u, 0xFFFFF000u, 0x000000FFu, 0x00000000u,\r
512 /* 159 128 191 160 223 192 255 224 */\r
513 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
514 /* 287 256 319 288 351 320 383 352 */\r
515 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
516 /* 415 384 447 416 479 448 511 480 */\r
517 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
518 \r
519 /* ownDmaChannels */\r
520 /* 31 0 63 32 */\r
521 {0x000000F0u, 0x00000000u},\r
522 \r
523 /* ownQdmaChannels */\r
524 /* 31 0 */\r
525 {0x0000000Cu},\r
526 \r
527 /* ownTccs */\r
528 /* 31 0 63 32 */\r
529 {0x000000F0u, 0x00000000u},\r
530 \r
531 /* resvdPaRAMSets */\r
532 /* 31 0 63 32 95 64 127 96 */\r
533 {0x00000030u, 0x00000000u, 0x00000000u, 0x00000000u,\r
534 /* 159 128 191 160 223 192 255 224 */\r
535 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
536 /* 287 256 319 288 351 320 383 352 */\r
537 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
538 /* 415 384 447 416 479 448 511 480 */\r
539 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
540 \r
541 /* resvdDmaChannels */\r
542 /* 31 0 63 32 */\r
543 {0x00000030u, 0x00000000u},\r
544 \r
545 /* resvdQdmaChannels */\r
546 /* 31 0 */\r
547 {0x00000000u},\r
548 \r
549 /* resvdTccs */\r
550 /* 31 0 63 32 */\r
551 {0x00000030u, 0x00000000u},\r
552 },\r
553 \r
554 /* Resources owned/reserved by region 2 */\r
555 {\r
556 /* ownPaRAMSets */\r
557 /* 31 0 63 32 95 64 127 96 */\r
558 {0x00000F00u, 0x00000000u, 0xFFFFFF00u, 0x0000000Fu,\r
559 /* 159 128 191 160 223 192 255 224 */\r
560 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
561 /* 287 256 319 288 351 320 383 352 */\r
562 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
563 /* 415 384 447 416 479 448 511 480 */\r
564 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
565 \r
566 /* ownDmaChannels */\r
567 /* 31 0 63 32 */\r
568 {0x00000F00u, 0x00000000u},\r
569 \r
570 /* ownQdmaChannels */\r
571 /* 31 0 */\r
572 {0x00000030u},\r
573 \r
574 /* ownTccs */\r
575 /* 31 0 63 32 */\r
576 {0x00000F00u, 0x00000000u},\r
577 \r
578 /* resvdPaRAMSets */\r
579 /* 31 0 63 32 95 64 127 96 */\r
580 {0x00000300u, 0x00000000u, 0x00000000u, 0x00000000u,\r
581 /* 159 128 191 160 223 192 255 224 */\r
582 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
583 /* 287 256 319 288 351 320 383 352 */\r
584 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
585 /* 415 384 447 416 479 448 511 480 */\r
586 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
587 \r
588 /* resvdDmaChannels */\r
589 /* 31 0 63 32 */\r
590 {0x00000300u, 0x00000000u},\r
591 \r
592 /* resvdQdmaChannels */\r
593 /* 31 0 */\r
594 {0x00000000u},\r
595 \r
596 /* resvdTccs */\r
597 /* 31 0 63 32 */\r
598 {0x00000300u, 0x00000000u},\r
599 },\r
600 \r
601 /* Resources owned/reserved by region 3 */\r
602 {\r
603 /* ownPaRAMSets */\r
604 /* 31 0 63 32 95 64 127 96 */\r
605 {0x0000F000u, 0x00000000u, 0x00000000u, 0xFFFFFFF0u,\r
606 /* 159 128 191 160 223 192 255 224 */\r
607 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
608 /* 287 256 319 288 351 320 383 352 */\r
609 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
610 /* 415 384 447 416 479 448 511 480 */\r
611 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
612 \r
613 /* ownDmaChannels */\r
614 /* 31 0 63 32 */\r
615 {0x0000F000u, 0x00000000u},\r
616 \r
617 /* ownQdmaChannels */\r
618 /* 31 0 */\r
619 {0x000000C0u},\r
620 \r
621 /* ownTccs */\r
622 /* 31 0 63 32 */\r
623 {0x0000F000u, 0x00000000u},\r
624 \r
625 /* resvdPaRAMSets */\r
626 /* 31 0 63 32 95 64 127 96 */\r
627 {0x00003000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
628 /* 159 128 191 160 223 192 255 224 */\r
629 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
630 /* 287 256 319 288 351 320 383 352 */\r
631 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
632 /* 415 384 447 416 479 448 511 480 */\r
633 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
634 \r
635 /* resvdDmaChannels */\r
636 /* 31 0 63 32 */\r
637 {0x00003000u, 0x00000000u},\r
638 \r
639 /* resvdQdmaChannels */\r
640 /* 31 0 */\r
641 {0x00000000u},\r
642 \r
643 /* resvdTccs */\r
644 /* 31 0 63 32 */\r
645 {0x00003000u, 0x00000000u},\r
646 },\r
647 \r
648 /* Resources owned/reserved by region 4 */\r
649 {\r
650 /* ownPaRAMSets */\r
651 /* 31 0 63 32 95 64 127 96 */\r
652 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
653 /* 159 128 191 160 223 192 255 224 */\r
654 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
655 /* 287 256 319 288 351 320 383 352 */\r
656 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
657 /* 415 384 447 416 479 448 511 480 */\r
658 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
659 \r
660 /* ownDmaChannels */\r
661 /* 31 0 63 32 */\r
662 {0x00000000u, 0x00000000u},\r
663 \r
664 /* ownQdmaChannels */\r
665 /* 31 0 */\r
666 {0x00000000u},\r
667 \r
668 /* ownTccs */\r
669 /* 31 0 63 32 */\r
670 {0x00000000u, 0x00000000u},\r
671 \r
672 /* resvdPaRAMSets */\r
673 /* 31 0 63 32 95 64 127 96 */\r
674 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
675 /* 159 128 191 160 223 192 255 224 */\r
676 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
677 /* 287 256 319 288 351 320 383 352 */\r
678 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
679 /* 415 384 447 416 479 448 511 480 */\r
680 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
681 \r
682 /* resvdDmaChannels */\r
683 /* 31 0 63 32 */\r
684 {0x00000000u, 0x00000000u},\r
685 \r
686 /* resvdQdmaChannels */\r
687 /* 31 0 */\r
688 {0x00000000u},\r
689 \r
690 /* resvdTccs */\r
691 /* 31 0 63 32 */\r
692 {0x00000000u, 0x00000000u},\r
693 },\r
694 \r
695 /* Resources owned/reserved by region 5 */\r
696 {\r
697 /* ownPaRAMSets */\r
698 /* 31 0 63 32 95 64 127 96 */\r
699 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
700 /* 159 128 191 160 223 192 255 224 */\r
701 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
702 /* 287 256 319 288 351 320 383 352 */\r
703 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
704 /* 415 384 447 416 479 448 511 480 */\r
705 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
706 \r
707 /* ownDmaChannels */\r
708 /* 31 0 63 32 */\r
709 {0x00000000u, 0x00000000u},\r
710 \r
711 /* ownQdmaChannels */\r
712 /* 31 0 */\r
713 {0x00000000u},\r
714 \r
715 /* ownTccs */\r
716 /* 31 0 63 32 */\r
717 {0x00000000u, 0x00000000u},\r
718 \r
719 /* resvdPaRAMSets */\r
720 /* 31 0 63 32 95 64 127 96 */\r
721 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
722 /* 159 128 191 160 223 192 255 224 */\r
723 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
724 /* 287 256 319 288 351 320 383 352 */\r
725 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
726 /* 415 384 447 416 479 448 511 480 */\r
727 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
728 \r
729 /* resvdDmaChannels */\r
730 /* 31 0 63 32 */\r
731 {0x00000000u, 0x00000000u},\r
732 \r
733 /* resvdQdmaChannels */\r
734 /* 31 0 */\r
735 {0x00000000u},\r
736 \r
737 /* resvdTccs */\r
738 /* 31 0 63 32 */\r
739 {0x00000000u, 0x00000000u},\r
740 },\r
741 \r
742 /* Resources owned/reserved by region 6 */\r
743 {\r
744 /* ownPaRAMSets */\r
745 /* 31 0 63 32 95 64 127 96 */\r
746 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
747 /* 159 128 191 160 223 192 255 224 */\r
748 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
749 /* 287 256 319 288 351 320 383 352 */\r
750 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
751 /* 415 384 447 416 479 448 511 480 */\r
752 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
753 \r
754 /* ownDmaChannels */\r
755 /* 31 0 63 32 */\r
756 {0x00000000u, 0x00000000u},\r
757 \r
758 /* ownQdmaChannels */\r
759 /* 31 0 */\r
760 {0x00000000u},\r
761 \r
762 /* ownTccs */\r
763 /* 31 0 63 32 */\r
764 {0x00000000u, 0x00000000u},\r
765 \r
766 /* resvdPaRAMSets */\r
767 /* 31 0 63 32 95 64 127 96 */\r
768 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
769 /* 159 128 191 160 223 192 255 224 */\r
770 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
771 /* 287 256 319 288 351 320 383 352 */\r
772 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
773 /* 415 384 447 416 479 448 511 480 */\r
774 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
775 \r
776 /* resvdDmaChannels */\r
777 /* 31 0 63 32 */\r
778 {0x00000000u, 0x00000000u},\r
779 \r
780 /* resvdQdmaChannels */\r
781 /* 31 0 */\r
782 {0x00000000u},\r
783 \r
784 /* resvdTccs */\r
785 /* 31 0 63 32 */\r
786 {0x00000000u, 0x00000000u},\r
787 },\r
788 \r
789 /* Resources owned/reserved by region 7 */\r
790 {\r
791 /* ownPaRAMSets */\r
792 /* 31 0 63 32 95 64 127 96 */\r
793 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
794 /* 159 128 191 160 223 192 255 224 */\r
795 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
796 /* 287 256 319 288 351 320 383 352 */\r
797 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
798 /* 415 384 447 416 479 448 511 480 */\r
799 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
800 \r
801 /* ownDmaChannels */\r
802 /* 31 0 63 32 */\r
803 {0x00000000u, 0x00000000u},\r
804 \r
805 /* ownQdmaChannels */\r
806 /* 31 0 */\r
807 {0x00000000u},\r
808 \r
809 /* ownTccs */\r
810 /* 31 0 63 32 */\r
811 {0x00000000u, 0x00000000u},\r
812 \r
813 /* resvdPaRAMSets */\r
814 /* 31 0 63 32 95 64 127 96 */\r
815 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
816 /* 159 128 191 160 223 192 255 224 */\r
817 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
818 /* 287 256 319 288 351 320 383 352 */\r
819 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
820 /* 415 384 447 416 479 448 511 480 */\r
821 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
822 \r
823 /* resvdDmaChannels */\r
824 /* 31 0 63 32 */\r
825 {0x00000000u, 0x00000000u},\r
826 \r
827 /* resvdQdmaChannels */\r
828 /* 31 0 */\r
829 {0x00000000u},\r
830 \r
831 /* resvdTccs */\r
832 /* 31 0 63 32 */\r
833 {0x00000000u, 0x00000000u},\r
834 },\r
835 },\r
836 \r
837 /* EDMA3 INSTANCE# 1 */\r
838 {\r
839 /* Resources owned/reserved by region 0 */\r
840 {\r
841 /* ownPaRAMSets */\r
842 /* 31 0 63 32 95 64 127 96 */\r
843 {0x0000FFFFu, 0x000F0000u, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
844 /* 159 128 191 160 223 192 255 224 */\r
845 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,\r
846 /* 287 256 319 288 351 320 383 352 */\r
847 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
848 /* 415 384 447 416 479 448 511 480 */\r
849 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
850 \r
851 /* ownDmaChannels */\r
852 /* 31 0 63 32 */\r
853 {0x0000FFFFu, 0x000F0000u},\r
854 \r
855 /* ownQdmaChannels */\r
856 /* 31 0 */\r
857 {0x00000003u},\r
858 \r
859 /* ownTccs */\r
860 /* 31 0 63 32 */\r
861 {0x0000FFFFu, 0x000F0000u},\r
862 \r
863 /* resvdPaRAMSets */\r
864 /* 31 0 63 32 95 64 127 96 */\r
865 {0x00003FFFu, 0x00000000u, 0x00000000u, 0x00000000u,\r
866 /* 159 128 191 160 223 192 255 224 */\r
867 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
868 /* 287 256 319 288 351 320 383 352 */\r
869 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
870 /* 415 384 447 416 479 448 511 480 */\r
871 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
872 \r
873 /* resvdDmaChannels */\r
874 /* 31 0 63 32 */\r
875 {0x00003FFFu, 0x00000000u},\r
876 \r
877 /* resvdQdmaChannels */\r
878 /* 31 0 */\r
879 {0x00000000u},\r
880 \r
881 /* resvdTccs */\r
882 /* 31 0 63 32 */\r
883 {0x00003FFFu, 0x00000000u},\r
884 },\r
885 \r
886 /* Resources owned/reserved by region 1 */\r
887 {\r
888 /* ownPaRAMSets */\r
889 /* 31 0 63 32 95 64 127 96 */\r
890 {0xFFFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
891 /* 159 128 191 160 223 192 255 224 */\r
892 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
893 /* 287 256 319 288 351 320 383 352 */\r
894 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,\r
895 /* 415 384 447 416 479 448 511 480 */\r
896 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
897 \r
898 /* ownDmaChannels */\r
899 /* 31 0 63 32 */\r
900 {0xFFFF0000u, 0x00000000u},\r
901 \r
902 /* ownQdmaChannels */\r
903 /* 31 0 */\r
904 {0x0000000Cu},\r
905 \r
906 /* ownTccs */\r
907 /* 31 0 63 32 */\r
908 {0xFFFF0000u, 0x00000000u},\r
909 \r
910 /* resvdPaRAMSets */\r
911 /* 31 0 63 32 95 64 127 96 */\r
912 {0x3FFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
913 /* 159 128 191 160 223 192 255 224 */\r
914 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
915 /* 287 256 319 288 351 320 383 352 */\r
916 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
917 /* 415 384 447 416 479 448 511 480 */\r
918 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
919 \r
920 /* resvdDmaChannels */\r
921 /* 31 0 63 32 */\r
922 {0x3FFF0000u, 0x00000000u},\r
923 \r
924 /* resvdQdmaChannels */\r
925 /* 31 0 */\r
926 {0x00000000u},\r
927 \r
928 /* resvdTccs */\r
929 /* 31 0 63 32 */\r
930 {0x3FFF0000u, 0x00000000u},\r
931 },\r
932 \r
933 /* Resources owned/reserved by region 2 */\r
934 {\r
935 /* ownPaRAMSets */\r
936 /* 31 0 63 32 95 64 127 96 */\r
937 {0x00000000u, 0x0000FFFFu, 0x00000000u, 0x00000000u,\r
938 /* 159 128 191 160 223 192 255 224 */\r
939 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
940 /* 287 256 319 288 351 320 383 352 */\r
941 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
942 /* 415 384 447 416 479 448 511 480 */\r
943 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,},\r
944 \r
945 /* ownDmaChannels */\r
946 /* 31 0 63 32 */\r
947 {0x00000000u, 0x0000FFFFu},\r
948 \r
949 /* ownQdmaChannels */\r
950 /* 31 0 */\r
951 {0x00000030u},\r
952 \r
953 /* ownTccs */\r
954 /* 31 0 63 32 */\r
955 {0x00000000u, 0x0000FFFFu},\r
956 \r
957 /* resvdPaRAMSets */\r
958 /* 31 0 63 32 95 64 127 96 */\r
959 {0x00000000u, 0x00003FFFu, 0x00000000u, 0x00000000u,\r
960 /* 159 128 191 160 223 192 255 224 */\r
961 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
962 /* 287 256 319 288 351 320 383 352 */\r
963 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
964 /* 415 384 447 416 479 448 511 480 */\r
965 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
966 \r
967 /* resvdDmaChannels */\r
968 /* 31 0 63 32 */\r
969 {0x00000000u, 0x00003FFFu},\r
970 \r
971 /* resvdQdmaChannels */\r
972 /* 31 0 */\r
973 {0x00000000u},\r
974 \r
975 /* resvdTccs */\r
976 /* 31 0 63 32 */\r
977 {0x00000000u, 0x00003FFFu},\r
978 },\r
979 \r
980 /* Resources owned/reserved by region 3 */\r
981 {\r
982 /* ownPaRAMSets */\r
983 /* 31 0 63 32 95 64 127 96 */\r
984 {0x00000000u, 0xFFFF0000u, 0x00000000u, 0x00000000u,\r
985 /* 159 128 191 160 223 192 255 224 */\r
986 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
987 /* 287 256 319 288 351 320 383 352 */\r
988 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
989 /* 415 384 447 416 479 448 511 480 */\r
990 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},\r
991 \r
992 /* ownDmaChannels */\r
993 /* 31 0 63 32 */\r
994 {0x00000000u, 0xFFFF0000u},\r
995 \r
996 /* ownQdmaChannels */\r
997 /* 31 0 */\r
998 {0x000000C0u},\r
999 \r
1000 /* ownTccs */\r
1001 /* 31 0 63 32 */\r
1002 {0x00000000u, 0xFFFF0000u},\r
1003 \r
1004 /* resvdPaRAMSets */\r
1005 /* 31 0 63 32 95 64 127 96 */\r
1006 {0x00000000u, 0x3FFF0000u, 0x00000000u, 0x00000000u,\r
1007 /* 159 128 191 160 223 192 255 224 */\r
1008 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1009 /* 287 256 319 288 351 320 383 352 */\r
1010 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1011 /* 415 384 447 416 479 448 511 480 */\r
1012 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
1013 \r
1014 /* resvdDmaChannels */\r
1015 /* 31 0 63 32 */\r
1016 {0x00000000u, 0x3FFF0000u},\r
1017 \r
1018 /* resvdQdmaChannels */\r
1019 /* 31 0 */\r
1020 {0x00000000u},\r
1021 \r
1022 /* resvdTccs */\r
1023 /* 31 0 63 32 */\r
1024 {0x00000000u, 0x3FFF0000u},\r
1025 },\r
1026 \r
1027 /* Resources owned/reserved by region 4 */\r
1028 {\r
1029 /* ownPaRAMSets */\r
1030 /* 31 0 63 32 95 64 127 96 */\r
1031 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1032 /* 159 128 191 160 223 192 255 224 */\r
1033 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1034 /* 287 256 319 288 351 320 383 352 */\r
1035 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1036 /* 415 384 447 416 479 448 511 480 */\r
1037 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1038 \r
1039 /* ownDmaChannels */\r
1040 /* 31 0 63 32 */\r
1041 {0x00000000u, 0x00000000u},\r
1042 \r
1043 /* ownQdmaChannels */\r
1044 /* 31 0 */\r
1045 {0x00000000u},\r
1046 \r
1047 /* ownTccs */\r
1048 /* 31 0 63 32 */\r
1049 {0x00000000u, 0x00000000u},\r
1050 \r
1051 /* resvdPaRAMSets */\r
1052 /* 31 0 63 32 95 64 127 96 */\r
1053 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1054 /* 159 128 191 160 223 192 255 224 */\r
1055 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1056 /* 287 256 319 288 351 320 383 352 */\r
1057 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1058 /* 415 384 447 416 479 448 511 480 */\r
1059 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1060 \r
1061 /* resvdDmaChannels */\r
1062 /* 31 0 63 32 */\r
1063 {0x00000000u, 0x00000000u},\r
1064 \r
1065 /* resvdQdmaChannels */\r
1066 /* 31 0 */\r
1067 {0x00000000u},\r
1068 \r
1069 /* resvdTccs */\r
1070 /* 31 0 63 32 */\r
1071 {0x00000000u, 0x00000000u},\r
1072 },\r
1073 \r
1074 /* Resources owned/reserved by region 5 */\r
1075 {\r
1076 /* ownPaRAMSets */\r
1077 /* 31 0 63 32 95 64 127 96 */\r
1078 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1079 /* 159 128 191 160 223 192 255 224 */\r
1080 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1081 /* 287 256 319 288 351 320 383 352 */\r
1082 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1083 /* 415 384 447 416 479 448 511 480 */\r
1084 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1085 \r
1086 /* ownDmaChannels */\r
1087 /* 31 0 63 32 */\r
1088 {0x00000000u, 0x00000000u},\r
1089 \r
1090 /* ownQdmaChannels */\r
1091 /* 31 0 */\r
1092 {0x00000000u},\r
1093 \r
1094 /* ownTccs */\r
1095 /* 31 0 63 32 */\r
1096 {0x00000000u, 0x00000000u},\r
1097 \r
1098 /* resvdPaRAMSets */\r
1099 /* 31 0 63 32 95 64 127 96 */\r
1100 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1101 /* 159 128 191 160 223 192 255 224 */\r
1102 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1103 /* 287 256 319 288 351 320 383 352 */\r
1104 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1105 /* 415 384 447 416 479 448 511 480 */\r
1106 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1107 \r
1108 /* resvdDmaChannels */\r
1109 /* 31 0 63 32 */\r
1110 {0x00000000u, 0x00000000u},\r
1111 \r
1112 /* resvdQdmaChannels */\r
1113 /* 31 0 */\r
1114 {0x00000000u},\r
1115 \r
1116 /* resvdTccs */\r
1117 /* 31 0 63 32 */\r
1118 {0x00000000u, 0x00000000u},\r
1119 },\r
1120 \r
1121 /* Resources owned/reserved by region 6 */\r
1122 {\r
1123 /* ownPaRAMSets */\r
1124 /* 31 0 63 32 95 64 127 96 */\r
1125 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1126 /* 159 128 191 160 223 192 255 224 */\r
1127 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1128 /* 287 256 319 288 351 320 383 352 */\r
1129 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1130 /* 415 384 447 416 479 448 511 480 */\r
1131 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1132 \r
1133 /* ownDmaChannels */\r
1134 /* 31 0 63 32 */\r
1135 {0x00000000u, 0x00000000u},\r
1136 \r
1137 /* ownQdmaChannels */\r
1138 /* 31 0 */\r
1139 {0x00000000u},\r
1140 \r
1141 /* ownTccs */\r
1142 /* 31 0 63 32 */\r
1143 {0x00000000u, 0x00000000u},\r
1144 \r
1145 /* resvdPaRAMSets */\r
1146 /* 31 0 63 32 95 64 127 96 */\r
1147 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1148 /* 159 128 191 160 223 192 255 224 */\r
1149 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1150 /* 287 256 319 288 351 320 383 352 */\r
1151 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1152 /* 415 384 447 416 479 448 511 480 */\r
1153 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1154 \r
1155 /* resvdDmaChannels */\r
1156 /* 31 0 63 32 */\r
1157 {0x00000000u, 0x00000000u},\r
1158 \r
1159 /* resvdQdmaChannels */\r
1160 /* 31 0 */\r
1161 {0x00000000u},\r
1162 \r
1163 /* resvdTccs */\r
1164 /* 31 0 63 32 */\r
1165 {0x00000000u, 0x00000000u},\r
1166 },\r
1167 \r
1168 /* Resources owned/reserved by region 7 */\r
1169 {\r
1170 /* ownPaRAMSets */\r
1171 /* 31 0 63 32 95 64 127 96 */\r
1172 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1173 /* 159 128 191 160 223 192 255 224 */\r
1174 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1175 /* 287 256 319 288 351 320 383 352 */\r
1176 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1177 /* 415 384 447 416 479 448 511 480 */\r
1178 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1179 \r
1180 /* ownDmaChannels */\r
1181 /* 31 0 63 32 */\r
1182 {0x00000000u, 0x00000000u},\r
1183 \r
1184 /* ownQdmaChannels */\r
1185 /* 31 0 */\r
1186 {0x00000000u},\r
1187 \r
1188 /* ownTccs */\r
1189 /* 31 0 63 32 */\r
1190 {0x00000000u, 0x00000000u},\r
1191 \r
1192 /* resvdPaRAMSets */\r
1193 /* 31 0 63 32 95 64 127 96 */\r
1194 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1195 /* 159 128 191 160 223 192 255 224 */\r
1196 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1197 /* 287 256 319 288 351 320 383 352 */\r
1198 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
1199 /* 415 384 447 416 479 448 511 480 */\r
1200 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
1201 \r
1202 /* resvdDmaChannels */\r
1203 /* 31 0 63 32 */\r
1204 {0x00000000u, 0x00000000u},\r
1205 \r
1206 /* resvdQdmaChannels */\r
1207 /* 31 0 */\r
1208 {0x00000000u},\r
1209 \r
1210 /* resvdTccs */\r
1211 /* 31 0 63 32 */\r
1212 {0x00000000u, 0x00000000u},\r
1213 },\r
1214 },\r
1215 \r
1216 };\r
1217 \r
1218 /* End of File */\r