1 /*\r
2 * sample_tci6616_int_reg.c\r
3 *\r
4 * Platform specific interrupt registration and un-registration routines.\r
5 *\r
6 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
7 *\r
8 *\r
9 * Redistribution and use in source and binary forms, with or without\r
10 * modification, are permitted provided that the following conditions\r
11 * are met:\r
12 *\r
13 * Redistributions of source code must retain the above copyright\r
14 * notice, this list of conditions and the following disclaimer.\r
15 *\r
16 * Redistributions in binary form must reproduce the above copyright\r
17 * notice, this list of conditions and the following disclaimer in the\r
18 * documentation and/or other materials provided with the\r
19 * distribution.\r
20 *\r
21 * Neither the name of Texas Instruments Incorporated nor the names of\r
22 * its contributors may be used to endorse or promote products derived\r
23 * from this software without specific prior written permission.\r
24 *\r
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
36 *\r
37 */\r
38 \r
39 #include <ti/sysbios/knl/Semaphore.h>\r
40 #include <ti/sysbios/hal/Hwi.h>\r
41 #include <ti/sysbios/family/c64p/EventCombiner.h>\r
42 #include <ti/sysbios/family/c66/tci66xx/CpIntc.h>\r
43 \r
44 #include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>\r
45 \r
46 extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];\r
47 extern unsigned int ccErrorInt[];\r
48 extern unsigned int tcErrorInt[][EDMA3_MAX_TC];\r
49 extern unsigned int numEdma3Tc[];\r
50 \r
51 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =\r
52 {\r
53 &lisrEdma3TC0ErrHandler0,\r
54 &lisrEdma3TC1ErrHandler0,\r
55 &lisrEdma3TC2ErrHandler0,\r
56 &lisrEdma3TC3ErrHandler0,\r
57 &lisrEdma3TC4ErrHandler0,\r
58 &lisrEdma3TC5ErrHandler0,\r
59 &lisrEdma3TC6ErrHandler0,\r
60 &lisrEdma3TC7ErrHandler0,\r
61 };\r
62 #if 0\r
63 unsigned int hwiInterrupt = 8;\r
64 \r
65 /* Host interrupts for transfer completion */\r
66 //unsigned int ccXferHostInt[NUM_EDMA3_INSTANCES][NUM_DSPS] = {\r
67 unsigned int ccXferHostInt[3][4] = {\r
68 {32, 24u, 40u, 56u},\r
69 {9u, 25u, 41u, 57u},\r
70 {10u, 26u, 42u, 58u},\r
71 };\r
72 unsigned int edma3ErrHostInt[3][4] = {\r
73 {33, 27u, 43u, 59u},\r
74 {12u, 28u, 44u, 60u},\r
75 {13u, 29u, 45u, 61u},\r
76 };\r
77 \r
78 \r
79 extern unsigned int dsp_num;\r
80 \r
81 /** To Register the ISRs with the underlying OS, if required */\r
82 void registerEdma3Interrupts (unsigned int edma3Id)\r
83 {\r
84 static UInt32 cookie = 0;\r
85 Int eventId = 0; /* GEM event id */\r
86 unsigned int numTc = 0;\r
87 \r
88 /* Disabling the global interrupts */\r
89 cookie = Hwi_disable();\r
90 \r
91 /* Transfer completion ISR */\r
92 #if 1\r
93 CpIntc_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],\r
94 lisrEdma3ComplHandler0,\r
95 edma3Id,\r
96 TRUE);\r
97 CpIntc_mapSysIntToHostInt(0, ccXferCompInt[edma3Id][dsp_num],\r
98 ccXferHostInt[edma3Id][dsp_num]);\r
99 CpIntc_enableHostInt(0, ccXferHostInt[edma3Id][dsp_num]);\r
100 #else\r
101 // Map system interrupt 15 to host interrupt 8\r
102 CpIntc_mapSysIntToHostInt(0, 136, 6);\r
103 \r
104 // Plug the function for event #15\r
105 CpIntc_dispatchPlug(136, lisrEdma3ComplHandler0,edma3Id,TRUE);\r
106 \r
107 // Enable host interrupt #8\r
108 CpIntc_enableHostInt(0,6); // enable host interrupt 8\r
109 #endif\r
110 eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);\r
111 eventId = 0x30;\r
112 EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,\r
113 ccXferHostInt[edma3Id][dsp_num], TRUE);\r
114 EventCombiner_enableEvent(eventId);\r
115 \r
116 /* CC Error ISR */\r
117 CpIntc_dispatchPlug(ccErrorInt[edma3Id], lisrEdma3CCErrHandler0,\r
118 edma3Id, TRUE);\r
119 CpIntc_mapSysIntToHostInt(0, ccErrorInt[edma3Id],\r
120 edma3ErrHostInt[edma3Id][dsp_num]);\r
121 /* TC Error ISR */\r
122 while (numTc < numEdma3Tc[edma3Id])\r
123 {\r
124 CpIntc_dispatchPlug(tcErrorInt[edma3Id][numTc],\r
125 (CpIntc_FuncPtr )(ptrEdma3TcIsrHandler[numTc]),\r
126 edma3Id, TRUE);\r
127 CpIntc_mapSysIntToHostInt(0, tcErrorInt[edma3Id][numTc],\r
128 edma3ErrHostInt[edma3Id][dsp_num]);\r
129 numTc++;\r
130 }\r
131 /* Enable the host interrupt which is common for both CC and TC error */\r
132 CpIntc_enableHostInt(0, edma3ErrHostInt[edma3Id][dsp_num]);\r
133 eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);\r
134 eventId = 0x31;\r
135 EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,\r
136 edma3ErrHostInt[edma3Id][dsp_num], TRUE);\r
137 EventCombiner_enableEvent(eventId);\r
138 \r
139 Hwi_enableInterrupt(hwiInterrupt);\r
140 \r
141 /* enable the 'global' switch */\r
142 CpIntc_enableAllHostInts(0);\r
143 {\r
144 Hwi_Params params;\r
145 CpIntc_mapSysIntToHostInt(0, 0x88, 32); // I picked host int 32 for CPINTC #0. CPINTC #1 is for cores 4-7\r
146 CpIntc_dispatchPlug(0x88, lisrEdma3ComplHandler0, 0, TRUE); // the 'arg' parameter could be anything, doesn't have to be 149\r
147 CpIntc_enableHostInt(0, 32); // CPINT #0 is for cores 0-3, CPINTC #1 is for cores 4-7\r
148 eventId = CpIntc_getEventId(32); // this should return the GEM event 21 (This was a bug fixed in 6.32.04)\r
149 eventId = 0x30;\r
150 Hwi_Params_init(¶ms);\r
151 params.arg = 32; // required to be the host interrupt #\r
152 params.eventId = eventId;\r
153 params.enableInt = TRUE;\r
154 Hwi_create(6, &CpIntc_dispatch, ¶ms, NULL); // create ISR to handle this event in Hwi vector 4\r
155 \r
156 }\r
157 \r
158 /* Restore interrupts */\r
159 Hwi_restore(cookie);\r
160 }\r
161 \r
162 /** To Unregister the ISRs with the underlying OS, if previously registered. */\r
163 void unregisterEdma3Interrupts (unsigned int edma3Id)\r
164 {\r
165 static UInt32 cookie = 0;\r
166 Int eventId = 0; /* GEM event id */\r
167 \r
168 /* Disabling the global interrupts */\r
169 cookie = Hwi_disable();\r
170 \r
171 /* Transfer completion ISR */\r
172 CpIntc_disableHostInt(0, ccXferHostInt[edma3Id][dsp_num]);\r
173 eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);\r
174 EventCombiner_disableEvent(eventId);\r
175 \r
176 /* CC/TC Error ISR */\r
177 CpIntc_disableHostInt(0, edma3ErrHostInt[edma3Id][dsp_num]);\r
178 eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);\r
179 EventCombiner_disableEvent(eventId);\r
180 \r
181 /* Restore interrupts */\r
182 Hwi_restore(cookie);\r
183 }\r
184 \r
185 #else\r
186 /** To Register the ISRs with the underlying OS, if required. */\r
187 void registerEdma3Interrupts (unsigned int edma3Id)\r
188 {\r
189 static UInt32 cookie = 0;\r
190 //unsigned int numTc = 0;\r
191 \r
192 /* Disabling the global interrupts */\r
193 cookie = Hwi_disable();\r
194 \r
195 if(edma3Id == 0)\r
196 {\r
197 /* Enable the Xfer Completion Event Interrupt */\r
198 EventCombiner_dispatchPlug(6,\r
199 (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0),\r
200 edma3Id, 1);\r
201 EventCombiner_enableEvent(6);\r
202 }\r
203 else if(edma3Id == 1)\r
204 {\r
205 /* Enable the Xfer Completion Event Interrupt */\r
206 EventCombiner_dispatchPlug(7,\r
207 (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0),\r
208 edma3Id, 1);\r
209 EventCombiner_enableEvent(7);\r
210 }\r
211 \r
212 \r
213 /**\r
214 * Enabling the HWI_ID.\r
215 * EDMA3 interrupts (transfer completion, CC error etc.)\r
216 * correspond to different ECM events (SoC specific). These ECM events come\r
217 * under ECM block XXX (handling those specific ECM events). Normally, block\r
218 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events\r
219 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)\r
220 * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this\r
221 * mapped HWI_INT YYY, one should use the corresponding bitmask in the\r
222 * API C64_enableIER(), in which the YYY bit is SET.\r
223 */\r
224 Hwi_enableInterrupt(7);\r
225 \r
226 /* Restore interrupts */\r
227 Hwi_restore(cookie);\r
228 }\r
229 \r
230 /** To Unregister the ISRs with the underlying OS, if previously registered. */\r
231 void unregisterEdma3Interrupts (unsigned int edma3Id)\r
232 {\r
233 static UInt32 cookie = 0;\r
234 unsigned int numTc = 0;\r
235 \r
236 /* Disabling the global interrupts */\r
237 cookie = Hwi_disable();\r
238 \r
239 /* Disable the Xfer Completion Event Interrupt */\r
240 EventCombiner_disableEvent(ccXferCompInt[edma3Id][0]);\r
241 \r
242 /* Disable the CC Error Event Interrupt */\r
243 EventCombiner_disableEvent(ccErrorInt[edma3Id]);\r
244 \r
245 /* Enable the TC Error Event Interrupt, according to the number of TCs. */\r
246 while (numTc < numEdma3Tc[edma3Id])\r
247 {\r
248 EventCombiner_disableEvent(tcErrorInt[edma3Id][numTc]);\r
249 numTc++;\r
250 }\r
251 \r
252 /* Restore interrupts */\r
253 Hwi_restore(cookie);\r
254 }\r
255 #endif\r