PRSDK-2194 Remove Library install path
[processor-sdk/audio-preprocessing.git] / realtime_demo_bios / omapl137 / src / mcasp_cfg.c
1 /*
2  * mcasp_cfg.c
3  *
4  * This file contains the test / demo code to demonstrate the Audio component
5  * driver functionality on SYS/BIOS 6.
6  *
7  * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
8  *
9  *
10  *  Redistribution and use in source and binary forms, with or without
11  *  modification, are permitted provided that the following conditions
12  *  are met:
13  *
14  *    Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer.
16  *
17  *    Redistributions in binary form must reproduce the above copyright
18  *    notice, this list of conditions and the following disclaimer in the
19  *    documentation and/or other materials provided with the
20  *    distribution.
21  *
22  *    Neither the name of Texas Instruments Incorporated nor the names of
23  *    its contributors may be used to endorse or promote products derived
24  *    from this software without specific prior written permission.
25  *
26  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37  *
38 */
40 /** \file     mcasp_cfg.c
41  *
42  *  \brief    sample application for demostration of audio playing
43  *
44  *  This file contains the implementation of the sample appliation for the
45  *  demonstration of audio playing through the audio interface layer.
46  *
47  *             (C) Copyright 2017, Texas Instruments, Inc
48  */
50 /* ========================================================================== */
51 /*                            INCLUDE FILES                                   */
52 /* ========================================================================== */
54 #include <xdc/std.h>
55 #include <ti/sysbios/io/IOM.h>
56 #include <xdc/runtime/Memory.h>
57 #include <ti/sysbios/heaps/HeapMem.h>
58 #include <xdc/runtime/IHeap.h>
59 #include <xdc/runtime/Error.h>
60 #include <xdc/runtime/Log.h>
61 #include <xdc/runtime/System.h>
62 #include <ti/sysbios/BIOS.h>
63 #include <ti/sysbios/knl/Semaphore.h>
64 #include <mcasp_drv.h>
65 #include <mcasp_cfg.h>
66 #include <mcasp_tune.h>
67 #include <ti/csl/csl_chip.h>
68 #include <ti/sdo/edma3/drv/edma3_drv.h>
69 #include <ti/sdo/edma3/rm/edma3_rm.h>
70 #include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
71 #include "ICodec.h"
72 #include "stdio.h"
73 #include "string.h"
76 void GblErrXmt(Mcasp_errCbStatus errCbStat);
77 void GblErrRcv(Mcasp_errCbStatus errCbStat);
79 /* ========================================================================== */
80 /*                          IMPORTED VARIABLES                                */
81 /* ========================================================================== */
84 extern EDMA3_DRV_Handle hEdma;
85 extern HeapMem_Handle myHeap;
87 /* ========================================================================== */
88 /*                          McASP Init config                                 */
89 /* ========================================================================== */
93 Mcasp_HwSetupData mcaspRcvSetup = {
94         /* .rmask    = */ 0xFFFFFFFF, /* All the data bits are to be used     */
95 #if defined (DSP_MODE)
96         /* .rfmt     = */ 0x000080f0,
97 #else /* I2S MODE*/
98     /* .rfmt     = */ 0x000180F0,
99 #endif                                                            /* 0/1 bit delay from framsync
100                                        * MSB first
101                                        * No extra bit padding
102                                        * Padding bit (ignore)
103                                        * slot Size is 32
104                                        * Reads from DMA port
105                                        * NO rotation
106                                        */
107 #if defined (MCASP_MASTER)
108         #if defined (DSP_MODE)
109     /* .afsrctl  = */ 0x00000002,           /* burst mode,
110                                              * Frame sync is one bit
111                                              * internally generated frame sync
112                                              * Rising edge is start of frame
113                                              */
115         #else /* I2S MODE*/
116           /* .afsrctl  = */ 0x00000113,     /* I2S mode,
117                                              * Frame sync is one word
118                                              * Internally generated frame sync
119                                              * Falling edge is start of frame
120                                              */
121         #endif
122 #else
123         #if defined (DSP_MODE)
124     /* .afsrctl  = */ 0x00000000,           /* burst mode,
125                                              * Frame sync is one bit
126                                              * Externally generated frame sync
127                                              * Rising edge is start of frame
128                                              */
130         #else /* I2S MODE*/
131           /* .afsrctl  = */ 0x00000111,     /* I2S mode,
132                                              * Frame sync is one word
133                                              * Externally generated frame sync
134                                              * Falling edge is start of frame
135                                              */
136         #endif
137 #endif
139 #if defined (DSP_MODE)
140 /* .rtdm     = */ 0x00000001,           /* slot 1 is active (DSP)
141                                          *              */
143 #else /* I2S MODE*/
144       /* .rtdm     = */ 0x00000003,     /* 2 slots are active (I2S)
145                                          *            */
146 #endif
147         /* .rintctl  = */ 0x00000000, /* sync error and overrun error         */
148         /* .rstat    = */ 0x000001FF, /* reset any existing status bits       */
149         /* .revtctl  = */ 0x00000000, /* DMA request is enabled or disabled   */
150         {
151 #if defined (MCASP_MASTER)
152                 #if defined (DSP_MODE)
153                         /* .aclkrctl  = */ 0x00000020,
154                         /* .ahclkrctl = */ 0x00008001,
155                 #else /* I2S MODE*/
156                         /* .aclkrctl  = */ 0x000000A3,  /* Div (4), Internal Source, rising edge */
157                         /* .ahclkrctl = */ 0x00008005,  /* Div (6), Internal AUX_CLK Source */
158                 #endif
159 #else
160                 #if defined (DSP_MODE)
161                         /* .aclkrctl  = */ 0x00000000,
162                 #else /* I2S MODE*/
163                         /* .aclkrctl  = */ 0x00000080,  /* External Source, rising edge */
164                 #endif
165                         /* .ahclkrctl = */ 0x00000000,  /* Don't Care */
166 #endif
167              /* .rclkchk   = */ 0x00000000
168         }
169 } ;
171 Mcasp_HwSetupData mcaspXmtSetup = {
172         /* .xmask    = */ 0xFFFFFFFF, /* All the data bits are to be used     */
173                 #if defined (DSP_MODE)
174                         /* .xfmt     = */ 0x000080F0,
175                 #else /* I2S MODE*/
176                         /* .xfmt     = */ 0x000180F0,
177                 #endif                                            /*
178                                        * 0/1 bit delay from framsync
179                                        * MSB first
180                                        * No extra bit padding
181                                        * Padding bit (ignore)
182                                        * slot Size is 32
183                                        * Reads from DMA port
184                                        * 0-bit rotation
185                                        */
186 #if defined (MCASP_MASTER)
187                 #if defined (DSP_MODE)
188                 /* .afsxctl  = */ 0x00000002,       /* burst mode,
189                                                                                          * Frame sync is one bit
190                                                                                          * Internally generated frame sync
191                                                                                          * Rising edge is start of frame
192                                                                                          */
193                 /* .xtdm     = */ 0x00000001,       /* slot 1 is active (DSP) */
194                 #else /*I2S MODE*/
195                           /* .afsxctl  = */ 0x00000113, /* I2S mode,
196                                                                                          * Frame sync is one word
197                                                                                          * internally generated frame sync
198                                                                                          * Falling edge is start of frame
199                                                                                          */
200                           /* .xtdm     = */ 0x00000003, /* 2 slots are active (I2S) */
201                 #endif
202 #else
203                 #if defined (DSP_MODE)
204                 /* .afsxctl  = */ 0x00000000,       /* burst mode,
205                                                                                          * Frame sync is one bit
206                                                                                          * Rising edge is start of frame
207                                                                                          * externally generated frame sync
208                                                                                          */
209                 /* .xtdm     = */ 0x00000001,       /* slot 1 is active (DSP) */
210                 #else /*I2S MODE*/
211                           /* .afsxctl  = */ 0x00000111, /* I2S mode,
212                                                                                          * Frame sync is one word
213                                                                                          * Externally generated frame sync
214                                                                                          * Falling edge is start of frame
215                                                                                          */
216                           /* .xtdm     = */ 0x00000003, /* 2 slots are active (I2S) */
217                 #endif
218 #endif
219         /* .xintctl  = */ 0x00000000, /* sync error,overrun error,clK error   */
220         /* .xstat    = */ 0x000001FF, /* reset any existing status bits       */
221         /* .xevtctl  = */ 0x00000000, /* DMA request is enabled or disabled   */
222         {
223 #if defined (MCASP_MASTER)
224         #if defined (DSP_MODE)
225                         /* .aclkxctl  = */ 0x00000027,
226                         /* .ahclkxctl = */ 0x00008001,
228                 #else /* I2S MODE*/
229                         /* .aclkxctl  = */ 0x000000E3, /* Div (4), Internal Source, SYNC, Falling edge */
230                         /* .ahclkxctl = */ 0x00008005, /* Div (6), Internal AUX_CLK Source */
231                 #endif
232 #else
233                 #if defined (DSP_MODE)
234                         /* .aclkxctl  = */ 0x00000000,  /* External Source, SYNC */
236                 #else /* I2S MODE*/
237                         /* .aclkxctl  = */ 0x00000080, /* External Source, SYNC, Falling edge */
238                 #endif
239 #endif
240              /* .xclkchk   = */ 0x00000000
241         },
243 };
245 /* McAsp channel parameters                                  */
246 Mcasp_ChanParams  mcasp_chanparam[2]=
248     {
249         RX_NUM_SERIALIZER,                    /* number of serialisers      */
250         {Mcasp_SerializerNum_1,                           /* serialiser index           */
251         Mcasp_SerializerNum_3,
252                 Mcasp_SerializerNum_2,
253                 Mcasp_SerializerNum_10},
254         &mcaspRcvSetup,
255         TRUE,
256         Mcasp_OpMode_TDM,          /* Mode (TDM/DIT)             */
257         Mcasp_WordLength_32,
258         NULL,
259         0,
260         NULL,
261                 (Mcasp_GblCallback)&GblErrRcv,
262 #if defined (DSP_MODE)
263         1,
264                 Mcasp_BufferFormat_1SER_1SLOT,
265 #else      /* I2S MODE*/
266         2, /* number of TDM channels      */
267                 Mcasp_BufferFormat_MULTISER_MULTISLOT_SEMI_INTERLEAVED_1,
268 #endif
269         TRUE,
270                 RX_FIFO_EVENT_DMA_RATIO,
271         FALSE
272     },
273     {
274         TX_NUM_SERIALIZER,                   /* number of serialisers       */
275         {Mcasp_SerializerNum_5,},
276         &mcaspXmtSetup,
277         TRUE,
278         Mcasp_OpMode_TDM,
279         Mcasp_WordLength_32,      /* word width                  */
280         NULL,
281         0,
282         NULL,
283                 (Mcasp_GblCallback)&GblErrXmt,
284 #if defined (DSP_MODE)
285         1,
286                 Mcasp_BufferFormat_1SER_1SLOT,
287 #else      /* I2S MODE*/
288         2, /* number of TDM channels      */
289                 Mcasp_BufferFormat_1SER_MULTISLOT_INTERLEAVED,
290 #endif
291         TRUE,
292         TX_FIFO_EVENT_DMA_RATIO,
293         FALSE
294     }
295 };
297 /*
298  * ======== createStreams ========
299  */
300 ICodec_ChannelConfig AIC31_config =
302                 16000,  /* sampling rate for codec */
303                 70,  /* gain (%) for codec      */
304                 0x00,
305                 0x00
306 };