1 /*
2 * mcasp_cfg.c
3 *
4 * This file contains the test / demo code to demonstrate the Audio component
5 * driver functionality on SYS/BIOS 6.
6 *
7 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
8 *
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 *
14 * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the
20 * distribution.
21 *
22 * Neither the name of Texas Instruments Incorporated nor the names of
23 * its contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 */
40 /** \file mcasp_cfg.c
41 *
42 * \brief sample application for demostration of audio playing
43 *
44 * This file contains the implementation of the sample appliation for the
45 * demonstration of audio playing through the audio interface layer.
46 *
47 * (C) Copyright 2017, Texas Instruments, Inc
48 */
50 /* ========================================================================== */
51 /* INCLUDE FILES */
52 /* ========================================================================== */
54 #include <xdc/std.h>
55 #include <ti/sysbios/io/IOM.h>
56 #include <xdc/runtime/Memory.h>
57 #include <ti/sysbios/heaps/HeapMem.h>
58 #include <xdc/runtime/IHeap.h>
59 #include <xdc/runtime/Error.h>
60 #include <xdc/runtime/Log.h>
61 #include <xdc/runtime/System.h>
62 #include <ti/sysbios/BIOS.h>
63 #include <ti/sysbios/knl/Semaphore.h>
64 #include <mcasp_drv.h>
65 #include <mcasp_cfg.h>
66 #include <mcasp_tune.h>
67 #include <ti/csl/csl_chip.h>
68 #include <ti/sdo/edma3/drv/edma3_drv.h>
69 #include <ti/sdo/edma3/rm/edma3_rm.h>
70 #include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
71 #include "ICodec.h"
72 #include "stdio.h"
73 #include "string.h"
76 void GblErrXmt(Mcasp_errCbStatus errCbStat);
77 void GblErrRcv(Mcasp_errCbStatus errCbStat);
79 /* ========================================================================== */
80 /* IMPORTED VARIABLES */
81 /* ========================================================================== */
84 extern EDMA3_DRV_Handle hEdma;
85 extern HeapMem_Handle myHeap;
87 /* ========================================================================== */
88 /* McASP Init config */
89 /* ========================================================================== */
92 #define TX_FIFO_EVENT_DMA_RATIO 1
93 #define RX_FIFO_EVENT_DMA_RATIO 1
95 Mcasp_HwSetupData mcaspRcvSetup = {
96 /* .rmask = */ 0xFFFFFFFF, /* All the data bits are to be used */
97 #if defined (DSP_MODE)
98 /* .rfmt = */ 0x000080f0,
99 #else /* I2S MODE*/
100 /* .rfmt = */ 0x000180F0,
101 #endif /* 0/1 bit delay from framsync
102 * MSB first
103 * No extra bit padding
104 * Padding bit (ignore)
105 * slot Size is 32
106 * Reads from DMA port
107 * NO rotation
108 */
109 #if defined (MCASP_MASTER)
110 #if defined (DSP_MODE)
111 /* .afsrctl = */ 0x00000002, /* burst mode,
112 * Frame sync is one bit
113 * internally generated frame sync
114 * Rising edge is start of frame
115 */
117 #else /* I2S MODE*/
118 /* .afsrctl = */ 0x00000113, /* I2S mode,
119 * Frame sync is one word
120 * Internally generated frame sync
121 * Falling edge is start of frame
122 */
123 #endif
124 #else
125 #if defined (DSP_MODE)
126 /* .afsrctl = */ 0x00000000, /* burst mode,
127 * Frame sync is one bit
128 * Externally generated frame sync
129 * Rising edge is start of frame
130 */
132 #else /* I2S MODE*/
133 /* .afsrctl = */ 0x00000111, /* I2S mode,
134 * Frame sync is one word
135 * Externally generated frame sync
136 * Falling edge is start of frame
137 */
138 #endif
139 #endif
141 #if defined (DSP_MODE)
142 /* .rtdm = */ 0x00000001, /* slot 1 is active (DSP)
143 * */
145 #else /* I2S MODE*/
146 /* .rtdm = */ 0x00000003, /* 2 slots are active (I2S)
147 * */
148 #endif
149 /* .rintctl = */ 0x00000000, /* sync error and overrun error */
150 /* .rstat = */ 0x000001FF, /* reset any existing status bits */
151 /* .revtctl = */ 0x00000000, /* DMA request is enabled or disabled */
152 {
153 #if defined (MCASP_MASTER)
154 #if defined (DSP_MODE)
155 /* .aclkrctl = */ 0x00000020,
156 /* .ahclkrctl = */ 0x00008001,
157 #else /* I2S MODE*/
158 /* .aclkrctl = */ 0x000000A3, /* Div (4), Internal Source, rising edge */
159 /* .ahclkrctl = */ 0x00008005, /* Div (6), Internal AUX_CLK Source */
160 #endif
161 #else
162 #if defined (DSP_MODE)
163 /* .aclkrctl = */ 0x00000000,
164 #else /* I2S MODE*/
165 /* .aclkrctl = */ 0x00000080, /* External Source, rising edge */
166 #endif
167 /* .ahclkrctl = */ 0x00000000, /* Don't Care */
168 #endif
169 /* .rclkchk = */ 0x00000000
170 }
171 } ;
173 Mcasp_HwSetupData mcaspXmtSetup = {
174 /* .xmask = */ 0xFFFFFFFF, /* All the data bits are to be used */
175 #if defined (DSP_MODE)
176 /* .xfmt = */ 0x000080F0,
177 #else /* I2S MODE*/
178 /* .xfmt = */ 0x000180F0,
179 #endif /*
180 * 0/1 bit delay from framsync
181 * MSB first
182 * No extra bit padding
183 * Padding bit (ignore)
184 * slot Size is 32
185 * Reads from DMA port
186 * 0-bit rotation
187 */
188 #if defined (MCASP_MASTER)
189 #if defined (DSP_MODE)
190 /* .afsxctl = */ 0x00000002, /* burst mode,
191 * Frame sync is one bit
192 * Internally generated frame sync
193 * Rising edge is start of frame
194 */
195 /* .xtdm = */ 0x00000001, /* slot 1 is active (DSP) */
196 #else /*I2S MODE*/
197 /* .afsxctl = */ 0x00000113, /* I2S mode,
198 * Frame sync is one word
199 * internally generated frame sync
200 * Falling edge is start of frame
201 */
202 /* .xtdm = */ 0x00000003, /* 2 slots are active (I2S) */
203 #endif
204 #else
205 #if defined (DSP_MODE)
206 /* .afsxctl = */ 0x00000000, /* burst mode,
207 * Frame sync is one bit
208 * Rising edge is start of frame
209 * externally generated frame sync
210 */
211 /* .xtdm = */ 0x00000001, /* slot 1 is active (DSP) */
212 #else /*I2S MODE*/
213 /* .afsxctl = */ 0x00000111, /* I2S mode,
214 * Frame sync is one word
215 * Externally generated frame sync
216 * Falling edge is start of frame
217 */
218 /* .xtdm = */ 0x00000003, /* 2 slots are active (I2S) */
219 #endif
220 #endif
221 /* .xintctl = */ 0x00000000, /* sync error,overrun error,clK error */
222 /* .xstat = */ 0x000001FF, /* reset any existing status bits */
223 /* .xevtctl = */ 0x00000000, /* DMA request is enabled or disabled */
224 {
225 #if defined (MCASP_MASTER)
226 #if defined (DSP_MODE)
227 /* .aclkxctl = */ 0x00000027,
228 /* .ahclkxctl = */ 0x00008001,
230 #else /* I2S MODE*/
231 /* .aclkxctl = */ 0x000000E3, /* Div (4), Internal Source, SYNC, Falling edge */
232 /* .ahclkxctl = */ 0x00008005, /* Div (6), Internal AUX_CLK Source */
233 #endif
234 #else
235 #if defined (DSP_MODE)
236 /* .aclkxctl = */ 0x00000000, /* External Source, SYNC */
238 #else /* I2S MODE*/
239 /* .aclkxctl = */ 0x00000080, /* External Source, SYNC, Falling edge */
240 #endif
241 #endif
242 /* .xclkchk = */ 0x00000000
243 },
245 };
247 /* McAsp channel parameters */
248 Mcasp_ChanParams mcasp_chanparam[2]=
249 {
250 {
251 RX_NUM_SERIALIZER, /* number of serialisers */
252 {Mcasp_SerializerNum_1, /* serialiser index */
253 Mcasp_SerializerNum_3,
254 Mcasp_SerializerNum_2,
255 Mcasp_SerializerNum_10},
256 &mcaspRcvSetup,
257 TRUE,
258 Mcasp_OpMode_TDM, /* Mode (TDM/DIT) */
259 Mcasp_WordLength_32,
260 NULL,
261 0,
262 NULL,
263 (Mcasp_GblCallback)&GblErrRcv,
264 #if defined (DSP_MODE)
265 1,
266 Mcasp_BufferFormat_1SER_1SLOT,
267 #else /* I2S MODE*/
268 2, /* number of TDM channels */
269 Mcasp_BufferFormat_MULTISER_MULTISLOT_SEMI_INTERLEAVED_1,
270 #endif
271 TRUE,
272 RX_FIFO_EVENT_DMA_RATIO,
273 TRUE,
274 Mcasp_WordBitsSelect_LSB
275 },
276 {
277 TX_NUM_SERIALIZER, /* number of serialisers */
278 {Mcasp_SerializerNum_5,},
279 &mcaspXmtSetup,
280 TRUE,
281 Mcasp_OpMode_TDM,
282 Mcasp_WordLength_32, /* word width */
283 NULL,
284 0,
285 NULL,
286 (Mcasp_GblCallback)&GblErrXmt,
287 #if defined (DSP_MODE)
288 1,
289 Mcasp_BufferFormat_1SER_1SLOT,
290 #else /* I2S MODE*/
291 2, /* number of TDM channels */
292 Mcasp_BufferFormat_1SER_MULTISLOT_INTERLEAVED,
293 #endif
294 TRUE,
295 TX_FIFO_EVENT_DMA_RATIO,
296 TRUE,
297 Mcasp_WordBitsSelect_LSB
298 }
299 };
301 /*
302 * ======== createStreams ========
303 */
304 ICodec_ChannelConfig AIC31_config =
305 {
306 16000, /* sampling rate for codec */
307 70, /* gain (%) for codec */
308 0x00,
309 0x00
310 };