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raw | patch | inline | side by side (parent: 6403b51)
raw | patch | inline | side by side (parent: 6403b51)
author | Ming Wei <a0868762@ti.com> | |
Thu, 9 Feb 2017 19:05:32 +0000 (13:05 -0600) | ||
committer | Ming Wei <a0868762@ti.com> | |
Thu, 9 Feb 2017 19:05:32 +0000 (13:05 -0600) |
Signed-off-by: Ming Wei <a0868762@ti.com>
realtime_demo_bios/k2g/src/main.c | patch | blob | history | |
realtime_demo_bios/k2g/src/mcasp_cfg.c | patch | blob | history |
index 3fad93c860b416f29c1857086fe621e8f34ea5c1..40fe00de22099ece9fc7fa1ed6ef23d4606ce08a 100644 (file)
/* reset Audio ADC module 0 */\r
status = cmb_AudioAdcReset(CMB_ADC_DEVICE_0);\r
cmb_delay(10000);\r
+ /* set PLL for Audio ADC module 0 */\r
+ status = cmb_AudioAdcSetPLL(CMB_ADC_DEVICE_0);\r
+ cmb_delay(200000);\r
+\r
/* reset Audio ADC module 1 */\r
status = cmb_AudioAdcReset(CMB_ADC_DEVICE_1);\r
cmb_delay(10000);\r
index 9c5984fb0d237cc0931e6c75513df6326cbb62f1..b41226db4c5b5ca31ccdc0d508ab4dcf5b23f6bd 100644 (file)
/* .xstat = */ 0x000001FF, /* reset any existing status bits */\r
/* .xevtctl = */ 0x00000000, /* DMA request is enabled or disabled */\r
{\r
- /* .aclkxctl = */ 0X000000E7, /* Bit CLK Pol: falling edge, ASYNC is 1, ACLKX is internal, HF CLK to BCLK divider is 8 */\r
+ /* .aclkxctl = */ 0X000000E3, /* Bit CLK Pol: falling edge, ASYNC is 1, ACLKX is internal, HF CLK to BCLK divider is 4 */\r
/* .ahclkxctl = */ 0x00000000, /* AHCLKX is external */\r
/* .xclkchk = */ 0x00000000\r
},\r