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raw | patch | inline | side by side (parent: 5e4b565)
raw | patch | inline | side by side (parent: 5e4b565)
author | unknown <a0226073@GTLA0226073.am.dhcp.ti.com> | |
Mon, 25 Jul 2016 18:22:23 +0000 (14:22 -0400) | ||
committer | unknown <a0226073@GTLA0226073.am.dhcp.ti.com> | |
Mon, 25 Jul 2016 18:22:23 +0000 (14:22 -0400) |
Signed-off-by: unknown <a0226073@GTLA0226073.am.dhcp.ti.com>
include/audk2g_audio.h | patch | blob | history | |
include/evmc66x_audio_dc_adc.h | patch | blob | history | |
src/audk2g.c | patch | blob | history | |
src/audk2g_dc_adc.c | patch | blob | history |
diff --git a/include/audk2g_audio.h b/include/audk2g_audio.h
index 86837f91d5969e82b2c2d812e6336947afac147b..7a309599b76a32fc2c8a9eff140b0af00341efc2 100644 (file)
--- a/include/audk2g_audio.h
+++ b/include/audk2g_audio.h
/** DAC HW instance count */
#define AUDK2G_AUDIO_DAC_COUNT (2)
/** ADC HW instance count */
-#define AUDK2G_AUDIO_ADC_COUNT (2)
+#define AUDK2G_AUDIO_AUDK2G_ADC_COUNT (2)
/** GPIO number for DIR RST pin - GPIO port 1 */
#define AUDK2G_AUDIO_DIR_RST_GPIO (9)
typedef enum _AdcDevId
{
/** Enables HW ADC device instance 0 for the operation */
- ADC_DEVICE_0 = 0,
+ AUDK2G_ADC_DEVICE_0 = 0,
/** Enables HW ADC device instance 1 for the operation */
- ADC_DEVICE_1,
+ AUDK2G_ADC_DEVICE_1,
/** Enables all the available HW ADC device instances for the operation */
- ADC_DEVICE_ALL
+ AUDK2G_ADC_DEVICE_ALL
} AdcDevId;
typedef enum _AdcChanId
{
/** ADC channel 1 left */
- ADC_CH1_LEFT = 0,
+ AUDK2G_ADC_CH1_LEFT = 0,
/** ADC channel 1 right */
- ADC_CH1_RIGHT,
+ AUDK2G_ADC_CH1_RIGHT,
/** ADC channel 2 left */
- ADC_CH2_LEFT,
+ AUDK2G_ADC_CH2_LEFT,
/** ADC channel 2 right */
- ADC_CH2_RIGHT,
+ AUDK2G_ADC_CH2_RIGHT,
/** All the 4 ADC channels */
- ADC_CH_ALL
+ AUDK2G_ADC_CH_ALL
} AdcChanId;
typedef enum _AdcLeftInputMux
{
/** ADC left channel input disabled */
- ADC_INL_NONE = 0x0,
+ AUDK2G_ADC_INL_NONE = 0x0,
/** Single ended VINL1 is selected as ADC left input */
- ADC_INL_SE_VINL1 = 0x1,
+ AUDK2G_ADC_INL_SE_VINL1 = 0x1,
/** Single ended VINL2 is selected as ADC left input */
- ADC_INL_SE_VINL2 = 0x2,
+ AUDK2G_ADC_INL_SE_VINL2 = 0x2,
/** Single ended VINL2 + VINL1 is selected as ADC left input */
- ADC_INL_SE_VINL2_VINL1 = 0x3,
+ AUDK2G_ADC_INL_SE_VINL2_VINL1 = 0x3,
/** Single ended VINL3 is selected as ADC left input */
- ADC_INL_SE_VINL3 = 0x4,
+ AUDK2G_ADC_INL_SE_VINL3 = 0x4,
/** Single ended VINL3 + VINL1 is selected as ADC left input */
- ADC_INL_SE_VINL3_VINL1 = 0x5,
+ AUDK2G_ADC_INL_SE_VINL3_VINL1 = 0x5,
/** Single ended VINL3 + VINL2 is selected as ADC left input */
- ADC_INL_SE_VINL3_VINL2 = 0x6,
+ AUDK2G_ADC_INL_SE_VINL3_VINL2 = 0x6,
/** Single ended VINL3 + VINL2 + VINL1 is selected as ADC left input */
- ADC_INL_SE_VINL3_VINL2_VINL1 = 0x7,
+ AUDK2G_ADC_INL_SE_VINL3_VINL2_VINL1 = 0x7,
/** Single ended VINL4 is selected as ADC left input */
- ADC_INL_SE_VINL4 = 0x8,
+ AUDK2G_ADC_INL_SE_VINL4 = 0x8,
/** Single ended VINL4 + VINL1 is selected as ADC left input */
- ADC_INL_SE_VINL4_VINL1 = 0x9,
+ AUDK2G_ADC_INL_SE_VINL4_VINL1 = 0x9,
/** Single ended VINL4 + VINL2 is selected as ADC left input */
- ADC_INL_SE_VINL4_VINL2 = 0xA,
+ AUDK2G_ADC_INL_SE_VINL4_VINL2 = 0xA,
/** Single ended VINL4 + VINL2 + VINL1 is selected as ADC left input */
- ADC_INL_SE_VINL4_VINL2_VINL1 = 0xB,
+ AUDK2G_ADC_INL_SE_VINL4_VINL2_VINL1 = 0xB,
/** Single ended VINL4 + VINL3 is selected as ADC left input */
- ADC_INL_SE_VINL4_VINL3 = 0xC,
+ AUDK2G_ADC_INL_SE_VINL4_VINL3 = 0xC,
/** Single ended VINL4 + VINL3 + VINL1 is selected as ADC left input */
- ADC_INL_SE_VINL4_VINL3_VINL1 = 0xD,
+ AUDK2G_ADC_INL_SE_VINL4_VINL3_VINL1 = 0xD,
/** Single ended VINL4 + VINL3 + VINL2 is selected as ADC left input */
- ADC_INL_SE_VINL4_VINL3_VINL2 = 0xE,
+ AUDK2G_ADC_INL_SE_VINL4_VINL3_VINL2 = 0xE,
/** Single ended VINL4 + VINL3 + VINL2 + VINL1 is selected
as ADC left input */
- ADC_INL_SE_VINL4_VINL3_VINL2_VINL1 = 0xF,
+ AUDK2G_ADC_INL_SE_VINL4_VINL3_VINL2_VINL1 = 0xF,
/** Differential VIN1P + VIN1M is selected as ADC left input */
- ADC_INL_DIFF_VIN1P_VIN1M = 0x10,
+ AUDK2G_ADC_INL_DIFF_VIN1P_VIN1M = 0x10,
/** Differential VIN4P + VIN4M is selected as ADC left input */
- ADC_INL_DIFF_VIN4P_VIN4M = 0x20,
+ AUDK2G_ADC_INL_DIFF_VIN4P_VIN4M = 0x20,
/** Differential VIN1P + VIN1M + VIN4P + VIN4M is selected
as ADC left input */
- ADC_INL_DIFF_VIN1P_VIN1M_VIN4P_VIN4M = 0x30
+ AUDK2G_ADC_INL_DIFF_VIN1P_VIN1M_VIN4P_VIN4M = 0x30
} AdcLeftInputMux;
typedef enum _AdcRightInputMux
{
/** ADC right channel input disabled */
- ADC_INR_NONE = 0x0,
+ AUDK2G_ADC_INR_NONE = 0x0,
/** Single ended VINR1 is selected as ADC right input */
- ADC_INR_SE_VINR1 = 0x1,
+ AUDK2G_ADC_INR_SE_VINR1 = 0x1,
/** Single ended VINR2 is selected as ADC right input */
- ADC_INR_SE_VINR2 = 0x2,
+ AUDK2G_ADC_INR_SE_VINR2 = 0x2,
/** Single ended VINR2 + VINR1 is selected as ADC right input */
- ADC_INR_SE_VINR2_VINR1 = 0x3,
+ AUDK2G_ADC_INR_SE_VINR2_VINR1 = 0x3,
/** Single ended VINR3 is selected as ADC right input */
- ADC_INR_SE_VINR3 = 0x4,
+ AUDK2G_ADC_INR_SE_VINR3 = 0x4,
/** Single ended VINR3 + VINR1 is selected as ADC right input */
- ADC_INR_SE_VINR3_VINR1 = 0x5,
+ AUDK2G_ADC_INR_SE_VINR3_VINR1 = 0x5,
/** Single ended VINR3 + VINR2 is selected as ADC right input */
- ADC_INR_SE_VINR3_VINR2 = 0x6,
+ AUDK2G_ADC_INR_SE_VINR3_VINR2 = 0x6,
/** Single ended VINR3 + VINR2 + VINR1 is selected as ADC right input */
- ADC_INR_SE_VINR3_VINR2_VINR1 = 0x7,
+ AUDK2G_ADC_INR_SE_VINR3_VINR2_VINR1 = 0x7,
/** Single ended VINR4 is selected as ADC right input */
- ADC_INL_SE_VINR4 = 0x8,
+ AUDK2G_ADC_INL_SE_VINR4 = 0x8,
/** Single ended VINR4 + VINR1 is selected as ADC right input */
- ADC_INR_SE_VINR4_VINR1 = 0x9,
+ AUDK2G_ADC_INR_SE_VINR4_VINR1 = 0x9,
/** Single ended VINR4 + VINR2 is selected as ADC right input */
- ADC_INR_SE_VINR4_VINR2 = 0xA,
+ AUDK2G_ADC_INR_SE_VINR4_VINR2 = 0xA,
/** Single ended VINR4 + VINR2 + VINR1 is selected as ADC right input */
- ADC_INR_SE_VINR4_VINR2_VINR1 = 0xB,
+ AUDK2G_ADC_INR_SE_VINR4_VINR2_VINR1 = 0xB,
/** Single ended VINR4 + VINR3 is selected as ADC right input */
- ADC_INR_SE_VINR4_VINR3 = 0xC,
+ AUDK2G_ADC_INR_SE_VINR4_VINR3 = 0xC,
/** Single ended VINR4 + VINR3 + VINR1 is selected as ADC right input */
- ADC_INR_SE_VINR4_VINR3_VINR1 = 0xD,
+ AUDK2G_ADC_INR_SE_VINR4_VINR3_VINR1 = 0xD,
/** Single ended VINR4 + VINR3 + VINR2 is selected as ADC right input */
- ADC_INR_SE_VINR4_VINR3_VINR2 = 0xE,
+ AUDK2G_ADC_INR_SE_VINR4_VINR3_VINR2 = 0xE,
/** Single ended VINR4 + VINR3 + VINR2 + VINR1 is selected
as ADC right input */
- ADC_INR_SE_VINR4_VINR3_VINR2_VINR1 = 0xF,
+ AUDK2G_ADC_INR_SE_VINR4_VINR3_VINR2_VINR1 = 0xF,
/** Differential VIN2P + VIN2M is selected as ADC right input */
- ADC_INR_DIFF_VIN2P_VIN2M = 0x10,
+ AUDK2G_ADC_INR_DIFF_VIN2P_VIN2M = 0x10,
/** Differential VIN4P + VIN4M is selected as ADC right input */
- ADC_INR_DIFF_VIN3P_VIN3M = 0x20,
+ AUDK2G_ADC_INR_DIFF_VIN3P_VIN3M = 0x20,
/** Differential VIN2P + VIN2M + VIN3P + VIN3M is selected
as ADC right input */
- ADC_INR_DIFF_VIN2P_VIN2M_VIN3P_VIN3M = 0x30
+ AUDK2G_ADC_INR_DIFF_VIN2P_VIN2M_VIN3P_VIN3M = 0x30
} AdcRightInputMux;
typedef enum _AdcRxWordLen
{
/** ADC PCM word length selection for 24 bit */
- ADC_RX_WLEN_24BIT = 1,
+ AUDK2G_ADC_RX_WLEN_24BIT = 1,
/** ADC PCM word length selection for 20 bit */
- ADC_RX_WLEN_20BIT = 2,
+ AUDK2G_ADC_RX_WLEN_20BIT = 2,
/** ADC PCM word length selection for 16 bit */
- ADC_RX_WLEN_16BIT = 3
+ AUDK2G_ADC_RX_WLEN_16BIT = 3
} AdcRxWordLen;
typedef enum _AdcDataFormat
{
/** ADC I2S data format */
- ADC_DATA_FORMAT_I2S = 0,
+ AUDK2G_ADC_DATA_FORMAT_I2S = 0,
/** ADC left justified data format */
- ADC_DATA_FORMAT_LEFTJ,
+ AUDK2G_ADC_DATA_FORMAT_LEFTJ,
/** ADC right justified data format */
- ADC_DATA_FORMAT_RIGHTJ,
+ AUDK2G_ADC_DATA_FORMAT_RIGHTJ,
/** ADC TDM/DSP data format */
- ADC_DATA_FORMAT_TDM_DSP
+ AUDK2G_ADC_DATA_FORMAT_TDM_DSP
} AdcDataFormat;
typedef enum _AdcPowerState
{
/** ADC digital standby state */
- ADC_POWER_STATE_STANDBY = 0,
+ AUDK2G_ADC_POWER_STATE_STANDBY = 0,
/** ADC device sleep state */
- ADC_POWER_STATE_SLEEP,
+ AUDK2G_ADC_POWER_STATE_SLEEP,
/** ADC Analog Power Down state */
- ADC_POWER_STATE_POWERDOWN
+ AUDK2G_ADC_POWER_STATE_POWERDOWN
} AdcPowerState;
/**
typedef enum _AdcIntr
{
/** Energysense Interrupt */
- ADC_INTR_ENERGY_SENSE = 0,
+ AUDK2G_ADC_INTR_ENERGY_SENSE = 0,
/** I2S RX DIN toggle Interrupt */
- ADC_INTR_DIN_TOGGLE,
+ AUDK2G_ADC_INTR_DIN_TOGGLE,
/** DC Level Change Interrupt */
- ADC_INTR_DC_CHANGE,
+ AUDK2G_ADC_INTR_DC_CHANGE,
/** Clock Error Interrupt */
- ADC_INTR_CLK_ERR,
+ AUDK2G_ADC_INTR_CLK_ERR,
/** Post-PGA Clipping Interrupt */
- ADC_INTR_POST_PGA_CLIP,
+ AUDK2G_ADC_INTR_POST_PGA_CLIP,
/** To controls all the ADC interrupts together */
- ADC_INTR_ALL
+ AUDK2G_ADC_INTR_ALL
} AdcIntr;
typedef enum _AdcStatus
{
/** Current Power State of the device */
- ADC_STATUS_POWER_STATE = 0,
+ AUDK2G_ADC_STATUS_POWER_STATE = 0,
/** Current Sampling Frequency */
- ADC_STATUS_SAMPLING_FREQ,
+ AUDK2G_ADC_STATUS_SAMPLING_FREQ,
/** Current receiving BCK ratio */
- ADC_STATUS_BCK_RATIO,
+ AUDK2G_ADC_STATUS_BCK_RATIO,
/** Current SCK Ratio */
- ADC_STATUS_SCK_RATIO,
+ AUDK2G_ADC_STATUS_SCK_RATIO,
/** LRCK Halt Status */
- ADC_STATUS_LRCK_HALT,
+ AUDK2G_ADC_STATUS_LRCK_HALT,
/** BCK Halt Status */
- ADC_STATUS_BCK_HALT,
+ AUDK2G_ADC_STATUS_BCK_HALT,
/** SCK Halt Status */
- ADC_STATUS_SCK_HALT,
+ AUDK2G_ADC_STATUS_SCK_HALT,
/** LRCK Error Status */
- ADC_STATUS_LRCK_ERR,
+ AUDK2G_ADC_STATUS_LRCK_ERR,
/** BCK Error Status */
- ADC_STATUS_BCK_ERR,
+ AUDK2G_ADC_STATUS_BCK_ERR,
/** SCK Error Status */
- ADC_STATUS_SCK_ERR,
+ AUDK2G_ADC_STATUS_SCK_ERR,
/** DVDD Status */
- ADC_STATUS_DVDD,
+ AUDK2G_ADC_STATUS_DVDD,
/** AVDD Status */
- ADC_STATUS_AVDD,
+ AUDK2G_ADC_STATUS_AVDD,
/** Digital LDO Status */
- ADC_STATUS_LDO
+ AUDK2G_ADC_STATUS_LDO
} AdcStatus;
typedef enum _AdcDspChanCfg
{
/** ADC DSP 4 channel mode processing */
- ADC_DSP_PROC_4CHAN = 0,
+ AUDK2G_ADC_DSP_PROC_4CHAN = 0,
/** ADC DSP 2 channel mode processing */
- ADC_DSP_PROC_2CHAN
+ AUDK2G_ADC_DSP_PROC_2CHAN
} AdcDspChanCfg;
typedef enum _AdcDspMixNum
{
/** ADC DSP mixer 1 */
- ADC_DSP_MIX1 = 0,
+ AUDK2G_ADC_DSP_MIX1 = 0,
/** ADC DSP mixer 2 */
- ADC_DSP_MIX2,
+ AUDK2G_ADC_DSP_MIX2,
/** ADC DSP mixer 3 */
- ADC_DSP_MIX3,
+ AUDK2G_ADC_DSP_MIX3,
/** ADC DSP mixer 4 */
- ADC_DSP_MIX4,
+ AUDK2G_ADC_DSP_MIX4,
/** To control all the DSP mixers together */
- ADC_DSP_ALL
+ AUDK2G_ADC_DSP_ALL
} AdcDspMixNum;
typedef enum _AdcDspMixChan
{
/** ADC DSP mixer channel 1 left */
- ADC_DSP_MIXCHAN_CH1L = 0,
+ AUDK2G_ADC_DSP_MIXCHAN_CH1L = 0,
/** ADC DSP mixer channel 1 right */
- ADC_DSP_MIXCHAN_CH1R,
+ AUDK2G_ADC_DSP_MIXCHAN_CH1R,
/** ADC DSP mixer channel 2 left */
- ADC_DSP_MIXCHAN_CH2L,
+ AUDK2G_ADC_DSP_MIXCHAN_CH2L,
/** ADC DSP mixer channel 2 right */
- ADC_DSP_MIXCHAN_CH2R,
+ AUDK2G_ADC_DSP_MIXCHAN_CH2R,
/** ADC DSP mixer I2S left */
- ADC_DSP_MIXCHAN_I2SL,
+ AUDK2G_ADC_DSP_MIXCHAN_I2SL,
/** ADC DSP mixer I2S right */
- ADC_DSP_MIXCHAN_I2SR,
+ AUDK2G_ADC_DSP_MIXCHAN_I2SR,
/** To control all the mixer channels together */
- ADC_DSP_MIXCHAN_ALL
+ AUDK2G_ADC_DSP_MIXCHAN_ALL
} AdcDspMixChan;
*
* \return Audk2g_EOK on Success or error code
*/
-Audk2g_STATUS audk2g_platformAudioResetDac(void);
+Audk2g_STATUS audk2g_AudioResetDac(void);
/**
* \brief Configures audio clock source
*
* \return Audk2g_EOK on Success or error code
*/
-Audk2g_STATUS audk2g_platformAudioSelectClkSrc(AudioClkSrc clkSrc);
+Audk2g_STATUS audk2g_AudioSelectClkSrc(AudioClkSrc clkSrc);
/*@}*/ /* defgroup */
* can be changed using the other ADC APIs if required.
*
* \param devId [IN] Device ID of ADC HW instance
- * Use 'ADC_DEVICE_ALL' to initialize
+ * Use 'AUDK2G_ADC_DEVICE_ALL' to initialize
* all the ADC devices available.
*
* \return Audk2g_EOK on Success or error code
*/
-Audk2g_STATUS audk2g_platformAudioAdcInit(AdcDevId devId);
+Audk2g_STATUS audk2g_AudioAdcInit(AdcDevId devId);
/**
* \brief Resets ADC module
* HW default values.
*
* \param devId [IN] Device ID of ADC HW instance
- * Use 'ADC_DEVICE_ALL' to reset
+ * Use 'AUDK2G_ADC_DEVICE_ALL' to reset
* all the ADC devices available.
*
* \return Audk2g_EOK on Success or error code
* 0 indicates minimum gain and 100 indicates maximum gain.
*
* \param devId [IN] Device ID of ADC HW instance
- * Use 'ADC_DEVICE_ALL' to apply the configuration
+ * Use 'AUDK2G_ADC_DEVICE_ALL' to apply the configuration
* for all the ADC devices available.
*
* \param chanId [IN] Internal ADC channel Id
- * Use ADC_CH_ALL to set gain for all the
+ * Use AUDK2G_ADC_CH_ALL to set gain for all the
* ADC channels
*
* \param gain [IN] Gain value; 0 to 100
*
* \return Audk2g_EOK on Success or error code
*/
-Audk2g_STATUS platformAudioAdcSetGain(AdcDevId devId,
+Audk2g_STATUS audk2g_platformAudioAdcSetGain(AdcDevId devId,
AdcChanId chanId,
uint8_t gain);
* CH2 LEFT - VINL2
*
* \param devId [IN] Device ID of ADC HW instance
- * Use 'ADC_DEVICE_ALL' to apply the configuration
+ * Use 'AUDK2G_ADC_DEVICE_ALL' to apply the configuration
* for all the ADC devices available.
*
* \param chanId [IN] Internal ADC channel Id
- * ADC_CH1_LEFT - Input selection for channel 1 left
- * ADC_CH2_LEFT - Input selection for channel 2 left
+ * AUDK2G_ADC_CH1_LEFT - Input selection for channel 1 left
+ * AUDK2G_ADC_CH2_LEFT - Input selection for channel 2 left
*
* \param inputMux [IN] Input mux configuration
*
* CH2_RIGHT - VINR2
*
* \param devId [IN] Device ID of ADC HW instance
- * Use 'ADC_DEVICE_ALL' to apply the configuration
+ * Use 'AUDK2G_ADC_DEVICE_ALL' to apply the configuration
* for all the ADC devices available.
*
* \param chanId [IN] Internal ADC channel Id
- * ADC_CH1_RIGHT - Input selection for channel 1 right
- * ADC_CH2_RIGHT - Input selection for channel 2 right
+ * AUDK2G_ADC_CH1_RIGHT - Input selection for channel 1 right
+ * AUDK2G_ADC_CH2_RIGHT - Input selection for channel 2 right
*
* \param inputMux [IN] Input mux configuration
*
* receive PCM word length for ADC
*
* \param devId [IN] Device ID of ADC HW instance
- * Use 'ADC_DEVICE_ALL' to apply the configuration
+ * Use 'AUDK2G_ADC_DEVICE_ALL' to apply the configuration
* for all the ADC devices available.
*
* \param wLen [IN] ADC data word length
* This function configures mute functionality of each ADC channel
*
* \param devId [IN] Device ID of ADC HW instance
- * Use 'ADC_DEVICE_ALL' to apply the configuration
+ * Use 'AUDK2G_ADC_DEVICE_ALL' to apply the configuration
* for all the ADC devices available.
*
* \param chanId [IN] Internal ADC channel Id
- * Use ADC_CH_ALL to apply mute configuration for
+ * Use AUDK2G_ADC_CH_ALL to apply mute configuration for
* all the ADC channels
*
* \param muteEnable [IN] Flag to configure mute
* This function enables/disables MIC bias for analog MIC input
*
* \param devId [IN] Device ID of ADC HW instance
- * Use 'ADC_DEVICE_ALL' to apply the configuration
+ * Use 'AUDK2G_ADC_DEVICE_ALL' to apply the configuration
* for all the ADC devices available.
*
* \param micBiasEnable [IN] Mic Bias enable flag
* This function enables/disables different power modes supported by ADC
*
* \param devId [IN] Device ID of ADC HW instance
- * Use 'ADC_DEVICE_ALL' to apply the configuration
+ * Use 'AUDK2G_ADC_DEVICE_ALL' to apply the configuration
* for all the ADC devices available.
*
* \param powState [IN] ADC power state to configure
* This function enables/disables different interrupts supported by ADC
*
* \param devId [IN] Device ID of ADC HW instance
- * Use 'ADC_DEVICE_ALL' to apply the configuration
+ * Use 'AUDK2G_ADC_DEVICE_ALL' to apply the configuration
* for all the ADC devices available.
*
* \param intId [IN] Interrupt Id to configure
- * Use to 'ADC_INTR_ALL' to configure all the
+ * Use to 'AUDK2G_ADC_INTR_ALL' to configure all the
* interrupts together
*
* \param intEnable [IN] Interrupt enable flag
* \param devId [IN] Device ID of ADC HW instance
*
* \param intId [IN] Interrupt Id to read the status
- * Use to 'ADC_INTR_ALL' to read status of all the
+ * Use to 'AUDK2G_ADC_INTR_ALL' to read status of all the
* interrupts together
*
* \return Interrupt status
* supported by ADC
*
* \param devId [IN] Device ID of ADC HW instance
- * Use 'ADC_DEVICE_ALL' to apply the configuration
+ * Use 'AUDK2G_ADC_DEVICE_ALL' to apply the configuration
* for all the ADC devices available.
*
* \param chanCfg [IN] DSP channel configuration
* DSP coefficients can be programmed by this function.
*
* \param devId [IN] Device ID of ADC HW instance
- * Use 'ADC_DEVICE_ALL' to apply the configuration
+ * Use 'AUDK2G_ADC_DEVICE_ALL' to apply the configuration
* for all the ADC devices available.
*
* \param coeffRegAddr [IN] Address of DSP coefficient register
* configuration for debug messages.
*
* \param devId [IN] Device ID of ADC HW instance
- * Use 'ADC_DEVICE_ALL' to read the register values
+ * Use 'AUDK2G_ADC_DEVICE_ALL' to read the register values
* for all the ADC devices available.
*
* \return Audk2g_EOK on Success or error code
index 8bfabdbf7dfb77d7bac0fd47de262c8de6fd9fef..3db9c416767062b61d94805e7376162f7bca0540 100644 (file)
*
*/
-#ifndef _EVMC66X_AUDIO_DC_ADC_H_
-#define _EVMC66X_AUDIO_DC_ADC_H_
+#ifndef _EVMC66X_AUDIO_DC_AUDK2G_ADC_H_
+#define _EVMC66X_AUDIO_DC_AUDK2G_ADC_H_
/**************************************************************************
** Macro Definitions
**************************************************************************/
/** Page 0 Register Definitions */
-#define PCM186x_ADC_RESET (0x00)
+#define AUDK2G_PCM186x_ADC_RESET (0x00)
#define PCM186x_PGA_VAL_CH1_L (0x01)
#define PCM186x_PGA_VAL_CH1_R (0x02)
#define PCM186x_PGA_VAL_CH2_L (0x03)
#define PCM186x_PGA_VAL_CH2_R (0x04)
-#define PCM186x_ADC_CH1_L (0x06)
-#define PCM186x_ADC_CH1_R (0x07)
-#define PCM186x_ADC_CH2_L (0x08)
-#define PCM186x_ADC_CH2_R (0x09)
-#define PCM186x_SEC_ADC_CH (0x0A)
+#define AUDK2G_PCM186x_ADC_CH1_L (0x06)
+#define AUDK2G_PCM186x_ADC_CH1_R (0x07)
+#define AUDK2G_PCM186x_ADC_CH2_L (0x08)
+#define AUDK2G_PCM186x_ADC_CH2_R (0x09)
+#define PCM186x_SEC_AUDK2G_ADC_CH (0x0A)
#define PCM186x_AUDIO_FMT (0x0B)
#define PCM186x_DIG_MIC_CTRL (0x1A)
#define PCM186x_SCK_XI_SEL (0x20)
#define PCM186x_MIC_BIAS_CTRL (0x15)
/** Function to calculate DAC input selection register address */
-#define PCM186x_INPUT_SELECT(x) (PCM186x_ADC_CH1_L + x)
+#define PCM186x_INPUT_SELECT(x) (AUDK2G_PCM186x_ADC_CH1_L + x)
/** Function to calculate DAC volume control register address */
#define PCM186x_VOL_CTRL(x) (PCM186x_PGA_VAL_CH1_L + x)
/** Macro to enable register echo in pcm186x_write_reg()
When this macro is enabled, every register written is read back and
its value is displayed by pcm186x_write_reg()*/
-#define ENABLE_ADC_REG_ECHO (1)
+#define ENABLE_AUDK2G_ADC_REG_ECHO (1)
#ifdef DEBUG_PCM186x_ENABLE
#define DBG_PCM186x(x) IFPRINT(x)
#endif
/** ADC API return type */
-typedef Int32 ADC_RET;
+typedef Int32 AUDK2G_ADC_RET;
/**************************************************************************
** Structure Definitions
* \return 0 if success.
*
**/
-ADC_RET pcm186xAdcInit(Uint8 addr);
+AUDK2G_ADC_RET pcm186xAdcInit(Uint8 addr);
/**
* \brief Reads the Current Page no.
* \return 0 if success.
*
**/
-ADC_RET pcm186xRegDump(Uint8 addr);
+AUDK2G_ADC_RET pcm186xRegDump(Uint8 addr);
/**
* \brief Enable/Disable Mic Bias Control for analog MIC input.
* \return 0 if success.
*
*/
-ADC_RET pcm186xMicBiasCtrl(Uint8 addr, Uint8 power);
+AUDK2G_ADC_RET pcm186xMicBiasCtrl(Uint8 addr, Uint8 power);
/**
* \brief Resets PCM1865 ADC. .
* \return 0 if success.
*
**/
-ADC_RET pcm186xReset(Uint8 addr);
+AUDK2G_ADC_RET audk2g_pcm186xReset(Uint8 addr);
/**
* \brief Configures the data format and slot width
* \param addr [IN] ADC HW instance I2C slave address.
*
* \param dataType [IN] Data type for the codec operation
- * ADC_DATA_FORMAT_I2S - for I2S mode
- * ADC_DATA_FORMAT_LEFTJ - for left aligned data
- * ADC_DATA_FORMAT_RIGHTJ - for right aligned data
- * ADC_DATA_FORMAT_TDM_DSP - for TDM/DSP data.
+ * AUDK2G_ADC_DATA_FORMAT_I2S - for I2S mode
+ * AUDK2G_ADC_DATA_FORMAT_LEFTJ - for left aligned data
+ * AUDK2G_ADC_DATA_FORMAT_RIGHTJ - for right aligned data
+ * AUDK2G_ADC_DATA_FORMAT_TDM_DSP - for TDM/DSP data.
*
* \param slotWidth [IN] Slot width in bits
- * ADC_RX_WLEN_24BIT - 24 bit
- * ADC_RX_WLEN_20BIT - 20 bit
- * ADC_RX_WLEN_16BIT - 16 bit
+ * AUDK2G_ADC_RX_WLEN_24BIT - 24 bit
+ * AUDK2G_ADC_RX_WLEN_20BIT - 20 bit
+ * AUDK2G_ADC_RX_WLEN_16BIT - 16 bit
*
* \return 0 if success.
*
**/
-ADC_RET pcm186xDataConfig(Uint8 addr, Uint8 dataType, Uint8 slotWidth);
+AUDK2G_ADC_RET pcm186xDataConfig(Uint8 addr, Uint8 dataType, Uint8 slotWidth);
/**
* \brief Selects input channel for ADC.
* \return 0 for success.
*
**/
-ADC_RET pcm186xInputSel(Uint8 addr, Uint8 channel, Uint8 input);
+AUDK2G_ADC_RET pcm186xInputSel(Uint8 addr, Uint8 channel, Uint8 input);
/**
* \brief Sets the ADC PGA Volume.
* \param vol [IN] Volume in percentage; 0 to 100
*
* \param channel [IN] Channel selection mask
- * ADC_CH1_LEFT - ADC CH1 LEFT
- * ADC_CH1_RIGHT - ADC CH1 RIGHT
- * ADC_CH2_LEFT - ADC CH2 LEFT
- * ADC_CH2_RIGHT - ADC CH2 RIGHT
- * ADC_CH_ALL - All the four channels
+ * AUDK2G_ADC_CH1_LEFT - ADC CH1 LEFT
+ * AUDK2G_ADC_CH1_RIGHT - ADC CH1 RIGHT
+ * AUDK2G_ADC_CH2_LEFT - ADC CH2 LEFT
+ * AUDK2G_ADC_CH2_RIGHT - ADC CH2 RIGHT
+ * AUDK2G_ADC_CH_ALL - All the four channels
*
* \return 0 for success.
*
**/
-ADC_RET pcm186xSetVolume(Uint8 addr, Uint8 vol, Uint8 channel);
+AUDK2G_ADC_RET pcm186xSetVolume(Uint8 addr, Uint8 vol, Uint8 channel);
/**
* \brief Unmute or Mute ADC the Channel.
* \return 0 for success.
*
**/
-ADC_RET pcm186xMuteChannel(Uint8 addr, Uint8 channel, Uint8 mute);
+AUDK2G_ADC_RET pcm186xMuteChannel(Uint8 addr, Uint8 channel, Uint8 mute);
/**
* \brief Unmute or Mute ADC the Channel.
* \param addr [IN] ADC HW instance I2C slave address.
*
* \param powState [IN] ADC power state
- * ADC_POWER_STATE_STANDBY - ADC standby state
- * ADC_POWER_STATE_SLEEP - ADC device sleep state
- * ADC_POWER_STATE_POWERDOWN - ADC Analog Power Down state
+ * AUDK2G_ADC_POWER_STATE_STANDBY - ADC standby state
+ * AUDK2G_ADC_POWER_STATE_SLEEP - ADC device sleep state
+ * AUDK2G_ADC_POWER_STATE_POWERDOWN - ADC Analog Power Down state
*
* \param enable [IN] Mute control
* 1 - Enables the power state
* \return 0 for success.
*
**/
-ADC_RET pcm186xConfigPowState(Uint8 addr, Uint8 powState, Uint8 enable);
+AUDK2G_ADC_RET pcm186xConfigPowState(Uint8 addr, Uint8 powState, Uint8 enable);
/**
* \brief Enables/Disables ADC interrupts.
* \param addr [IN] ADC HW instance I2C slave address.
*
* \param intrNum [IN] ADC interrupt ID
- * ADC_INTR_ENERGY_SENSE - Energysense Interrupt
- * ADC_INTR_DIN_TOGGLE - I2S RX DIN toggle Interrupt
- * ADC_INTR_DC_CHANGE - DC Level Change Interrupt
- * ADC_INTR_CLK_ERR - Clock Error Interrupt
- * ADC_INTR_POST_PGA_CLIP - Post-PGA Clipping Interrupt
- * ADC_INTR_ALL - To controls all the ADC interrupts together
+ * AUDK2G_ADC_INTR_ENERGY_SENSE - Energysense Interrupt
+ * AUDK2G_ADC_INTR_DIN_TOGGLE - I2S RX DIN toggle Interrupt
+ * AUDK2G_ADC_INTR_DC_CHANGE - DC Level Change Interrupt
+ * AUDK2G_ADC_INTR_CLK_ERR - Clock Error Interrupt
+ * AUDK2G_ADC_INTR_POST_PGA_CLIP - Post-PGA Clipping Interrupt
+ * AUDK2G_ADC_INTR_ALL - To controls all the ADC interrupts together
*
* \param enable [IN] Interrupt control
* 1 - Enables the interrupt
* \return 0 for success.
*
**/
-ADC_RET pcm186xSetIntr(Uint8 addr, Uint8 intrNum, Uint8 enable);
+AUDK2G_ADC_RET pcm186xSetIntr(Uint8 addr, Uint8 intrNum, Uint8 enable);
/**
* \brief Reads ADC interrupt status register.
* \param addr [IN] ADC HW instance I2C slave address.
*
* \param channel [IN] Channel configuration
- * ADC_DSP_PROC_4CHAN - ADC DSP 4 channel mode processing
- * ADC_DSP_PROC_2CHAN - ADC DSP 2 channel mode processing
+ * AUDK2G_ADC_DSP_PROC_4CHAN - ADC DSP 4 channel mode processing
+ * AUDK2G_ADC_DSP_PROC_2CHAN - ADC DSP 2 channel mode processing
*
* \return 0 for success.
*
**/
-ADC_RET pcm186xDspCtrl(Uint8 addr, Uint8 channel);
+AUDK2G_ADC_RET pcm186xDspCtrl(Uint8 addr, Uint8 channel);
/**
* \brief Programs ADC DSP coefficients
* \return 0 for success.
*
**/
-ADC_RET pcm186xProgDspCoeff(Uint8 addr, Uint8 regAddr, Uint32 coeff);
+AUDK2G_ADC_RET pcm186xProgDspCoeff(Uint8 addr, Uint8 regAddr, Uint32 coeff);
/**
* \brief Reads ADC power state
**/
Uint8 pcm186xGetLdoStatus(Uint8 addr);
-#endif // _EVMC66X_AUDIO_DC_ADC_H_
+#endif // _EVMC66X_AUDIO_DC_AUDK2G_ADC_H_
/***************************** End Of File ***********************************/
diff --git a/src/audk2g.c b/src/audk2g.c
index 64b37b600f027dc83726fe1eb3e9adc706e4b8b8..3e219d196110f75aed0fdbdb7ca3a1733316c6af 100644 (file)
--- a/src/audk2g.c
+++ b/src/audk2g.c
Uint8 audk2g_gDacI2cAddr[AUDK2G_AUDIO_DAC_COUNT] = {AUDK2G_AUDIO_DAC0_ADDR,
AUDK2G_AUDIO_DAC1_ADDR};
/* ADC HW instance I2C slave address */
-Uint8 audk2g_gAdcI2cAddr[AUDK2G_AUDIO_ADC_COUNT] = {AUDK2G_AUDIO_ADC0_ADDR,
+Uint8 audk2g_gAdcI2cAddr[AUDK2G_AUDIO_AUDK2G_ADC_COUNT] = {AUDK2G_AUDIO_ADC0_ADDR,
AUDK2G_AUDIO_ADC1_ADDR};
/**
*
* \return Audk2g_EOK on Success or error code
*/
-Audk2g_STATUS audk2g_platformAudioResetDac(void)
+Audk2g_STATUS audk2g_AudioResetDac(void)
{
audk2g_gpioClearOutput(AUDK2G_GPIO_PORT_1, AUDK2G_AUDIO_PCM1690_RST_GPIO);
audk2g_delay(1000);
*
* \return Audk2g_EOK on Success or error code
*/
-Audk2g_STATUS audk2g_platformAudioSelectClkSrc(AudioClkSrc clkSrc)
+Audk2g_STATUS audk2g_AudioSelectClkSrc(AudioClkSrc clkSrc)
{
- IFPRINT(audk2g_write("audk2g_platformAudioSelectClkSrc Called \n"));
+ IFPRINT(audk2g_write("audk2g_AudioSelectClkSrc Called \n"));
/* Configure GPIO for McASP_CLK_SEL - GPIO0 132 & AUDK2G_PADCONFIG 163 */
audk2g_pinMuxSetMode(163, AUDK2G_PADCONFIG_MUX_MODE_QUATERNARY);
}
else
{
- IFPRINT(audk2g_write("audk2g_platformAudioSelectClkSrc : Invalid Inputs\n"));
+ IFPRINT(audk2g_write("audk2g_AudioSelectClkSrc : Invalid Inputs\n"));
audk2g_errno = AUDK2G_ERRNO_INVALID_ARGUMENT;
return (Audk2g_EINVALID);
}
* can be changed using the other ADC APIs if required.
*
* \param devId [IN] Device ID of ADC HW instance
- * Use 'ADC_DEVICE_ALL' to initialize
+ * Use 'AUDK2G_ADC_DEVICE_ALL' to initialize
* all the ADC devices available.
*
* \return Audk2g_EOK on Success or error code
*/
-Audk2g_STATUS audk2g_platformAudioAdcInit(AdcDevId devId)
+Audk2g_STATUS audk2g_AudioAdcInit(AdcDevId devId)
{
- ADC_RET retVal;
+ AUDK2G_ADC_RET retVal;
Uint8 id;
- IFPRINT(audk2g_write("audk2g_platformAudioAdcInit Called \n"));
+ IFPRINT(audk2g_write("audk2g_AudioAdcInit Called \n"));
- if(!((devId >= ADC_DEVICE_0) && (devId <= ADC_DEVICE_ALL)))
+ if(!((devId >= AUDK2G_ADC_DEVICE_0) && (devId <= AUDK2G_ADC_DEVICE_ALL)))
{
- IFPRINT(audk2g_write("audk2g_platformAudioAdcInit : Invalid Inputs\n"));
+ IFPRINT(audk2g_write("audk2g_AudioAdcInit : Invalid Inputs\n"));
audk2g_errno = AUDK2G_ERRNO_INVALID_ARGUMENT;
return (Audk2g_EINVALID);
}
- for (id = ADC_DEVICE_0; id < ADC_DEVICE_ALL; id++)
+ for (id = AUDK2G_ADC_DEVICE_0; id < AUDK2G_ADC_DEVICE_ALL; id++)
{
- if((id == devId) || (devId == ADC_DEVICE_ALL))
+ if((id == devId) || (devId == AUDK2G_ADC_DEVICE_ALL))
{
retVal = pcm186xAdcInit(audk2g_gAdcI2cAddr[id]);
if(retVal)
{
- IFPRINT(audk2g_write("audk2g_platformAudioAdcInit : ADC Initialization Failed \n"));
+ IFPRINT(audk2g_write("audk2g_AudioAdcInit : ADC Initialization Failed \n"));
audk2g_errno = AUDK2G_ERRNO_AUDIO_INIT;
return (Audk2g_EFAIL);
}
* HW default values.
*
* \param devId [IN] Device ID of ADC HW instance
- * Use 'ADC_DEVICE_ALL' to reset
+ * Use 'AUDK2G_ADC_DEVICE_ALL' to reset
* all the ADC devices available.
*
* \return Audk2g_EOK on Success or error code
*/
Audk2g_STATUS platformAudioAdcReset(AdcDevId devId)
{
- ADC_RET retVal;
+ AUDK2G_ADC_RET retVal;
Uint8 id;
IFPRINT(audk2g_write("platformAudioAdcReset Called \n"));
- if(!((devId >= ADC_DEVICE_0) && (devId <= ADC_DEVICE_ALL)))
+ if(!((devId >= AUDK2G_ADC_DEVICE_0) && (devId <= AUDK2G_ADC_DEVICE_ALL)))
{
IFPRINT(audk2g_write("platformAudioAdcReset : Invalid Inputs\n"));
audk2g_errno = AUDK2G_ERRNO_INVALID_ARGUMENT;
return (Audk2g_EINVALID);
}
- for (id = ADC_DEVICE_0; id < ADC_DEVICE_ALL; id++)
+ for (id = AUDK2G_ADC_DEVICE_0; id < AUDK2G_ADC_DEVICE_ALL; id++)
{
- if((id == devId) || (devId == ADC_DEVICE_ALL))
+ if((id == devId) || (devId == AUDK2G_ADC_DEVICE_ALL))
{
- retVal = pcm186xReset(audk2g_gAdcI2cAddr[id]);
+ retVal = audk2g_pcm186xReset(audk2g_gAdcI2cAddr[id]);
if(retVal)
{
IFPRINT(audk2g_write("platformAudioAdcReset : ADC Reset Failed \n"));
* 0 indicates minimum gain and 100 indicates maximum gain.
*
* \param devId [IN] Device ID of ADC HW instance
- * Use 'ADC_DEVICE_ALL' to apply the configuration
+ * Use 'AUDK2G_ADC_DEVICE_ALL' to apply the configuration
* for all the ADC devices available.
*
* \param chanId [IN] Internal ADC channel Id
- * Use ADC_CH_ALL to set gain for all the
+ * Use AUDK2G_ADC_CH_ALL to set gain for all the
* ADC channels
*
* \param gain [IN] Gain value; 0 to 100
*
* \return Audk2g_EOK on Success or error code
*/
-Audk2g_STATUS platformAudioAdcSetGain(AdcDevId devId,
+Audk2g_STATUS audk2g_platformAudioAdcSetGain(AdcDevId devId,
AdcChanId chanId,
uint8_t gain)
{
- ADC_RET retVal;
+ AUDK2G_ADC_RET retVal;
Uint8 id;
- IFPRINT(audk2g_write("platformAudioAdcSetGain Called \n"));
+ IFPRINT(audk2g_write("audk2g_platformAudioAdcSetGain Called \n"));
- if( !( ((devId >= ADC_DEVICE_0) && (devId <= ADC_DEVICE_ALL)) &&
- ((chanId >= ADC_CH1_LEFT) && (chanId <= ADC_CH_ALL)) &&
+ if( !( ((devId >= AUDK2G_ADC_DEVICE_0) && (devId <= AUDK2G_ADC_DEVICE_ALL)) &&
+ ((chanId >= AUDK2G_ADC_CH1_LEFT) && (chanId <= AUDK2G_ADC_CH_ALL)) &&
(gain <= 100) ) )
{
- IFPRINT(audk2g_write("platformAudioAdcSetGain : Invalid Inputs\n"));
+ IFPRINT(audk2g_write("audk2g_platformAudioAdcSetGain : Invalid Inputs\n"));
audk2g_errno = AUDK2G_ERRNO_INVALID_ARGUMENT;
return (Audk2g_EINVALID);
}
- for (id = ADC_DEVICE_0; id < ADC_DEVICE_ALL; id++)
+ for (id = AUDK2G_ADC_DEVICE_0; id < AUDK2G_ADC_DEVICE_ALL; id++)
{
- if((id == devId) || (devId == ADC_DEVICE_ALL))
+ if((id == devId) || (devId == AUDK2G_ADC_DEVICE_ALL))
{
retVal = pcm186xSetVolume(audk2g_gAdcI2cAddr[id], (Uint8)gain,
(Uint8)chanId);
if(retVal)
{
- IFPRINT(audk2g_write("platformAudioAdcSetGain : ADC Access for Gain Config Failed \n"));
+ IFPRINT(audk2g_write("audk2g_platformAudioAdcSetGain : ADC Access for Gain Config Failed \n"));
audk2g_errno = AUDK2G_ERRNO_AUDIO_CFG;
return (Audk2g_EFAIL);
}
* CH2 LEFT - VINL2
*
* \param devId [IN] Device ID of ADC HW instance
- * Use 'ADC_DEVICE_ALL' to apply the configuration
+ * Use 'AUDK2G_ADC_DEVICE_ALL' to apply the configuration
* for all the ADC devices available.
*
* \param chanId [IN] Internal ADC channel Id
- * ADC_CH1_LEFT - Input selection for channel 1 left
- * ADC_CH2_LEFT - Input selection for channel 2 left
- * ADC_CH_ALL - Input selection for channel 1 & 2 left
+ * AUDK2G_ADC_CH1_LEFT - Input selection for channel 1 left
+ * AUDK2G_ADC_CH2_LEFT - Input selection for channel 2 left
+ * AUDK2G_ADC_CH_ALL - Input selection for channel 1 & 2 left
*
* \param inputMux [IN] Input mux configuration
*
AdcChanId chanId,
AdcLeftInputMux inputMux)
{
- ADC_RET retVal;
+ AUDK2G_ADC_RET retVal;
Uint8 id;
IFPRINT(audk2g_write("platformAudioAdcSetLeftInputMux Called \n"));
- if( !( ((devId >= ADC_DEVICE_0) && (devId <= ADC_DEVICE_ALL)) &&
- ((chanId == ADC_CH1_LEFT) || (chanId == ADC_CH2_LEFT) ||
- (chanId == ADC_CH_ALL)) &&
- ((inputMux >= ADC_INL_NONE) &&
- (inputMux <= ADC_INL_DIFF_VIN1P_VIN1M_VIN4P_VIN4M)) ) )
+ if( !( ((devId >= AUDK2G_ADC_DEVICE_0) && (devId <= AUDK2G_ADC_DEVICE_ALL)) &&
+ ((chanId == AUDK2G_ADC_CH1_LEFT) || (chanId == AUDK2G_ADC_CH2_LEFT) ||
+ (chanId == AUDK2G_ADC_CH_ALL)) &&
+ ((inputMux >= AUDK2G_ADC_INL_NONE) &&
+ (inputMux <= AUDK2G_ADC_INL_DIFF_VIN1P_VIN1M_VIN4P_VIN4M)) ) )
{
IFPRINT(audk2g_write("platformAudioAdcSetLeftInputMux : Invalid Inputs\n"));
audk2g_errno = AUDK2G_ERRNO_INVALID_ARGUMENT;
return (Audk2g_EINVALID);
}
- for (id = ADC_DEVICE_0; id < ADC_DEVICE_ALL; id++)
+ for (id = AUDK2G_ADC_DEVICE_0; id < AUDK2G_ADC_DEVICE_ALL; id++)
{
- if((id == devId) || (devId == ADC_DEVICE_ALL))
+ if((id == devId) || (devId == AUDK2G_ADC_DEVICE_ALL))
{
- if(chanId == ADC_CH_ALL)
+ if(chanId == AUDK2G_ADC_CH_ALL)
{
- retVal = pcm186xInputSel(audk2g_gAdcI2cAddr[id], (Uint8)ADC_CH1_LEFT,
+ retVal = pcm186xInputSel(audk2g_gAdcI2cAddr[id], (Uint8)AUDK2G_ADC_CH1_LEFT,
(Uint8)inputMux);
if(retVal)
{
return (Audk2g_EFAIL);
}
- retVal = pcm186xInputSel(audk2g_gAdcI2cAddr[id], (Uint8)ADC_CH2_LEFT,
+ retVal = pcm186xInputSel(audk2g_gAdcI2cAddr[id], (Uint8)AUDK2G_ADC_CH2_LEFT,
(Uint8)inputMux);
}
else
* CH2_RIGHT - VINR2
*
* \param devId [IN] Device ID of ADC HW instance
- * Use 'ADC_DEVICE_ALL' to apply the configuration
+ * Use 'AUDK2G_ADC_DEVICE_ALL' to apply the configuration
* for all the ADC devices available.
*
* \param chanId [IN] Internal ADC channel Id
- * ADC_CH1_RIGHT - Input selection for channel 1 right
- * ADC_CH2_RIGHT - Input selection for channel 2 right
- * ADC_CH_ALL - Input selection for channel 1 & 2 right
+ * AUDK2G_ADC_CH1_RIGHT - Input selection for channel 1 right
+ * AUDK2G_ADC_CH2_RIGHT - Input selection for channel 2 right
+ * AUDK2G_ADC_CH_ALL - Input selection for channel 1 & 2 right
*
* \param inputMux [IN] Input mux configuration
*
AdcChanId chanId,
AdcRightInputMux inputMux)
{
- ADC_RET retVal;
+ AUDK2G_ADC_RET retVal;
Uint8 id;
IFPRINT(audk2g_write("platformAudioAdcSetRightInputMux Called \n"));
- if( !( ((devId >= ADC_DEVICE_0) && (devId <= ADC_DEVICE_ALL)) &&
- ((chanId == ADC_CH1_RIGHT) || (chanId == ADC_CH2_RIGHT) ||
- (chanId == ADC_CH_ALL)) &&
- ((inputMux >= ADC_INR_NONE) &&
- (inputMux <= ADC_INR_DIFF_VIN2P_VIN2M_VIN3P_VIN3M)) ) )
+ if( !( ((devId >= AUDK2G_ADC_DEVICE_0) && (devId <= AUDK2G_ADC_DEVICE_ALL)) &&
+ ((chanId == AUDK2G_ADC_CH1_RIGHT) || (chanId == AUDK2G_ADC_CH2_RIGHT) ||
+ (chanId == AUDK2G_ADC_CH_ALL)) &&
+ ((inputMux >= AUDK2G_ADC_INR_NONE) &&
+ (inputMux <= AUDK2G_ADC_INR_DIFF_VIN2P_VIN2M_VIN3P_VIN3M)) ) )
{
IFPRINT(audk2g_write("platformAudioAdcSetRightInputMux : Invalid Inputs\n"));
audk2g_errno = AUDK2G_ERRNO_INVALID_ARGUMENT;
return (Audk2g_EINVALID);
}
- for (id = ADC_DEVICE_0; id < ADC_DEVICE_ALL; id++)
+ for (id = AUDK2G_ADC_DEVICE_0; id < AUDK2G_ADC_DEVICE_ALL; id++)
{
- if((id == devId) || (devId == ADC_DEVICE_ALL))
+ if((id == devId) || (devId == AUDK2G_ADC_DEVICE_ALL))
{
- if(chanId == ADC_CH_ALL)
+ if(chanId == AUDK2G_ADC_CH_ALL)
{
- retVal = pcm186xInputSel(audk2g_gAdcI2cAddr[id], (Uint8)ADC_CH1_RIGHT,
+ retVal = pcm186xInputSel(audk2g_gAdcI2cAddr[id], (Uint8)AUDK2G_ADC_CH1_RIGHT,
(Uint8)inputMux);
if(retVal)
{
return (Audk2g_EFAIL);
}
- retVal = pcm186xInputSel(audk2g_gAdcI2cAddr[id], (Uint8)ADC_CH2_RIGHT,
+ retVal = pcm186xInputSel(audk2g_gAdcI2cAddr[id], (Uint8)AUDK2G_ADC_CH2_RIGHT,
(Uint8)inputMux);
}
else
* receive PCM word length for ADC
*
* \param devId [IN] Device ID of ADC HW instance
- * Use 'ADC_DEVICE_ALL' to apply the configuration
+ * Use 'AUDK2G_ADC_DEVICE_ALL' to apply the configuration
* for all the ADC devices available.
*
* \param wLen [IN] ADC data word length
AdcRxWordLen wLen,
AdcDataFormat format)
{
- ADC_RET retVal;
+ AUDK2G_ADC_RET retVal;
Uint8 id;
IFPRINT(audk2g_write("platformAudioAdcDataConfig Called \n"));
- if( !( ((devId >= ADC_DEVICE_0) && (devId <= ADC_DEVICE_ALL)) &&
- ((wLen >= ADC_RX_WLEN_24BIT) && (wLen <= ADC_RX_WLEN_16BIT)) &&
- ((format >= ADC_DATA_FORMAT_I2S) &&
- (format <= ADC_DATA_FORMAT_TDM_DSP)) ) )
+ if( !( ((devId >= AUDK2G_ADC_DEVICE_0) && (devId <= AUDK2G_ADC_DEVICE_ALL)) &&
+ ((wLen >= AUDK2G_ADC_RX_WLEN_24BIT) && (wLen <= AUDK2G_ADC_RX_WLEN_16BIT)) &&
+ ((format >= AUDK2G_ADC_DATA_FORMAT_I2S) &&
+ (format <= AUDK2G_ADC_DATA_FORMAT_TDM_DSP)) ) )
{
IFPRINT(audk2g_write("platformAudioAdcDataConfig : Invalid Inputs\n"));
audk2g_errno = AUDK2G_ERRNO_INVALID_ARGUMENT;
return (Audk2g_EINVALID);
}
- for (id = ADC_DEVICE_0; id < ADC_DEVICE_ALL; id++)
+ for (id = AUDK2G_ADC_DEVICE_0; id < AUDK2G_ADC_DEVICE_ALL; id++)
{
- if((id == devId) || (devId == ADC_DEVICE_ALL))
+ if((id == devId) || (devId == AUDK2G_ADC_DEVICE_ALL))
{
retVal = pcm186xDataConfig(audk2g_gAdcI2cAddr[id], (Uint8)format,
(Uint8)wLen);
* This function configures mute functionality of each ADC channel
*
* \param devId [IN] Device ID of ADC HW instance
- * Use 'ADC_DEVICE_ALL' to apply the configuration
+ * Use 'AUDK2G_ADC_DEVICE_ALL' to apply the configuration
* for all the ADC devices available.
*
* \param chanId [IN] Internal ADC channel Id
- * Use ADC_CH_ALL to apply mute configuration for
+ * Use AUDK2G_ADC_CH_ALL to apply mute configuration for
* all the ADC channels
*
* \param muteEnable [IN] Flag to configure mute
AdcChanId chanId,
uint8_t muteEnable)
{
- ADC_RET retVal;
+ AUDK2G_ADC_RET retVal;
Uint8 chan;
Uint8 id;
IFPRINT(audk2g_write("platformAudioAdcMuteCtrl Called \n"));
- if( !( ((devId >= ADC_DEVICE_0) && (devId <= ADC_DEVICE_ALL)) &&
- ((chanId >= ADC_CH1_LEFT) && (chanId <= ADC_CH_ALL)) &&
+ if( !( ((devId >= AUDK2G_ADC_DEVICE_0) && (devId <= AUDK2G_ADC_DEVICE_ALL)) &&
+ ((chanId >= AUDK2G_ADC_CH1_LEFT) && (chanId <= AUDK2G_ADC_CH_ALL)) &&
((muteEnable == 0) || (muteEnable == 1)) ) )
{
IFPRINT(audk2g_write("platformAudioAdcMuteCtrl : Invalid Inputs\n"));
return (Audk2g_EINVALID);
}
- if(chanId == ADC_CH_ALL)
+ if(chanId == AUDK2G_ADC_CH_ALL)
{
chan = 0xF;
}
chan = (1 << chanId);
}
- for (id = ADC_DEVICE_0; id < ADC_DEVICE_ALL; id++)
+ for (id = AUDK2G_ADC_DEVICE_0; id < AUDK2G_ADC_DEVICE_ALL; id++)
{
- if((id == devId) || (devId == ADC_DEVICE_ALL))
+ if((id == devId) || (devId == AUDK2G_ADC_DEVICE_ALL))
{
retVal = pcm186xMuteChannel(audk2g_gAdcI2cAddr[id], chan,
(Uint8)muteEnable);
* This function enables/disables MIC bias for analog MIC input
*
* \param devId [IN] Device ID of ADC HW instance
- * Use 'ADC_DEVICE_ALL' to apply the configuration
+ * Use 'AUDK2G_ADC_DEVICE_ALL' to apply the configuration
* for all the ADC devices available.
*
* \param micBiasEnable [IN] Mic Bias enable flag
Audk2g_STATUS platformAudioAdcMicBiasCtrl(AdcDevId devId,
uint8_t micBiasEnable)
{
- ADC_RET retVal;
+ AUDK2G_ADC_RET retVal;
Uint8 id;
IFPRINT(audk2g_write("platformAudioAdcMicBiasCtrl Called \n"));
- if( !( ((devId >= ADC_DEVICE_0) && (devId <= ADC_DEVICE_ALL)) &&
+ if( !( ((devId >= AUDK2G_ADC_DEVICE_0) && (devId <= AUDK2G_ADC_DEVICE_ALL)) &&
((micBiasEnable == 0) || (micBiasEnable == 1)) ) )
{
IFPRINT(audk2g_write("platformAudioAdcMicBiasCtrl : Invalid Inputs\n"));
return (Audk2g_EINVALID);
}
- for (id = ADC_DEVICE_0; id < ADC_DEVICE_ALL; id++)
+ for (id = AUDK2G_ADC_DEVICE_0; id < AUDK2G_ADC_DEVICE_ALL; id++)
{
- if((id == devId) || (devId == ADC_DEVICE_ALL))
+ if((id == devId) || (devId == AUDK2G_ADC_DEVICE_ALL))
{
retVal = pcm186xMicBiasCtrl(audk2g_gAdcI2cAddr[id], (Uint8)micBiasEnable);
if(retVal)
* This function enables/disables different power modes supported by ADC
*
* \param devId [IN] Device ID of ADC HW instance
- * Use 'ADC_DEVICE_ALL' to apply the configuration
+ * Use 'AUDK2G_ADC_DEVICE_ALL' to apply the configuration
* for all the ADC devices available.
*
* \param powState [IN] ADC power state to configure
AdcPowerState powState,
uint8_t stateEnable)
{
- ADC_RET retVal;
+ AUDK2G_ADC_RET retVal;
Uint8 id;
IFPRINT(audk2g_write("platformAudioAdcConfigPowState Called \n"));
- if( !( ((devId >= ADC_DEVICE_0) && (devId <= ADC_DEVICE_ALL)) &&
- ((powState >= ADC_POWER_STATE_STANDBY) &&
- (powState <= ADC_POWER_STATE_POWERDOWN)) &&
+ if( !( ((devId >= AUDK2G_ADC_DEVICE_0) && (devId <= AUDK2G_ADC_DEVICE_ALL)) &&
+ ((powState >= AUDK2G_ADC_POWER_STATE_STANDBY) &&
+ (powState <= AUDK2G_ADC_POWER_STATE_POWERDOWN)) &&
((stateEnable == 0) || (stateEnable == 1)) ) )
{
IFPRINT(audk2g_write("platformAudioAdcConfigPowState : Invalid Inputs\n"));
return (Audk2g_EINVALID);
}
- for (id = ADC_DEVICE_0; id < ADC_DEVICE_ALL; id++)
+ for (id = AUDK2G_ADC_DEVICE_0; id < AUDK2G_ADC_DEVICE_ALL; id++)
{
- if((id == devId) || (devId == ADC_DEVICE_ALL))
+ if((id == devId) || (devId == AUDK2G_ADC_DEVICE_ALL))
{
retVal = pcm186xConfigPowState(audk2g_gAdcI2cAddr[id], (Uint8)powState,
(Uint8)stateEnable);
* This function enables/disables different interrupts supported by ADC
*
* \param devId [IN] Device ID of ADC HW instance
- * Use 'ADC_DEVICE_ALL' to apply the configuration
+ * Use 'AUDK2G_ADC_DEVICE_ALL' to apply the configuration
* for all the ADC devices available.
*
* \param intId [IN] Interrupt Id to configure
- * Use to 'ADC_INTR_ALL' to configure all the
+ * Use to 'AUDK2G_ADC_INTR_ALL' to configure all the
* interrupts together
*
* \param intEnable [IN] Interrupt enable flag
AdcIntr intId,
uint8_t intEnable)
{
- ADC_RET retVal;
+ AUDK2G_ADC_RET retVal;
Uint8 id;
IFPRINT(audk2g_write("platformAudioAdcConfigIntr Called \n"));
- if( !( ((devId >= ADC_DEVICE_0) && (devId <= ADC_DEVICE_ALL)) &&
- ((intId >= ADC_INTR_ENERGY_SENSE) && (intId <= ADC_INTR_ALL)) &&
+ if( !( ((devId >= AUDK2G_ADC_DEVICE_0) && (devId <= AUDK2G_ADC_DEVICE_ALL)) &&
+ ((intId >= AUDK2G_ADC_INTR_ENERGY_SENSE) && (intId <= AUDK2G_ADC_INTR_ALL)) &&
((intEnable == 0) || (intEnable == 1)) ) )
{
IFPRINT(audk2g_write("platformAudioAdcConfigIntr : Invalid Inputs\n"));
return (Audk2g_EINVALID);
}
- for (id = ADC_DEVICE_0; id < ADC_DEVICE_ALL; id++)
+ for (id = AUDK2G_ADC_DEVICE_0; id < AUDK2G_ADC_DEVICE_ALL; id++)
{
- if((id == devId) || (devId == ADC_DEVICE_ALL))
+ if((id == devId) || (devId == AUDK2G_ADC_DEVICE_ALL))
{
retVal = pcm186xSetIntr(audk2g_gAdcI2cAddr[id], (Uint8)intId,
(Uint8)intEnable);
* \param devId [IN] Device ID of ADC HW instance
*
* \param intId [IN] Interrupt Id to read the status
- * Use to 'ADC_INTR_ALL' to read status of all the
+ * Use to 'AUDK2G_ADC_INTR_ALL' to read status of all the
* interrupts together
*
* \return Interrupt status
IFPRINT(audk2g_write("platformAudioAdcGetIntrStatus Called \n"));
- if( !( ((devId >= ADC_DEVICE_0) && (devId <= ADC_DEVICE_1)) &&
- ((intId >= ADC_INTR_ENERGY_SENSE) && (intId <= ADC_INTR_ALL)) ) )
+ if( !( ((devId >= AUDK2G_ADC_DEVICE_0) && (devId <= AUDK2G_ADC_DEVICE_1)) &&
+ ((intId >= AUDK2G_ADC_INTR_ENERGY_SENSE) && (intId <= AUDK2G_ADC_INTR_ALL)) ) )
{
IFPRINT(audk2g_write("platformAudioAdcGetIntrStatus : Invalid Inputs\n"));
audk2g_errno = AUDK2G_ERRNO_INVALID_ARGUMENT;
return ((uint8_t)retVal);
}
- if(intId != ADC_INTR_ALL)
+ if(intId != AUDK2G_ADC_INTR_ALL)
{
retVal = (retVal >> intId) & 0x1;
}
IFPRINT(audk2g_write("platformAudioAdcGetStatus Called \n"));
- if( !( ((devId >= ADC_DEVICE_0) && (devId <= ADC_DEVICE_1)) &&
- ((status >= ADC_STATUS_POWER_STATE) &&
- (status <= ADC_STATUS_LDO)) ) )
+ if( !( ((devId >= AUDK2G_ADC_DEVICE_0) && (devId <= AUDK2G_ADC_DEVICE_1)) &&
+ ((status >= AUDK2G_ADC_STATUS_POWER_STATE) &&
+ (status <= AUDK2G_ADC_STATUS_LDO)) ) )
{
IFPRINT(audk2g_write("platformAudioAdcGetStatus : Invalid Inputs\n"));
audk2g_errno = AUDK2G_ERRNO_INVALID_ARGUMENT;
* 0x9 - Sleep
* 0xF - Run
*/
- case ADC_STATUS_POWER_STATE:
+ case AUDK2G_ADC_STATUS_POWER_STATE:
retVal = pcm186xGetPowerStateStatus(audk2g_gAdcI2cAddr[devId]);
break;
* 0x6 - Out of range (High)
* 0x7 - Invalid Fs
*/
- case ADC_STATUS_SAMPLING_FREQ:
+ case AUDK2G_ADC_STATUS_SAMPLING_FREQ:
retVal = pcm186xGetSampleFreqStatus(audk2g_gAdcI2cAddr[devId]);
break;
* 0x6 - Out of range (High)
* 0x7 - Invalid BCK ratio or LRCK Halt
*/
- case ADC_STATUS_BCK_RATIO:
+ case AUDK2G_ADC_STATUS_BCK_RATIO:
retVal = pcm186xGetBckRatioStatus(audk2g_gAdcI2cAddr[devId]);
break;
* 0x6 - Out of range (High)
* 0x7 - Invalid SCK ratio or LRCK Halt
*/
- case ADC_STATUS_SCK_RATIO:
+ case AUDK2G_ADC_STATUS_SCK_RATIO:
retVal = pcm186xGetSckRatioStatus(audk2g_gAdcI2cAddr[devId]);
break;
* 0 - No Error
* 1 - Halt
*/
- case ADC_STATUS_LRCK_HALT:
+ case AUDK2G_ADC_STATUS_LRCK_HALT:
retVal = pcm186xGetLrckHltStatus(audk2g_gAdcI2cAddr[devId]);
break;
* 0 - No Error
* 1 - Halt
*/
- case ADC_STATUS_BCK_HALT:
+ case AUDK2G_ADC_STATUS_BCK_HALT:
retVal = pcm186xGetBckHltStatus(audk2g_gAdcI2cAddr[devId]);
break;
* 0 - No Error
* 1 - Halt
*/
- case ADC_STATUS_SCK_HALT:
+ case AUDK2G_ADC_STATUS_SCK_HALT:
retVal = pcm186xGetSckHltStatus(audk2g_gAdcI2cAddr[devId]);
break;
* 0 - No Error
* 1 - Error
*/
- case ADC_STATUS_LRCK_ERR:
+ case AUDK2G_ADC_STATUS_LRCK_ERR:
retVal = pcm186xGetLrckErrStatus(audk2g_gAdcI2cAddr[devId]);
break;
* 0 - No Error
* 1 - Error
*/
- case ADC_STATUS_BCK_ERR:
+ case AUDK2G_ADC_STATUS_BCK_ERR:
retVal = pcm186xGetBckErrStatus(audk2g_gAdcI2cAddr[devId]);
break;
* 0 - No Error
* 1 - Error
*/
- case ADC_STATUS_SCK_ERR:
+ case AUDK2G_ADC_STATUS_SCK_ERR:
retVal = pcm186xGetSckErrStatus(audk2g_gAdcI2cAddr[devId]);
break;
* 0 - Bad/Missing
* 1 - Good
*/
- case ADC_STATUS_DVDD:
+ case AUDK2G_ADC_STATUS_DVDD:
retVal = pcm186xGetDvddStatus(audk2g_gAdcI2cAddr[devId]);
break;
* 0 - Bad/Missing
* 1 - Good
*/
- case ADC_STATUS_AVDD:
+ case AUDK2G_ADC_STATUS_AVDD:
retVal = pcm186xGetAvddStatus(audk2g_gAdcI2cAddr[devId]);
break;
* 0 - Bad/Missing
* 1 - Good
*/
- case ADC_STATUS_LDO:
+ case AUDK2G_ADC_STATUS_LDO:
retVal = pcm186xGetLdoStatus(audk2g_gAdcI2cAddr[devId]);
break;
* supported by ADC
*
* \param devId [IN] Device ID of ADC HW instance
- * Use 'ADC_DEVICE_ALL' to apply the configuration
+ * Use 'AUDK2G_ADC_DEVICE_ALL' to apply the configuration
* for all the ADC devices available.
*
* \param chanCfg [IN] DSP channel configuration
Audk2g_STATUS platformAudioAdcDspCtrl(AdcDevId devId,
AdcDspChanCfg chanCfg)
{
- ADC_RET retVal;
+ AUDK2G_ADC_RET retVal;
Uint8 id;
IFPRINT(audk2g_write("platformAudioAdcDspCtrl Called \n"));
- if( !( ((devId >= ADC_DEVICE_0) && (devId <= ADC_DEVICE_ALL)) &&
- ((chanCfg == ADC_DSP_PROC_4CHAN) ||
- (chanCfg == ADC_DSP_PROC_2CHAN)) ) )
+ if( !( ((devId >= AUDK2G_ADC_DEVICE_0) && (devId <= AUDK2G_ADC_DEVICE_ALL)) &&
+ ((chanCfg == AUDK2G_ADC_DSP_PROC_4CHAN) ||
+ (chanCfg == AUDK2G_ADC_DSP_PROC_2CHAN)) ) )
{
IFPRINT(audk2g_write("platformAudioAdcDspCtrl : Invalid Inputs\n"));
audk2g_errno = AUDK2G_ERRNO_INVALID_ARGUMENT;
return (Audk2g_EINVALID);
}
- for (id = ADC_DEVICE_0; id < ADC_DEVICE_ALL; id++)
+ for (id = AUDK2G_ADC_DEVICE_0; id < AUDK2G_ADC_DEVICE_ALL; id++)
{
- if((id == devId) || (devId == ADC_DEVICE_ALL))
+ if((id == devId) || (devId == AUDK2G_ADC_DEVICE_ALL))
{
retVal = pcm186xDspCtrl(audk2g_gAdcI2cAddr[id], (Uint8)chanCfg);
if(retVal)
* DSP coefficients can be programmed by this function.
*
* \param devId [IN] Device ID of ADC HW instance
- * Use 'ADC_DEVICE_ALL' to apply the configuration
+ * Use 'AUDK2G_ADC_DEVICE_ALL' to apply the configuration
* for all the ADC devices available.
*
* \param coeffRegAddr [IN] Address of DSP coefficient register
uint8_t coeffRegAddr,
uint32_t dspCoeff)
{
- ADC_RET retVal;
+ AUDK2G_ADC_RET retVal;
Uint8 id;
IFPRINT(audk2g_write("platformAudioAdcProgDspCoeff Called \n"));
- if(!((devId >= ADC_DEVICE_0) && (devId <= ADC_DEVICE_ALL)))
+ if(!((devId >= AUDK2G_ADC_DEVICE_0) && (devId <= AUDK2G_ADC_DEVICE_ALL)))
{
IFPRINT(audk2g_write("platformAudioAdcProgDspCoeff : Invalid Inputs\n"));
audk2g_errno = AUDK2G_ERRNO_INVALID_ARGUMENT;
return (Audk2g_EINVALID);
}
- for (id = ADC_DEVICE_0; id < ADC_DEVICE_ALL; id++)
+ for (id = AUDK2G_ADC_DEVICE_0; id < AUDK2G_ADC_DEVICE_ALL; id++)
{
- if((id == devId) || (devId == ADC_DEVICE_ALL))
+ if((id == devId) || (devId == AUDK2G_ADC_DEVICE_ALL))
{
retVal = pcm186xProgDspCoeff(audk2g_gAdcI2cAddr[id], (Uint8)coeffRegAddr,
(Uint32)dspCoeff);
* configuration for debug messages.
*
* \param devId [IN] Device ID of ADC HW instance
- * Use 'ADC_DEVICE_ALL' to read the register values
+ * Use 'AUDK2G_ADC_DEVICE_ALL' to read the register values
* for all the ADC devices available.
*
* \return Audk2g_EOK on Success or error code
*/
Audk2g_STATUS platformAudioAdcGetRegDump(AdcDevId devId)
{
- ADC_RET retVal;
+ AUDK2G_ADC_RET retVal;
Uint8 id;
IFPRINT(audk2g_write("platformAudioAdcGetRegDump Called \n"));
- if(!((devId >= ADC_DEVICE_0) && (devId <= ADC_DEVICE_ALL)))
+ if(!((devId >= AUDK2G_ADC_DEVICE_0) && (devId <= AUDK2G_ADC_DEVICE_ALL)))
{
IFPRINT(audk2g_write("platformAudioAdcGetRegDump : Invalid Inputs\n"));
audk2g_errno = AUDK2G_ERRNO_INVALID_ARGUMENT;
return (Audk2g_EINVALID);
}
- for (id = ADC_DEVICE_0; id < ADC_DEVICE_ALL; id++)
+ for (id = AUDK2G_ADC_DEVICE_0; id < AUDK2G_ADC_DEVICE_ALL; id++)
{
- if((id == devId) || (devId == ADC_DEVICE_ALL))
+ if((id == devId) || (devId == AUDK2G_ADC_DEVICE_ALL))
{
retVal = pcm186xRegDump(audk2g_gAdcI2cAddr[id]);
if(retVal)
diff --git a/src/audk2g_dc_adc.c b/src/audk2g_dc_adc.c
index 434a4bb7459ab8adccf174c8b83590fa476f5658..fe502b9086c3126cacee89edd0f72aabf737f41c 100644 (file)
--- a/src/audk2g_dc_adc.c
+++ b/src/audk2g_dc_adc.c
{0x10, 0x05}, /** GPIO0_FUNC - DOUT2, GPIO0_POL - Normal
GPIO1_FUNC - GPIO1, GPIO1_POL - Normal */
{0x20, 0x40}, /** SCK_XI_SEL : SCK or XTAL,MST_SCK_SRC : SCK or XI,
- MST_MODE : Slave,ADC_CLK_SRC : SCK,DSP2_CLK_SRC : SCK,
+ MST_MODE : Slave,AUDK2G_ADC_CLK_SRC : SCK,DSP2_CLK_SRC : SCK,
DSP1_CLK_SRC : SCK,CLKDET_EN : Enable */
{0x60, 0x00}, /** POSTPGA : Disable,CLKERR : Disable,DC_CHANG : Disable,
* \return 0 for success.
*
**/
-static ADC_RET pcm186x_read_reg(Uint8 addr, Uint8 reg, Uint8 *data)
+static AUDK2G_ADC_RET pcm186x_read_reg(Uint8 addr, Uint8 reg, Uint8 *data)
{
- ADC_RET ret;
+ AUDK2G_ADC_RET ret;
DBG_PCM186x (audk2g_write("\nEnter pcm186x_read_reg\n"));
/**
* \brief Writes into ADC register.
*
- * Note: Disable ENABLE_ADC_REG_ECHO to stop register echo by write function
+ * Note: Disable ENABLE_AUDK2G_ADC_REG_ECHO to stop register echo by write function
*
* \param addr [IN] ADC HW instance I2C slave address.
* \param reg [IN] Register to be written.
* \return 0 for success.
*
**/
-static ADC_RET pcm186x_write_reg(Uint8 addr, Uint8 reg, Uint8 data)
+static AUDK2G_ADC_RET pcm186x_write_reg(Uint8 addr, Uint8 reg, Uint8 data)
{
Uint8 slaveData[2];
- ADC_RET ret;
+ AUDK2G_ADC_RET ret;
Uint8 value;
slaveData[0] = reg;
IFPRINT (audk2g_write("\npcm186x_write_reg(): i2cWrite error : ret = %d\n", ret));
}
-#ifdef ENABLE_ADC_REG_ECHO
+#ifdef ENABLE_AUDK2G_ADC_REG_ECHO
ret = pcm186x_read_reg(addr, reg, &value);
if(ret)
{
* \return 0 if success.
*
**/
-ADC_RET pcm186xAdcInit(Uint8 addr)
+AUDK2G_ADC_RET pcm186xAdcInit(Uint8 addr)
{
- ADC_RET ret = -1;
+ AUDK2G_ADC_RET ret = -1;
Uint8 count;
DBG_PCM186x (audk2g_write("\nEnter pcm186xAdcInit\n"));
* \return 0 if success.
*
**/
-ADC_RET pcm186xRegDump(Uint8 addr)
+AUDK2G_ADC_RET pcm186xRegDump(Uint8 addr)
{
- ADC_RET ret;
+ AUDK2G_ADC_RET ret;
Uint8 count;
Uint8 read = 0;
* \return 0 if success.
*
*/
-ADC_RET pcm186xMicBiasCtrl(Uint8 addr, Uint8 power)
+AUDK2G_ADC_RET pcm186xMicBiasCtrl(Uint8 addr, Uint8 power)
{
Uint8 read = 0;
- ADC_RET ret;
+ AUDK2G_ADC_RET ret;
/* Changing to Page 3 */
ret = pcm186x_write_reg(addr, 0x0, 0x03);
* \return 0 if success.
*
**/
-ADC_RET pcm186xReset(Uint8 addr)
+AUDK2G_ADC_RET audk2g_pcm186xReset(Uint8 addr)
{
- ADC_RET ret;
+ AUDK2G_ADC_RET ret;
- DBG_PCM186x (audk2g_write("pcm186xReset() : addr = 0x%x page = %d\n",
+ DBG_PCM186x (audk2g_write("audk2g_pcm186xReset() : addr = 0x%x page = %d\n",
addr, pcm186xPageCheck(addr)));
- ret = pcm186x_write_reg(addr, PCM186x_ADC_RESET, 0xFF);
+ ret = pcm186x_write_reg(addr, AUDK2G_PCM186x_ADC_RESET, 0xFF);
return (ret);
}
* \param addr [IN] ADC HW instance I2C slave address.
*
* \param dataType [IN] Data type for the codec operation
- * ADC_DATA_FORMAT_I2S - for I2S mode
- * ADC_DATA_FORMAT_LEFTJ - for left aligned data
- * ADC_DATA_FORMAT_RIGHTJ - for right aligned data
- * ADC_DATA_FORMAT_TDM_DSP - for TDM/DSP data.
+ * AUDK2G_ADC_DATA_FORMAT_I2S - for I2S mode
+ * AUDK2G_ADC_DATA_FORMAT_LEFTJ - for left aligned data
+ * AUDK2G_ADC_DATA_FORMAT_RIGHTJ - for right aligned data
+ * AUDK2G_ADC_DATA_FORMAT_TDM_DSP - for TDM/DSP data.
*
* \param slotWidth [IN] Slot width in bits
- * ADC_RX_WLEN_24BIT - 24 bit
- * ADC_RX_WLEN_20BIT - 20 bit
- * ADC_RX_WLEN_16BIT - 16 bit
+ * AUDK2G_ADC_RX_WLEN_24BIT - 24 bit
+ * AUDK2G_ADC_RX_WLEN_20BIT - 20 bit
+ * AUDK2G_ADC_RX_WLEN_16BIT - 16 bit
*
* \return 0 if success.
*
**/
-ADC_RET pcm186xDataConfig(Uint8 addr, Uint8 dataType, Uint8 slotWidth)
+AUDK2G_ADC_RET pcm186xDataConfig(Uint8 addr, Uint8 dataType, Uint8 slotWidth)
{
Uint8 read = 0;
Uint8 val;
- ADC_RET ret;
+ AUDK2G_ADC_RET ret;
DBG_PCM186x (audk2g_write("pcm186xDataConfig() : addr = 0x%x dataType = %d "
"slotWidth = %d page = %d\n", addr, dataType,
* \return 0 for success.
*
**/
-ADC_RET pcm186xInputSel(Uint8 addr, Uint8 channel, Uint8 input)
+AUDK2G_ADC_RET pcm186xInputSel(Uint8 addr, Uint8 channel, Uint8 input)
{
- ADC_RET ret;
+ AUDK2G_ADC_RET ret;
Uint8 read = 0;
DBG_PCM186x (audk2g_write("pcm186xInputSel() : addr = 0x%x "
* \param vol [IN] Volume in percentage; 0 to 100
*
* \param channel [IN] Channel selection mask
- * ADC_CH1_LEFT - ADC CH1 LEFT
- * ADC_CH1_RIGHT - ADC CH1 RIGHT
- * ADC_CH2_LEFT - ADC CH2 LEFT
- * ADC_CH2_RIGHT - ADC CH2 RIGHT
- * ADC_CH_ALL - All the four channels
+ * AUDK2G_ADC_CH1_LEFT - ADC CH1 LEFT
+ * AUDK2G_ADC_CH1_RIGHT - ADC CH1 RIGHT
+ * AUDK2G_ADC_CH2_LEFT - ADC CH2 LEFT
+ * AUDK2G_ADC_CH2_RIGHT - ADC CH2 RIGHT
+ * AUDK2G_ADC_CH_ALL - All the four channels
*
* \return 0 for success.
*
**/
-ADC_RET pcm186xSetVolume(Uint8 addr, Uint8 vol, Uint8 channel)
+AUDK2G_ADC_RET pcm186xSetVolume(Uint8 addr, Uint8 vol, Uint8 channel)
{
Uint8 value;
Uint8 count;
- ADC_RET ret;
+ AUDK2G_ADC_RET ret;
DBG_PCM186x (audk2g_write("pcm186xSetVolume() : addr = 0x%x vol = %d "
"channel = %d page = %d\n", addr,
value = value | 0x1;
}
- if(channel == ADC_CH_ALL)
+ if(channel == AUDK2G_ADC_CH_ALL)
{
- for (count = ADC_CH1_LEFT; count <= ADC_CH2_RIGHT; count++)
+ for (count = AUDK2G_ADC_CH1_LEFT; count <= AUDK2G_ADC_CH2_RIGHT; count++)
{
ret = pcm186x_write_reg(addr, PCM186x_VOL_CTRL(count), value);
if(ret)
* \return 0 for success.
*
**/
-ADC_RET pcm186xMuteChannel(Uint8 addr, Uint8 channel, Uint8 mute)
+AUDK2G_ADC_RET pcm186xMuteChannel(Uint8 addr, Uint8 channel, Uint8 mute)
{
- ADC_RET ret;
+ AUDK2G_ADC_RET ret;
Uint8 read = 0;
DBG_PCM186x (audk2g_write("pcm186xMuteChannel() : addr = 0x%x mute = %d"
* \param addr [IN] ADC HW instance I2C slave address.
*
* \param powState [IN] ADC power state
- * ADC_POWER_STATE_STANDBY - ADC standby state
- * ADC_POWER_STATE_SLEEP - ADC device sleep state
- * ADC_POWER_STATE_POWERDOWN - ADC Analog Power Down state
+ * AUDK2G_ADC_POWER_STATE_STANDBY - ADC standby state
+ * AUDK2G_ADC_POWER_STATE_SLEEP - ADC device sleep state
+ * AUDK2G_ADC_POWER_STATE_POWERDOWN - ADC Analog Power Down state
*
* \param enable [IN] Mute control
* 1 - Enables the power state
* \return 0 for success.
*
**/
-ADC_RET pcm186xConfigPowState(Uint8 addr, Uint8 powState, Uint8 enable)
+AUDK2G_ADC_RET pcm186xConfigPowState(Uint8 addr, Uint8 powState, Uint8 enable)
{
- ADC_RET ret;
+ AUDK2G_ADC_RET ret;
Uint8 read = 0;
DBG_PCM186x (audk2g_write("pcm186xConfigPowState() : addr = 0x%x"
* \param addr [IN] ADC HW instance I2C slave address.
*
* \param intrNum [IN] ADC interrupt ID
- * ADC_INTR_ENERGY_SENSE - Energysense Interrupt
- * ADC_INTR_DIN_TOGGLE - I2S RX DIN toggle Interrupt
- * ADC_INTR_DC_CHANGE - DC Level Change Interrupt
- * ADC_INTR_CLK_ERR - Clock Error Interrupt
- * ADC_INTR_POST_PGA_CLIP - Post-PGA Clipping Interrupt
- * ADC_INTR_ALL - To controls all the ADC interrupts together
+ * AUDK2G_ADC_INTR_ENERGY_SENSE - Energysense Interrupt
+ * AUDK2G_ADC_INTR_DIN_TOGGLE - I2S RX DIN toggle Interrupt
+ * AUDK2G_ADC_INTR_DC_CHANGE - DC Level Change Interrupt
+ * AUDK2G_ADC_INTR_CLK_ERR - Clock Error Interrupt
+ * AUDK2G_ADC_INTR_POST_PGA_CLIP - Post-PGA Clipping Interrupt
+ * AUDK2G_ADC_INTR_ALL - To controls all the ADC interrupts together
*
* \param enable [IN] Interrupt control
* 1 - Enables the interrupt
* \return 0 for success.
*
**/
-ADC_RET pcm186xSetIntr(Uint8 addr, Uint8 intrNum, Uint8 enable)
+AUDK2G_ADC_RET pcm186xSetIntr(Uint8 addr, Uint8 intrNum, Uint8 enable)
{
- ADC_RET ret;
+ AUDK2G_ADC_RET ret;
Uint8 value;
Uint8 read = 0;
return (ret);
}
- if(intrNum == ADC_INTR_ALL)
+ if(intrNum == AUDK2G_ADC_INTR_ALL)
{
if(enable)
{
**/
Uint8 pcm186xGetIntrStatus(Uint8 addr)
{
- ADC_RET ret;
+ AUDK2G_ADC_RET ret;
Uint8 read = 0;
DBG_PCM186x (audk2g_write("pcm186xGetIntrStatus() : addr = 0x%x page"
* \param addr [IN] ADC HW instance I2C slave address.
*
* \param channel [IN] Channel configuration
- * ADC_DSP_PROC_4CHAN - ADC DSP 4 channel mode processing
- * ADC_DSP_PROC_2CHAN - ADC DSP 2 channel mode processing
+ * AUDK2G_ADC_DSP_PROC_4CHAN - ADC DSP 4 channel mode processing
+ * AUDK2G_ADC_DSP_PROC_2CHAN - ADC DSP 2 channel mode processing
*
* \return 0 for success.
*
**/
-ADC_RET pcm186xDspCtrl(Uint8 addr, Uint8 channel)
+AUDK2G_ADC_RET pcm186xDspCtrl(Uint8 addr, Uint8 channel)
{
- ADC_RET ret;
+ AUDK2G_ADC_RET ret;
Uint8 read;
DBG_PCM186x (audk2g_write("pcm186xDspCtrl() : addr = 0x%x channel = %d"
* \return 0 for success.
*
**/
-ADC_RET pcm186xProgDspCoeff(Uint8 addr, Uint8 regAddr, Uint32 coeff)
+AUDK2G_ADC_RET pcm186xProgDspCoeff(Uint8 addr, Uint8 regAddr, Uint32 coeff)
{
- ADC_RET ret;
+ AUDK2G_ADC_RET ret;
Uint8 value;
Uint8 count;
Uint8 coeffBuf[3];
**/
Uint8 pcm186xGetPowerStateStatus(Uint8 addr)
{
- ADC_RET ret;
+ AUDK2G_ADC_RET ret;
Uint8 read = 0;
DBG_PCM186x (audk2g_write("pcm186xGetPowerStateStatus() : addr = 0x%x"
**/
Uint8 pcm186xGetSampleFreqStatus(Uint8 addr)
{
- ADC_RET ret;
+ AUDK2G_ADC_RET ret;
Uint8 read = 0;
DBG_PCM186x (audk2g_write("pcm186xGetSampleFreqStatus() : addr = 0x%x"
**/
Uint8 pcm186xGetBckRatioStatus(Uint8 addr)
{
- ADC_RET ret;
+ AUDK2G_ADC_RET ret;
Uint8 read = 0;
DBG_PCM186x (audk2g_write("pcm186xGetBckRatioStatus() : addr = 0x%x"
**/
Uint8 pcm186xGetSckRatioStatus(Uint8 addr)
{
- ADC_RET ret;
+ AUDK2G_ADC_RET ret;
Uint8 read = 0;
DBG_PCM186x (audk2g_write("pcm186xGetSckRatioStatus() : addr = 0x%x"
**/
Uint8 pcm186xGetLrckHltStatus(Uint8 addr)
{
- ADC_RET ret;
+ AUDK2G_ADC_RET ret;
Uint8 read = 0;
DBG_PCM186x (audk2g_write("pcm186xGetLrckHltStatus() : addr = 0x%x"
**/
Uint8 pcm186xGetBckHltStatus(Uint8 addr)
{
- ADC_RET ret;
+ AUDK2G_ADC_RET ret;
Uint8 read = 0;
DBG_PCM186x (audk2g_write("pcm186xGetBckHltStatus() : addr = 0x%x"
**/
Uint8 pcm186xGetSckHltStatus(Uint8 addr)
{
- ADC_RET ret;
+ AUDK2G_ADC_RET ret;
Uint8 read = 0;
DBG_PCM186x (audk2g_write("pcm186xGetSckHltStatus() : addr = 0x%x"
**/
Uint8 pcm186xGetLrckErrStatus(Uint8 addr)
{
- ADC_RET ret;
+ AUDK2G_ADC_RET ret;
Uint8 read = 0;
DBG_PCM186x (audk2g_write("pcm186xGetLrckErrStatus() : addr = 0x%x"
**/
Uint8 pcm186xGetBckErrStatus(Uint8 addr)
{
- ADC_RET ret;
+ AUDK2G_ADC_RET ret;
Uint8 read = 0;
DBG_PCM186x (audk2g_write("pcm186xGetBckErrStatus() : addr = 0x%x"
**/
Uint8 pcm186xGetSckErrStatus(Uint8 addr)
{
- ADC_RET ret;
+ AUDK2G_ADC_RET ret;
Uint8 read = 0;
DBG_PCM186x (audk2g_write("pcm186xGetSckErrStatus() : addr = 0x%x"
**/
Uint8 pcm186xGetDvddStatus(Uint8 addr)
{
- ADC_RET ret;
+ AUDK2G_ADC_RET ret;
Uint8 read = 0;
DBG_PCM186x (audk2g_write("pcm186xGetDvddStatus() : addr = 0x%x"
**/
Uint8 pcm186xGetAvddStatus(Uint8 addr)
{
- ADC_RET ret;
+ AUDK2G_ADC_RET ret;
Uint8 read = 0;
DBG_PCM186x (audk2g_write("pcm186xGetAvddStatus() : addr = 0x%x"
**/
Uint8 pcm186xGetLdoStatus(Uint8 addr)
{
- ADC_RET ret;
+ AUDK2G_ADC_RET ret;
Uint8 read = 0;
DBG_PCM186x (audk2g_write("pcm186xGetLdoStatus() : addr = 0x%x"