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raw | patch | inline | side by side (parent: 5df9232)
raw | patch | inline | side by side (parent: 5df9232)
author | Jan Kiszka <jan.kiszka@siemens.com> | |
Wed, 28 Feb 2018 07:39:23 +0000 (08:39 +0100) | ||
committer | Jan Kiszka <jan.kiszka@siemens.com> | |
Wed, 28 Feb 2018 07:39:23 +0000 (08:39 +0100) |
It's called ISS according to the ARM manual, not ICC.
No functional changes.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
No functional changes.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
hypervisor/arch/arm/include/asm/sysregs.h | patch | blob | history | |
hypervisor/arch/arm/mmio.c | patch | blob | history | |
hypervisor/arch/arm/traps.c | patch | blob | history |
index 797585b499a665811903371feef1c058231a3ba3..afcb45ecf1c782d968377f2d81e602d1d6f60444 100644 (file)
#define HSR_IL_SHIFT 25
#define HSR_IL(hsr) ((hsr) >> HSR_IL_SHIFT & 0x1)
/* Instruction specific */
-#define HSR_ICC_MASK 0x1ffffff
-#define HSR_ICC(hsr) ((hsr) & HSR_ICC_MASK)
+#define HSR_ISS_MASK 0x1ffffff
+#define HSR_ISS(hsr) ((hsr) & HSR_ISS_MASK)
/* Exception classes values */
#define HSR_EC_UNK 0x00
#define HSR_EC_WFI 0x01
#define HSR_EC_DABT 0x24
#define HSR_EC_DABT_HYP 0x25
/* Condition code */
-#define HSR_ICC_CV_BIT (1 << 24)
-#define HSR_ICC_COND(icc) ((icc) >> 20 & 0xf)
+#define HSR_ISS_CV_BIT (1 << 24)
+#define HSR_ISS_COND(iss) ((iss) >> 20 & 0xf)
#define HSR_MATCH_MCR_MRC(hsr, crn, opc1, crm, opc2) \
(((hsr) & (BIT_MASK(19, 10) | BIT_MASK(4, 1))) == \
index b3f7669603381aa3a2c9c593fc64ae96696cbd1e..25e4b52a21ec8120918db4cb0d171dfe79d9fbd8 100644 (file)
unsigned long hpfar;
unsigned long hdfar;
/* Decode the syndrome fields */
- u32 icc = HSR_ICC(ctx->hsr);
- u32 isv = icc >> 24;
- u32 sas = icc >> 22 & 0x3;
- u32 sse = icc >> 21 & 0x1;
- u32 srt = icc >> 16 & 0xf;
- u32 ea = icc >> 9 & 0x1;
- u32 cm = icc >> 8 & 0x1;
- u32 s1ptw = icc >> 7 & 0x1;
- u32 is_write = icc >> 6 & 0x1;
+ u32 iss = HSR_ISS(ctx->hsr);
+ u32 isv = iss >> 24;
+ u32 sas = iss >> 22 & 0x3;
+ u32 sse = iss >> 21 & 0x1;
+ u32 srt = iss >> 16 & 0xf;
+ u32 ea = iss >> 9 & 0x1;
+ u32 cm = iss >> 8 & 0x1;
+ u32 s1ptw = iss >> 7 & 0x1;
+ u32 is_write = iss >> 6 & 0x1;
u32 size = 1 << sas;
arm_read_sysreg(HPFAR, hpfar);
index cf27ec098e0cd7f8419e94ffcb4e67bdb568c0ae..f75a3b0041264456a57e6dbf163a35ef13f03ea7 100644 (file)
static bool arch_failed_condition(struct trap_context *ctx)
{
u32 class = HSR_EC(ctx->hsr);
- u32 icc = HSR_ICC(ctx->hsr);
+ u32 iss = HSR_ISS(ctx->hsr);
u32 cpsr, flags, cond;
arm_read_banked_reg(SPSR_hyp, cpsr);
return false;
/* Is condition field valid? */
- if (icc & HSR_ICC_CV_BIT) {
- cond = HSR_ICC_COND(icc);
+ if (iss & HSR_ISS_CV_BIT) {
+ cond = HSR_ISS_COND(iss);
} else {
/* This can happen in Thumb mode: examine IT state. */
unsigned long it = PSR_IT(cpsr);