7e775f61472a8f395c94dabd2dc4f2d67e60eca5
2 /*
3 * Copyright (c) 2014, Mentor Graphics Corporation
4 * All rights reserved.
5 *
6 * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright notice,
12 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright notice,
14 * this list of conditions and the following disclaimer in the documentation
15 * and/or other materials provided with the distribution.
16 * 3. Neither the name of the <ORGANIZATION> nor the names of its contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32 #include <string.h>
33 #include "xparameters.h"
34 #include "xil_exception.h"
35 #include "xscugic.h"
36 #include "xil_cache.h"
37 #include "metal/sys.h"
39 #define INTC_DEVICE_ID XPAR_SCUGIC_0_DEVICE_ID
40 /** IPI IRQ ID */
41 #define IPI_IRQ_VECT_ID 65
43 XScuGic InterruptController;
45 extern void metal_irq_isr(unsigned int irq);
46 extern int platform_register_metal_device(void);
48 int zynqmp_r5_gic_initialize()
49 {
50 u32 Status;
52 Xil_ExceptionDisable();
54 XScuGic_Config *IntcConfig; /* The configuration parameters of the interrupt controller */
56 /*
57 * Initialize the interrupt controller driver
58 */
59 IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
60 if (NULL == IntcConfig) {
61 return XST_FAILURE;
62 }
64 Status = XScuGic_CfgInitialize(&InterruptController, IntcConfig,
65 IntcConfig->CpuBaseAddress);
66 if (Status != XST_SUCCESS) {
67 return XST_FAILURE;
68 }
70 /*
71 * Register the interrupt handler to the hardware interrupt handling
72 * logic in the ARM processor.
73 */
74 Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
75 (Xil_ExceptionHandler)XScuGic_InterruptHandler,
76 &InterruptController);
78 Xil_ExceptionEnable();
79 /* Connect Interrupt ID with ISR */
80 XScuGic_Connect(&InterruptController, IPI_IRQ_VECT_ID,
81 (Xil_ExceptionHandler)metal_irq_isr,
82 (void *)IPI_IRQ_VECT_ID);
84 return 0;
85 }
87 void init_system()
88 {
89 struct metal_init_params metal_param = METAL_INIT_DEFAULTS;
91 metal_init(&metal_param);
92 zynqmp_r5_gic_initialize();
93 platform_register_metal_device();
94 }
96 void cleanup_system()
97 {
98 metal_finish();
99 Xil_DCacheDisable();
100 Xil_ICacheDisable();
101 Xil_DCacheInvalidate();
102 Xil_ICacheInvalidate();
103 }