1 /*
2 * Copyright (c) 2014, Mentor Graphics Corporation
3 * All rights reserved.
4 *
5 * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright notice,
13 * this list of conditions and the following disclaimer in the documentation
14 * and/or other materials provided with the distribution.
15 * 3. Neither the name of the <ORGANIZATION> nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
32 #include "xparameters.h"
33 #include "xil_exception.h"
34 #include "xscugic.h"
35 #include "xil_cache.h"
36 #include "metal/sys.h"
37 #include "metal/irq.h"
38 #include "platform_info.h"
40 #define INTC_DEVICE_ID XPAR_SCUGIC_0_DEVICE_ID
42 static XScuGic xInterruptController;
44 /* Interrupt Controller setup */
45 static int app_gic_initialize(void)
46 {
47 u32 Status;
48 XScuGic_Config *IntcConfig; /* The configuration parameters of the interrupt controller */
50 Xil_ExceptionDisable();
52 /*
53 * Initialize the interrupt controller driver
54 */
55 IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
56 if (NULL == IntcConfig) {
57 return XST_FAILURE;
58 }
60 Status = XScuGic_CfgInitialize(&xInterruptController, IntcConfig,
61 IntcConfig->CpuBaseAddress);
62 if (Status != XST_SUCCESS) {
63 return XST_FAILURE;
64 }
66 /*
67 * Register the interrupt handler to the hardware interrupt handling
68 * logic in the ARM processor.
69 */
70 Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
71 (Xil_ExceptionHandler)XScuGic_InterruptHandler,
72 &xInterruptController);
74 Xil_ExceptionEnable();
76 /* Connect Interrupt ID with ISR */
77 XScuGic_Connect(&xInterruptController, IPI_IRQ_VECT_ID,
78 (Xil_ExceptionHandler)metal_irq_isr,
79 (void *)IPI_IRQ_VECT_ID);
81 return 0;
82 }
84 /* Main hw machinery initialization entry point, called from main()*/
85 /* return 0 on success */
86 int init_system(void)
87 {
88 struct metal_init_params metal_param = METAL_INIT_DEFAULTS;
90 /* Low level abstraction layer for openamp initialization */
91 metal_init(&metal_param);
93 /* configure the global interrupt controller */
94 app_gic_initialize();
96 return 0;
97 }
99 void cleanup_system()
100 {
101 metal_finish();
103 Xil_DCacheDisable();
104 Xil_ICacheDisable();
105 Xil_DCacheInvalidate();
106 Xil_ICacheInvalidate();
107 }