2 /*
3 * Copyright (c) 2014, Mentor Graphics Corporation
4 * All rights reserved.
5 *
6 * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright notice,
12 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright notice,
14 * this list of conditions and the following disclaimer in the documentation
15 * and/or other materials provided with the distribution.
16 * 3. Neither the name of the <ORGANIZATION> nor the names of its contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32 #include <string.h>
33 #include "xparameters.h"
34 #include "xil_exception.h"
35 #include "xscugic.h"
36 #include "xil_cache.h"
37 #include "metal/sys.h"
39 #define INTC_DEVICE_ID XPAR_SCUGIC_0_DEVICE_ID
41 XScuGic InterruptController;
43 extern void bm_env_isr(int vector);
44 extern int platform_register_metal_device(void);
46 void zynqmp_r5_irq_isr()
47 {
49 unsigned int raw_irq;
50 int irq_vector;
51 raw_irq =
52 (unsigned int)XScuGic_CPUReadReg(&InterruptController,
53 XSCUGIC_INT_ACK_OFFSET);
54 irq_vector = (int)(raw_irq & XSCUGIC_ACK_INTID_MASK);
56 bm_env_isr(irq_vector);
58 XScuGic_CPUWriteReg(&InterruptController, XSCUGIC_EOI_OFFSET, raw_irq);
59 }
61 int zynqmp_r5_gic_initialize()
62 {
63 u32 Status;
65 Xil_ExceptionDisable();
67 XScuGic_Config *IntcConfig; /* The configuration parameters of the interrupt controller */
69 /*
70 * Initialize the interrupt controller driver
71 */
72 IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
73 if (NULL == IntcConfig) {
74 return XST_FAILURE;
75 }
77 Status = XScuGic_CfgInitialize(&InterruptController, IntcConfig,
78 IntcConfig->CpuBaseAddress);
79 if (Status != XST_SUCCESS) {
80 return XST_FAILURE;
81 }
83 /*
84 * Register the interrupt handler to the hardware interrupt handling
85 * logic in the ARM processor.
86 */
87 Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
88 (Xil_ExceptionHandler) zynqmp_r5_irq_isr,
89 &InterruptController);
91 Xil_ExceptionEnable();
93 return 0;
94 }
96 void init_system()
97 {
98 struct metal_init_params metal_param = METAL_INIT_DEFAULTS;
100 metal_init(&metal_param);
101 zynqmp_r5_gic_initialize();
102 platform_register_metal_device();
103 }
105 void cleanup_system()
106 {
107 metal_finish();
108 Xil_DCacheDisable();
109 Xil_ICacheDisable();
110 Xil_DCacheInvalidate();
111 Xil_ICacheInvalidate();
112 }