[processor-sdk/open-amp.git] / include / openamp / porting / system / generic / machine / zynqmp_r5 / machine.h
1 /*
2 * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright notice,
8 * this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright notice,
10 * this list of conditions and the following disclaimer in the documentation
11 * and/or other materials provided with the distribution.
12 * 3. Neither the name of the <ORGANIZATION> nor the names of its contributors
13 * may be used to endorse or promote products derived from this software
14 * without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
29 #ifndef _BAREMETAL_H
30 #define _BAREMETAL_H
32 #include "xil_types.h"
33 #include "xparameters.h"
34 #include "xil_cache.h"
35 #include "xreg_cortexr5.h"
37 #define INTC_DEVICE_ID XPAR_SCUGIC_0_DEVICE_ID
39 /* IPI REGs OFFSET */
40 #define IPI_TRIG_OFFSET 0x00000000 /* IPI trigger register offset */
41 #define IPI_OBS_OFFSET 0x00000004 /* IPI observation register offset */
42 #define IPI_ISR_OFFSET 0x00000010 /* IPI interrupt status register offset */
43 #define IPI_IMR_OFFSET 0x00000014 /* IPI interrupt mask register offset */
44 #define IPI_IER_OFFSET 0x00000018 /* IPI interrupt enable register offset */
45 #define IPI_IDR_OFFSET 0x0000001C /* IPI interrupt disable register offset */
47 #define platform_dcache_all_flush() { Xil_DCacheFlush(); }
49 #define platform_dcache_flush_range(addr, len) { Xil_DCacheFlushRange(addr, len); }
51 #define CORTEXR5_CPSR_INTERRUPTS_BITS (XREG_CPSR_IRQ_ENABLE | XREG_CPSR_FIQ_ENABLE)
53 /* This macro writes the current program status register (CPSR - all fields) */
54 #define ARM_AR_CPSR_CXSF_WRITE(cpsr_cxsf_value) \
55 { \
56 asm volatile(" MSR CPSR_cxsf, %0" \
57 : /* No outputs */ \
58 : "r" (cpsr_cxsf_value) ); \
59 }
61 /* This macro sets the interrupt related bits in the status register / control
62 register to the specified value. */
63 #define ARM_AR_INT_BITS_SET(set_bits) \
64 { \
65 int tmp_val; \
66 tmp_val = mfcpsr(); \
67 tmp_val &= ~((unsigned int)CORTEXR5_CPSR_INTERRUPTS_BITS); \
68 tmp_val |= set_bits; \
69 ARM_AR_CPSR_CXSF_WRITE(tmp_val); \
70 }
72 /* This macro gets the interrupt related bits from the status register / control
73 register. */
74 #define ARM_AR_INT_BITS_GET(get_bits_ptr) \
75 { \
76 int tmp_val; \
77 tmp_val = mfcpsr(); \
78 tmp_val &= CORTEXR5_CPSR_INTERRUPTS_BITS; \
79 *get_bits_ptr = tmp_val; \
80 }
82 /* Memory barrier */
83 #if (defined(__CC_ARM))
84 #define MEM_BARRIER() __schedule_barrier()
85 #elif (defined(__GNUC__))
86 #define MEM_BARRIER() asm volatile("dsb" : : : "memory")
87 #else
88 #define MEM_BARRIER()
89 #endif
91 static inline unsigned int xchg(void* plock, unsigned int lockVal)
92 {
93 volatile unsigned int tmpVal = 0;
94 volatile unsigned int tmpVal1 = 0;
96 #ifdef __GNUC__
98 asm (
99 "1: \n\t"
100 "LDREX %[tmpVal], [%[plock]] \n\t"
101 "STREX %[tmpVal1], %[lockVal], [%[plock]] \n\t"
102 "CMP %[tmpVal1], #0 \n\t"
103 "BNE 1b \n\t"
104 "DMB \n\t"
105 : [tmpVal] "=&r"(tmpVal)
106 : [tmpVal1] "r" (tmpVal1), [lockVal] "r"(lockVal), [plock] "r"(plock)
107 : "cc", "memory"
108 );
110 #endif
112 return tmpVal;
113 }
115 void zynqMP_r5_map_mem_region(u32 addr, u32 size, u32 attrib);
117 int zynqMP_r5_gic_initialize();
118 void zynqMP_r5_irq_isr();
120 void restore_global_interrupts();
121 void disable_global_interrupts();
122 int platform_interrupt_enable(unsigned int vector, unsigned int polarity,
123 unsigned int priority);
124 int platform_interrupt_disable(unsigned int vector);
125 void platform_cache_all_flush_invalidate();
126 void platform_cache_disable();
127 void platform_map_mem_region(unsigned int va, unsigned int pa,
128 unsigned int size, unsigned int flags);
129 unsigned long platform_vatopa(void *addr);
130 void *platform_patova(unsigned long addr);
132 #endif /* _BAREMETAL_H */