[processor-sdk/open-amp.git] / libs / system / zynqmp_r5 / generic / xil_standalone_lib / xparameters_ps.h
1 /******************************************************************************
2 *
3 * Copyright (C) 2014 Xilinx, Inc. All rights reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
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29 * this Software without prior written authorization from Xilinx.
30 *
31 ******************************************************************************/
32 /*****************************************************************************/
33 /**
34 * @file xparameters_ps.h
35 *
36 * This file contains the address definitions for the hard peripherals
37 * attached to the ARM Cortex R5 core.
38 *
39 * <pre>
40 * MODIFICATION HISTORY:
41 *
42 * Ver Who Date Changes
43 * ----- ------- -------- ---------------------------------------------------
44 * 5.00 pkp 02/29/14 Initial version
45 * </pre>
46 *
47 * @note
48 *
49 * None.
50 *
51 ******************************************************************************/
53 #ifndef XPARAMETERS_PS_H_
54 #define XPARAMETERS_PS_H_
56 #ifdef __cplusplus
57 extern "C" {
58 #endif
60 /************************** Constant Definitions *****************************/
62 /*
63 * This block contains constant declarations for the peripherals
64 * within the hardblock
65 */
67 /* Canonical definitions for DDR MEMORY */
68 #define XPAR_DDR_MEM_BASEADDR 0x00000000U
69 #define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU
71 /* Canonical definitions for Interrupts */
72 #define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID
73 #define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID
74 #define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID
75 #define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID
76 #define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID
77 #define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID
78 #define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID
79 #define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID
80 #define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID
81 #define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID
82 #define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
83 #define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID
84 #define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
85 #define XPAR_XEMACPS_2_INTR XPS_GEM2_INT_ID
86 #define XPAR_XEMACPS_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID
87 #define XPAR_XEMACPS_3_INTR XPS_GEM3_INT_ID
88 #define XPAR_XEMACPS_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID
89 #define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
90 #define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
91 #define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
92 #define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID
93 #define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
94 #define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID
95 #define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID
96 #define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
97 #define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
98 #define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
99 #define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID
100 #define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID
101 #define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID
102 #define XPAR_XTTCPS_6_INTR XPS_TTC2_0_INT_ID
103 #define XPAR_XTTCPS_7_INTR XPS_TTC2_1_INT_ID
104 #define XPAR_XTTCPS_8_INTR XPS_TTC2_2_INT_ID
105 #define XPAR_XTTCPS_9_INTR XPS_TTC3_0_INT_ID
106 #define XPAR_XTTCPS_10_INTR XPS_TTC3_1_INT_ID
107 #define XPAR_XTTCPS_11_INTR XPS_TTC3_2_INT_ID
108 #define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID
109 #define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID
110 #define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID
111 #define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID
112 #define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID
113 #define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID
114 #define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID
115 #define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID
116 #define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID
117 #define XPAR_XNANDPS8_0_INTR XPS_NAND_INT_ID
118 #define XPAR_XADMAPS_0_INTR XPS_ADMA_CH0_INT_ID
119 #define XPAR_XADMAPS_1_INTR XPS_ADMA_CH1_INT_ID
120 #define XPAR_XADMAPS_2_INTR XPS_ADMA_CH2_INT_ID
121 #define XPAR_XADMAPS_3_INTR XPS_ADMA_CH3_INT_ID
122 #define XPAR_XADMAPS_4_INTR XPS_ADMA_CH4_INT_ID
123 #define XPAR_XADMAPS_5_INTR XPS_ADMA_CH5_INT_ID
124 #define XPAR_XADMAPS_6_INTR XPS_ADMA_CH6_INT_ID
125 #define XPAR_XADMAPS_7_INTR XPS_ADMA_CH7_INT_ID
126 #define XPAR_XCSUDMA_INTR XPS_CSU_DMA_INT_ID
127 #define XPAR_XMPU_LPD_INTR XPS_XMPU_LPD_INT_ID
128 #define XPAR_XZDMAPS_0_INTR XPS_ZDMA_CH0_INT_ID
129 #define XPAR_XZDMAPS_1_INTR XPS_ZDMA_CH1_INT_ID
130 #define XPAR_XZDMAPS_2_INTR XPS_ZDMA_CH2_INT_ID
131 #define XPAR_XZDMAPS_3_INTR XPS_ZDMA_CH3_INT_ID
132 #define XPAR_XZDMAPS_4_INTR XPS_ZDMA_CH4_INT_ID
133 #define XPAR_XZDMAPS_5_INTR XPS_ZDMA_CH5_INT_ID
134 #define XPAR_XZDMAPS_6_INTR XPS_ZDMA_CH6_INT_ID
135 #define XPAR_XZDMAPS_7_INTR XPS_ZDMA_CH7_INT_ID
136 #define XPAR_XMPU_FPD_INTR XPS_XMPU_FPD_INT_ID
137 #define XPAR_XCCI_FPD_INTR XPS_FPD_CCI_INT_ID
138 #define XPAR_XSMMU_FPD_INTR XPS_FPD_SMMU_INT_ID
139 #define XPAR_XUSBPS_0_INTR XPS_USB3_0_ENDPT_INT_ID
140 #define XPAR_XUSBPS_1_INTR XPS_USB3_1_ENDPT_INT_ID
142 /* Canonical definitions for SCU GIC */
143 #define XPAR_SCUGIC_NUM_INSTANCES 1U
144 #define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U
145 #define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U)
146 #define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00002000U)
147 #define XPAR_SCUGIC_ACK_BEFORE 0U
149 #define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ
152 /*
153 * This block contains constant declarations for the peripherals
154 * within the hardblock. These have been put for bacwards compatibilty
155 */
157 #define XPS_SYS_CTRL_BASEADDR 0xFF180000U
158 #define XPS_SCU_PERIPH_BASE 0xF9000000U
161 /* Shared Peripheral Interrupts (SPI) */
163 /* FIXME */
164 /*#define XPS_FPGA0_INT_ID 100U */
165 #define XPS_FPGA1_INT_ID 62U
166 #define XPS_FPGA2_INT_ID 63U
167 #define XPS_FPGA3_INT_ID 64U
168 #define XPS_FPGA4_INT_ID 65U
169 #define XPS_FPGA5_INT_ID 66U
170 #define XPS_FPGA6_INT_ID 67U
171 #define XPS_FPGA7_INT_ID 68U
172 #define XPS_DMA4_INT_ID 72U
173 #define XPS_DMA5_INT_ID 73U
174 #define XPS_DMA6_INT_ID 74U
175 #define XPS_DMA7_INT_ID 75U
176 #define XPS_FPGA8_INT_ID 84U
177 #define XPS_FPGA9_INT_ID 85U
178 #define XPS_FPGA10_INT_ID 86U
179 #define XPS_FPGA11_INT_ID 87U
180 #define XPS_FPGA12_INT_ID 88U
181 #define XPS_FPGA13_INT_ID 89U
182 #define XPS_FPGA14_INT_ID 90U
183 #define XPS_FPGA15_INT_ID 91U
185 /* Updated Interrupt-IDs */
186 #define XPS_OCMINTR_INT_ID (10U + 32U)
187 #define XPS_NAND_INT_ID (14U + 32U)
188 #define XPS_QSPI_INT_ID (15U + 32U)
189 #define XPS_GPIO_INT_ID (16U + 32U)
190 #define XPS_I2C0_INT_ID (17U + 32U)
191 #define XPS_I2C1_INT_ID (18U + 32U)
192 #define XPS_SPI0_INT_ID (19U + 32U)
193 #define XPS_SPI1_INT_ID (20U + 32U)
194 #define XPS_UART0_INT_ID (21U + 32U)
195 #define XPS_UART1_INT_ID (22U + 32U)
196 #define XPS_CAN0_INT_ID (23U + 32U)
197 #define XPS_CAN1_INT_ID (24U + 32U)
198 #define XPS_WDT_INT_ID (52U + 32U)
199 #define XPS_TTC0_0_INT_ID (36U + 32U)
200 #define XPS_TTC0_1_INT_ID (37U + 32U)
201 #define XPS_TTC0_2_INT_ID (38U + 32U)
202 #define XPS_TTC1_0_INT_ID (39U + 32U)
203 #define XPS_TTC1_1_INT_ID (40U + 32U)
204 #define XPS_TTC1_2_INT_ID (41U + 32U)
205 #define XPS_TTC2_0_INT_ID (42U + 32U)
206 #define XPS_TTC2_1_INT_ID (43U + 32U)
207 #define XPS_TTC2_2_INT_ID (44U + 32U)
208 #define XPS_TTC3_0_INT_ID (45U + 32U)
209 #define XPS_TTC3_1_INT_ID (46U + 32U)
210 #define XPS_TTC3_2_INT_ID (47U + 32U)
211 #define XPS_SDIO0_INT_ID (48U + 32U)
212 #define XPS_SDIO1_INT_ID (49U + 32U)
213 #define XPS_GEM0_INT_ID (57U + 32U)
214 #define XPS_GEM0_WAKE_INT_ID (58U + 32U)
215 #define XPS_GEM1_INT_ID (59U + 32U)
216 #define XPS_GEM1_WAKE_INT_ID (60U + 32U)
217 #define XPS_GEM2_INT_ID (61U + 32U)
218 #define XPS_GEM2_WAKE_INT_ID (62U + 32U)
219 #define XPS_GEM3_INT_ID (63U + 32U)
220 #define XPS_GEM3_WAKE_INT_ID (64U + 32U)
221 #define XPS_USB3_0_ENDPT_INT_ID (65U + 32U)
222 #define XPS_USB3_1_ENDPT_INT_ID (70U + 32U)
223 #define XPS_ADMA_CH0_INT_ID (77U + 32U)
224 #define XPS_ADMA_CH1_INT_ID (78U + 32U)
225 #define XPS_ADMA_CH2_INT_ID (79U + 32U)
226 #define XPS_ADMA_CH3_INT_ID (80U + 32U)
227 #define XPS_ADMA_CH4_INT_ID (81U + 32U)
228 #define XPS_ADMA_CH5_INT_ID (82U + 32U)
229 #define XPS_ADMA_CH6_INT_ID (83U + 32U)
230 #define XPS_ADMA_CH7_INT_ID (84U + 32U)
231 #define XPS_CSU_DMA_INT_ID (86U + 32U)
232 #define XPS_XMPU_LPD_INT_ID (88U + 32U)
233 #define XPS_ZDMA_CH0_INT_ID (124U + 32U)
234 #define XPS_ZDMA_CH1_INT_ID (125U + 32U)
235 #define XPS_ZDMA_CH2_INT_ID (126U + 32U)
236 #define XPS_ZDMA_CH3_INT_ID (127U + 32U)
237 #define XPS_ZDMA_CH4_INT_ID (128U + 32U)
238 #define XPS_ZDMA_CH5_INT_ID (129U + 32U)
239 #define XPS_ZDMA_CH6_INT_ID (130U + 32U)
240 #define XPS_ZDMA_CH7_INT_ID (131U + 32U)
241 #define XPS_XMPU_FPD_INT_ID (134U + 32U)
242 #define XPS_FPD_CCI_INT_ID (154U + 32U)
243 #define XPS_FPD_SMMU_INT_ID (155U + 32U)
245 /* Private Peripheral Interrupts (PPI) */
246 /*#define XPS_GLOBAL_TMR_INT_ID 27 SCU Global Timer interrupt */
247 /*#define XPS_FIQ_INT_ID 28 FIQ from FPGA fabric */
248 /*#define XPS_SCU_TMR_INT_ID 29 SCU Private Timer interrupt */
249 /*#define XPS_SCU_WDT_INT_ID 30 SCU Private WDT interrupt */
250 /*#define XPS_IRQ_INT_ID 31 IRQ from FPGA fabric */
252 /* REDEFINES for TEST APP */
253 /* Definitions for UART */
254 #define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID
255 #define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID
256 #define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID
257 #define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID
258 #define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID
259 #define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID
260 #define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID
261 #define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID
262 #define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID
263 #define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID
264 #define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID
265 #define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID
266 #define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
267 #define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID
268 #define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
269 #define XPAR_PS7_ETHERNET_2_INTR XPS_GEM2_INT_ID
270 #define XPAR_PS7_ETHERNET_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID
271 #define XPAR_PS7_ETHERNET_3_INTR XPS_GEM3_INT_ID
272 #define XPAR_PS7_ETHERNET_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID
274 #define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID
275 #define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID
276 #define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID
277 #define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
278 #define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID
280 #define XPAR_XADCPS_NUM_INSTANCES 1U
281 #define XPAR_XADCPS_0_DEVICE_ID 0U
282 #define XPAR_XADCPS_0_BASEADDR (0xF8007000U)
283 #define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
285 /* For backwards compatibilty */
286 #define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
287 #define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
288 #define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
289 #define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
290 #define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
291 #define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
292 #define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
293 #define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
294 #define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
295 #define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
297 #define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
299 #ifdef XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ
300 #define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ
301 #endif
303 #ifdef XPAR_CPU_CORTEXR5_1_CPU_CLK_FREQ_HZ
304 #define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXR5_1_CPU_CLK_FREQ_HZ
305 #endif
307 #define XPAR_SCUTIMER_DEVICE_ID 0U
308 #define XPAR_SCUWDT_DEVICE_ID 0U
311 #ifdef __cplusplus
312 }
313 #endif
315 #endif /* protection macro */