[processor-sdk/open-amp.git] / obsolete / system / generic / machine / zynqmp_r5 / xil_standalone_lib / boot.S
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32 /*****************************************************************************/
33 /**
34 * @file boot.S
35 *
36 * This file contains the initial startup code for the Cortex R5 processor
37 *
38 * <pre>
39 * MODIFICATION HISTORY:
40 *
41 * Ver Who Date Changes
42 * ----- ---- -------- ---------------------------------------------------
43 * 5.00 pkp 02/10/14 Initial version
44 * </pre>
45 *
46 * @note
47 *
48 * None.
49 *
50 ******************************************************************************/
52 #include "xparameters.h"
55 .global _prestart
56 .global _boot
57 .global __stack
58 .global __irq_stack
59 .global __supervisor_stack
60 .global __abort_stack
61 .global __fiq_stack
62 .global __undef_stack
63 .global _vector_table
66 /* Stack Pointer locations for boot code */
67 .set Undef_stack, __undef_stack
68 .set FIQ_stack, __fiq_stack
69 .set Abort_stack, __abort_stack
70 .set SPV_stack, __supervisor_stack
71 .set IRQ_stack, __irq_stack
72 .set SYS_stack, __stack
74 .set vector_base, _vector_table
76 .section .boot,"axS"
79 /* this initializes the various processor modes */
81 _prestart:
82 _boot:
86 OKToRun:
88 /* Initialize processor registers to 0 */
89 mov r0,#0
90 mov r1,#0
91 mov r2,#0
92 mov r3,#0
93 mov r4,#0
94 mov r5,#0
95 mov r6,#0
96 mov r7,#0
97 mov r8,#0
98 mov r9,#0
99 mov r10,#0
100 mov r11,#0
101 mov r12,#0
103 /* Disable MPU and caches */
104 mrc p15, 0, r0, c1, c0, 0 /* Read CP15 Control Register*/
105 bic r0, r0, #0x05 /* Disable MPU (M bit) and data cache (C bit) */
106 bic r0, r0, #0x1000 /* Disable instruction cache (I bit) */
107 dsb /* Ensure all previous loads/stores have completed */
108 mcr p15, 0, r0, c1, c0, 0 /* Write CP15 Control Register */
109 isb /* Ensure subsequent insts execute wrt new MPU settings */
111 /* Disable Branch prediction */
112 mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR */
113 orr r0, r0, #(0x1 << 17) /* Enable RSDIS bit 17 to disable the return stack */
114 orr r0, r0, #(0x1 << 16) /* Clear BP bit 15 and set BP bit 16:*/
115 bic r0, r0, #(0x1 << 15) /* Branch always not taken and history table updates disabled*/
116 mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/
117 dsb /* Complete all outstanding explicit memory operations*/
119 /* Invalidate caches */
120 mov r0,#0 /* r0 = 0 */
121 dsb
122 mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
123 mcr p15, 0, r0, c15, c5, 0 /* Invalidate entire data cache*/
124 isb
126 /* Initialize stack pointer for various mode */
127 mrs r0, cpsr /* get the current PSR */
128 mvn r1, #0x1f /* set up the irq stack pointer */
129 and r2, r1, r0
130 orr r2, r2, #0x12 /* IRQ mode */
131 msr cpsr, r2
132 ldr r13,=IRQ_stack /* IRQ stack pointer */
134 mrs r0, cpsr /* get the current PSR */
135 mvn r1, #0x1f /* set up the supervisor stack pointer */
136 and r2, r1, r0
137 orr r2, r2, #0x13 /* supervisor mode */
138 msr cpsr, r2
139 ldr r13,=SPV_stack /* Supervisor stack pointer */
141 mrs r0, cpsr /* get the current PSR */
142 mvn r1, #0x1f /* set up the Abort stack pointer */
143 and r2, r1, r0
144 orr r2, r2, #0x17 /* Abort mode */
145 msr cpsr, r2
146 ldr r13,=Abort_stack /* Abort stack pointer */
148 mrs r0, cpsr /* get the current PSR */
149 mvn r1, #0x1f /* set up the FIQ stack pointer */
150 and r2, r1, r0
151 orr r2, r2, #0x11 /* FIQ mode */
152 msr cpsr, r2
153 ldr r13,=FIQ_stack /* FIQ stack pointer */
155 mrs r0, cpsr /* get the current PSR */
156 mvn r1, #0x1f /* set up the Undefine stack pointer */
157 and r2, r1, r0
158 orr r2, r2, #0x1b /* Undefine mode */
159 msr cpsr, r2
160 ldr r13,=Undef_stack /* Undefine stack pointer */
162 mrs r0, cpsr /* get the current PSR */
163 mvn r1, #0x1f /* set up the system stack pointer */
164 and r2, r1, r0
165 orr r2, r2, #0x1F /* SYS mode */
166 msr cpsr, r2
167 ldr r13,=SYS_stack /* SYS stack pointer */
169 bl Init_MPU /* Initialize MPU */
171 /* Enable Branch prediction */
172 mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/
173 bic r0, r0, #(0x1 << 17) /* Clear RSDIS bit 17 to enable return stack*/
174 bic r0, r0, #(0x1 << 16) /* Clear BP bit 15 and BP bit 16:*/
175 bic r0, r0, #(0x1 << 15) /* Normal operation, BP is taken from the global history table.*/
176 mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/
178 /* Enable icahce and dcache */
179 mrc p15,0,r1,c1,c0,0
180 ldr r0, =0x1005
181 orr r1,r1,r0
182 dsb
183 mcr p15,0,r1,c1,c0,0 /* Enable cache */
184 isb /* isb flush prefetch buffer */
186 /*
187 * Currently OpenAMP is supported only with HIVEC
188 * exception vectors are set to LOVEC if BSP is not built
189 * for OpenAMP as the default state is HIVEC
190 */
192 #if USEAMP != 1
193 /*set exception vector to LOVEC */
194 mrc p15, 0, r0, c1, c0, 0
195 mvn r1, #0x2000
196 and r0, r0, r1
197 mcr p15, 0, r0, c1, c0, 0
198 #endif
199 b _startup /* jump to C startup code */
202 .Ldone: b .Ldone /* Paranoia: we should never get here */
205 .end