1 /******************************************************************************
2 *
3 * Copyright (C) 2014 Xilinx, Inc. All rights reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
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12 * The above copyright notice and this permission notice shall be included in
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15 * Use of the Software is limited solely to applications:
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29 * this Software without prior written authorization from Xilinx.
30 *
31 ******************************************************************************/
32 /*****************************************************************************/
33 /**
34 * @file mpu.c
35 *
36 * This file contains initial configuration of the MPU.
37 *
38 * <pre>
39 * MODIFICATION HISTORY:
40 *
41 * Ver Who Date Changes
42 * ----- ---- -------- ---------------------------------------------------
43 * 5.00 pkp 02/20/14 First release
44 * </pre>
45 *
46 * @note
47 *
48 * None.
49 *
50 ******************************************************************************/
51 /***************************** Include Files *********************************/
53 #include "xil_types.h"
54 #include "xreg_cortexr5.h"
55 #include "xil_mpu.h"
56 #include "xpseudo_asm.h"
58 /***************** Macros (Inline Functions) Definitions *********************/
60 /**************************** Type Definitions *******************************/
62 /************************** Constant Definitions *****************************/
64 /************************** Variable Definitions *****************************/
66 /************************** Function Prototypes ******************************/
67 void Init_MPU(void);
68 static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib);
69 static void Xil_DisableMPURegions(void);
71 /*****************************************************************************
72 *
73 * Initialize MPU for a given address map and Enabled the background Region in
74 * MPU with default memory attributes for rest of address range for Cortex R5
75 * processor.
76 *
77 * @param None.
78 *
79 * @return None.
80 *
81 *
82 ******************************************************************************/
84 void Init_MPU(void)
85 {
86 u32 Addr;
87 u32 RegSize;
88 u32 Attrib;
89 u32 RegNum = 0;
91 Xil_DisableMPURegions();
93 Addr = 0x00000000U;
94 RegSize = REGION_2G;
95 Attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW;
96 Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
97 RegNum++;
99 Addr = 0xC0000000U;
100 RegSize = REGION_512M;
101 Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
102 Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
103 RegNum++;
105 Addr = 0xF0000000U;
106 RegSize = REGION_128M;
107 Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
108 Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
109 RegNum++;
111 Addr = 0xF8000000U;
112 RegSize = REGION_64M;
113 Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
114 Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
115 RegNum++;
117 Addr = 0xFC000000U;
118 RegSize = REGION_32M;
119 Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
120 Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
121 RegNum++;
123 Addr = 0xFE000000U;
124 RegSize = REGION_16M;
125 Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
126 Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
127 RegNum++;
129 Addr = 0xFF000000U;
130 RegSize = REGION_16M;
131 Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
132 Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
133 RegNum++;
135 Addr = 0xFFFC0000U;
136 RegSize = REGION_256K;
137 Attrib = NORM_NSHARED_WB_WA| PRIV_RW_USER_RW ;
138 Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
140 }
142 /*****************************************************************************
143 *
144 * Set the memory attributes for a section of memory with starting address addr
145 * of the region size defined by reg_size having attributes attrib of region number
146 * reg_num
147 *
148 * @param addr is the address for which attributes are to be set.
149 * @param attrib specifies the attributes for that memory region.
150 * @param reg_size specifies the size for that memory region.
151 * @param reg_num specifies the number for that memory region.
152 * @return None.
153 *
154 *
155 ******************************************************************************/
156 static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib)
157 {
158 u32 Local_reg_size = reg_size;
160 Local_reg_size = Local_reg_size<<1U;
161 Local_reg_size |= REGION_EN;
162 dsb();
163 mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num);
164 isb();
165 mtcp(XREG_CP15_MPU_REG_BASEADDR,addr); /* Set base address of a region */
166 mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL,attrib); /* Set the control attribute */
167 mtcp(XREG_CP15_MPU_REG_SIZE_EN,Local_reg_size); /* set the region size and enable it*/
168 dsb();
169 isb(); /* synchronize context on this processor */
170 }
173 /*****************************************************************************
174 *
175 * Disable all the MPU regions if any of them is enabled
176 *
177 * @param None.
178 *
179 * @return None.
180 *
181 *
182 ******************************************************************************/
183 static void Xil_DisableMPURegions(void)
184 {
185 u32 Temp;
186 u32 Index;
187 for (Index = 0; Index <= 15; Index++) {
188 mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,Index);
189 Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN);
190 Temp &= (~REGION_EN);
191 dsb();
192 mtcp(XREG_CP15_MPU_REG_SIZE_EN,Temp);
193 dsb();
194 isb();
195 }
197 }