[processor-sdk/open-amp.git] / obsolete / system / zynqmp_r5 / generic / xil_standalone_lib / xscugic_hw.h
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31 ******************************************************************************/
32 /*****************************************************************************/
33 /**
34 *
35 * @file xscugic_hw.h
36 *
37 * This header file contains identifiers and HW access functions (or
38 * macros) that can be used to access the device. The user should refer to the
39 * hardware device specification for more details of the device operation.
40 * The driver functions/APIs are defined in xscugic.h.
41 *
42 * This GIC device has two parts, a distributor and CPU interface(s). Each part
43 * has separate register definition sections.
44 *
45 *
46 * <pre>
47 * MODIFICATION HISTORY:
48 *
49 * Ver Who Date Changes
50 * ----- ---- -------- -----------------------------------------------------
51 * 1.00a drg 01/19/10 First release
52 * 1.01a sdm 11/09/11 "xil_exception.h" added as include.
53 * Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
54 * added to enable or disable interrupts based on
55 * Distributor Register base address. Normally users use
56 * XScuGic instance and call XScuGic_Enable or
57 * XScuGic_Disable to enable/disable interrupts. These
58 * new macros are provided when user does not want to
59 * use an instance pointer but still wants to enable or
60 * disable interrupts.
61 * Function prototypes for functions (present in newly
62 * added file xscugic_hw.c) are added.
63 * 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR
64 * 702687).
65 * 1.04a hk 05/04/13 Fix for CR#705621. Moved function prototypes
66 * XScuGic_SetPriTrigTypeByDistAddr and
67 * XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
68 * 3.0 pkp 12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
69 * Zynq Ultrascale Mp
70 * 3.0 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
71 * </pre>
72 *
73 ******************************************************************************/
75 #ifndef XSCUGIC_HW_H /* prevent circular inclusions */
76 #define XSCUGIC_HW_H /* by using protection macros */
78 #ifdef __cplusplus
79 extern "C" {
80 #endif
82 /***************************** Include Files *********************************/
84 #include "xil_types.h"
85 #include "xil_assert.h"
86 #include "xil_io.h"
87 #include "xil_exception.h"
89 /************************** Constant Definitions *****************************/
91 /*
92 * The maximum number of interrupts supported by the hardware.
93 */
94 #ifdef __ARM_NEON__
95 #define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /* Maximum number of interrupt defined by Zynq */
96 #else
97 #define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */
98 #endif
100 /*
101 * The maximum priority value that can be used in the GIC.
102 */
103 #define XSCUGIC_MAX_INTR_PRIO_VAL 248U
104 #define XSCUGIC_INTR_PRIO_MASK 0x000000F8U
106 /** @name Distributor Interface Register Map
107 *
108 * Define the offsets from the base address for all Distributor registers of
109 * the interrupt controller, some registers may be reserved in the hardware
110 * device.
111 * @{
112 */
113 #define XSCUGIC_DIST_EN_OFFSET 0x00000000U /**< Distributor Enable
114 Register */
115 #define XSCUGIC_IC_TYPE_OFFSET 0x00000004U /**< Interrupt Controller
116 Type Register */
117 #define XSCUGIC_DIST_IDENT_OFFSET 0x00000008U /**< Implementor ID
118 Register */
119 #define XSCUGIC_SECURITY_OFFSET 0x00000080U /**< Interrupt Security
120 Register */
121 #define XSCUGIC_ENABLE_SET_OFFSET 0x00000100U /**< Enable Set
122 Register */
123 #define XSCUGIC_DISABLE_OFFSET 0x00000180U /**< Enable Clear Register */
124 #define XSCUGIC_PENDING_SET_OFFSET 0x00000200U /**< Pending Set
125 Register */
126 #define XSCUGIC_PENDING_CLR_OFFSET 0x00000280U /**< Pending Clear
127 Register */
128 #define XSCUGIC_ACTIVE_OFFSET 0x00000300U /**< Active Status Register */
129 #define XSCUGIC_PRIORITY_OFFSET 0x00000400U /**< Priority Level Register */
130 #define XSCUGIC_SPI_TARGET_OFFSET 0x00000800U /**< SPI Target
131 Register 0x800-0x8FB */
132 #define XSCUGIC_INT_CFG_OFFSET 0x00000C00U /**< Interrupt Configuration
133 Register 0xC00-0xCFC */
134 #define XSCUGIC_PPI_STAT_OFFSET 0x00000D00U /**< PPI Status Register */
135 #define XSCUGIC_SPI_STAT_OFFSET 0x00000D04U /**< SPI Status Register
136 0xd04-0xd7C */
137 #define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80U /**< AHB Configuration
138 Register */
139 #define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00U /**< Software Triggered
140 Interrupt Register */
141 #define XSCUGIC_PERPHID_OFFSET 0x00000FD0U /**< Peripheral ID Reg */
142 #define XSCUGIC_PCELLID_OFFSET 0x00000FF0U /**< Pcell ID Register */
143 /* @} */
145 /** @name Distributor Enable Register
146 * Controls if the distributor response to external interrupt inputs.
147 * @{
148 */
149 #define XSCUGIC_EN_INT_MASK 0x00000001U /**< Interrupt In Enable */
150 /* @} */
152 /** @name Interrupt Controller Type Register
153 * @{
154 */
155 #define XSCUGIC_LSPI_MASK 0x0000F800U /**< Number of Lockable
156 Shared Peripheral
157 Interrupts*/
158 #define XSCUGIC_DOMAIN_MASK 0x00000400U /**< Number os Security domains*/
159 #define XSCUGIC_CPU_NUM_MASK 0x000000E0U /**< Number of CPU Interfaces */
160 #define XSCUGIC_NUM_INT_MASK 0x0000001FU /**< Number of Interrupt IDs */
161 /* @} */
163 /** @name Implementor ID Register
164 * Implementor and revision information.
165 * @{
166 */
167 #define XSCUGIC_REV_MASK 0x00FFF000U /**< Revision Number */
168 #define XSCUGIC_IMPL_MASK 0x00000FFFU /**< Implementor */
169 /* @} */
171 /** @name Interrupt Security Registers
172 * Each bit controls the security level of an interrupt, either secure or non
173 * secure. These registers can only be accessed using secure read and write.
174 * There are registers for each of the CPU interfaces at offset 0x080. A
175 * register set for the SPI interrupts is available to all CPU interfaces.
176 * There are up to 32 of these registers staring at location 0x084.
177 * @{
178 */
179 #define XSCUGIC_INT_NS_MASK 0x00000001U /**< Each bit corresponds to an
180 INT_ID */
181 /* @} */
183 /** @name Enable Set Register
184 * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
185 * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
186 * bit to 0.
187 * There are registers for each of the CPU interfaces at offset 0x100. With up
188 * to 8 registers aliased to the same address. A register set for the SPI
189 * interrupts is available to all CPU interfaces.
190 * There are up to 32 of these registers staring at location 0x104.
191 * @{
192 */
193 #define XSCUGIC_INT_EN_MASK 0x00000001U /**< Each bit corresponds to an
194 INT_ID */
195 /* @} */
197 /** @name Enable Clear Register
198 * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
199 * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
200 * sets the corresponding bit to 0.
201 * There are registers for each of the CPU interfaces at offset 0x180. With up
202 * to 8 registers aliased to the same address.
203 * A register set for the SPI interrupts is available to all CPU interfaces.
204 * There are up to 32 of these registers staring at location 0x184.
205 * @{
206 */
207 #define XSCUGIC_INT_CLR_MASK 0x00000001U /**< Each bit corresponds to an
208 INT_ID */
209 /* @} */
211 /** @name Pending Set Register
212 * Each bit controls the Pending or Active and Pending state of an interrupt, a
213 * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
214 * an interrupt to the pending state.
215 * There are registers for each of the CPU interfaces at offset 0x200. With up
216 * to 8 registers aliased to the same address.
217 * A register set for the SPI interrupts is available to all CPU interfaces.
218 * There are up to 32 of these registers staring at location 0x204.
219 * @{
220 */
221 #define XSCUGIC_PEND_SET_MASK 0x00000001U /**< Each bit corresponds to an
222 INT_ID */
223 /* @} */
225 /** @name Pending Clear Register
226 * Each bit can clear the Pending or Active and Pending state of an interrupt, a
227 * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
228 * clears the pending state of an interrupt.
229 * There are registers for each of the CPU interfaces at offset 0x280. With up
230 * to 8 registers aliased to the same address.
231 * A register set for the SPI interrupts is available to all CPU interfaces.
232 * There are up to 32 of these registers staring at location 0x284.
233 * @{
234 */
235 #define XSCUGIC_PEND_CLR_MASK 0x00000001U /**< Each bit corresponds to an
236 INT_ID */
237 /* @} */
239 /** @name Active Status Register
240 * Each bit provides the Active status of an interrupt, a
241 * 0 is not Active, a 1 is Active. This is a read only register.
242 * There are registers for each of the CPU interfaces at offset 0x300. With up
243 * to 8 registers aliased to each address.
244 * A register set for the SPI interrupts is available to all CPU interfaces.
245 * There are up to 32 of these registers staring at location 0x380.
246 * @{
247 */
248 #define XSCUGIC_ACTIVE_MASK 0x00000001U /**< Each bit corresponds to an
249 INT_ID */
250 /* @} */
252 /** @name Priority Level Register
253 * Each byte in a Priority Level Register sets the priority level of an
254 * interrupt. Reading the register provides the priority level of an interrupt.
255 * There are registers for each of the CPU interfaces at offset 0x400 through
256 * 0x41C. With up to 8 registers aliased to each address.
257 * 0 is highest priority, 0xFF is lowest.
258 * A register set for the SPI interrupts is available to all CPU interfaces.
259 * There are up to 255 of these registers staring at location 0x420.
260 * @{
261 */
262 #define XSCUGIC_PRIORITY_MASK 0x000000FFU /**< Each Byte corresponds to an
263 INT_ID */
264 #define XSCUGIC_PRIORITY_MAX 0x000000FFU /**< Highest value of a priority
265 actually the lowest priority*/
266 /* @} */
268 /** @name SPI Target Register 0x800-0x8FB
269 * Each byte references a separate SPI and programs which of the up to 8 CPU
270 * interfaces are sent a Pending interrupt.
271 * There are registers for each of the CPU interfaces at offset 0x800 through
272 * 0x81C. With up to 8 registers aliased to each address.
273 * A register set for the SPI interrupts is available to all CPU interfaces.
274 * There are up to 255 of these registers staring at location 0x820.
275 *
276 * This driver does not support multiple CPU interfaces. These are included
277 * for complete documentation.
278 * @{
279 */
280 #define XSCUGIC_SPI_CPU7_MASK 0x00000080U /**< CPU 7 Mask*/
281 #define XSCUGIC_SPI_CPU6_MASK 0x00000040U /**< CPU 6 Mask*/
282 #define XSCUGIC_SPI_CPU5_MASK 0x00000020U /**< CPU 5 Mask*/
283 #define XSCUGIC_SPI_CPU4_MASK 0x00000010U /**< CPU 4 Mask*/
284 #define XSCUGIC_SPI_CPU3_MASK 0x00000008U /**< CPU 3 Mask*/
285 #define XSCUGIC_SPI_CPU2_MASK 0x00000003U /**< CPU 2 Mask*/
286 #define XSCUGIC_SPI_CPU1_MASK 0x00000002U /**< CPU 1 Mask*/
287 #define XSCUGIC_SPI_CPU0_MASK 0x00000001U /**< CPU 0 Mask*/
288 /* @} */
290 /** @name Interrupt Configuration Register 0xC00-0xCFC
291 * The interrupt configuration registers program an SFI to be active HIGH level
292 * sensitive or rising edge sensitive.
293 * Each bit pair describes the configuration for an INT_ID.
294 * SFI Read Only b10 always
295 * PPI Read Only depending on how the PPIs are configured.
296 * b01 Active HIGH level sensitive
297 * b11 Rising edge sensitive
298 * SPI LSB is read only.
299 * b01 Active HIGH level sensitive
300 * b11 Rising edge sensitive/
301 * There are registers for each of the CPU interfaces at offset 0xC00 through
302 * 0xC04. With up to 8 registers aliased to each address.
303 * A register set for the SPI interrupts is available to all CPU interfaces.
304 * There are up to 255 of these registers staring at location 0xC08.
305 * @{
306 */
307 #define XSCUGIC_INT_CFG_MASK 0x00000003U /**< */
308 /* @} */
310 /** @name PPI Status Register
311 * Enables an external AMBA master to access the status of the PPI inputs.
312 * A CPU can only read the status of its local PPI signals and cannot read the
313 * status for other CPUs.
314 * This register is aliased for each CPU interface.
315 * @{
316 */
317 #define XSCUGIC_PPI_C15_MASK 0x00008000U /**< PPI Status */
318 #define XSCUGIC_PPI_C14_MASK 0x00004000U /**< PPI Status */
319 #define XSCUGIC_PPI_C13_MASK 0x00002000U /**< PPI Status */
320 #define XSCUGIC_PPI_C12_MASK 0x00001000U /**< PPI Status */
321 #define XSCUGIC_PPI_C11_MASK 0x00000800U /**< PPI Status */
322 #define XSCUGIC_PPI_C10_MASK 0x00000400U /**< PPI Status */
323 #define XSCUGIC_PPI_C09_MASK 0x00000200U /**< PPI Status */
324 #define XSCUGIC_PPI_C08_MASK 0x00000100U /**< PPI Status */
325 #define XSCUGIC_PPI_C07_MASK 0x00000080U /**< PPI Status */
326 #define XSCUGIC_PPI_C06_MASK 0x00000040U /**< PPI Status */
327 #define XSCUGIC_PPI_C05_MASK 0x00000020U /**< PPI Status */
328 #define XSCUGIC_PPI_C04_MASK 0x00000010U /**< PPI Status */
329 #define XSCUGIC_PPI_C03_MASK 0x00000008U /**< PPI Status */
330 #define XSCUGIC_PPI_C02_MASK 0x00000004U /**< PPI Status */
331 #define XSCUGIC_PPI_C01_MASK 0x00000002U /**< PPI Status */
332 #define XSCUGIC_PPI_C00_MASK 0x00000001U /**< PPI Status */
333 /* @} */
335 /** @name SPI Status Register 0xd04-0xd7C
336 * Enables an external AMBA master to access the status of the SPI inputs.
337 * There are up to 63 registers if the maximum number of SPI inputs are
338 * configured.
339 * @{
340 */
341 #define XSCUGIC_SPI_N_MASK 0x00000001U /**< Each bit corresponds to an SPI
342 input */
343 /* @} */
345 /** @name AHB Configuration Register
346 * Provides the status of the CFGBIGEND input signal and allows the endianess
347 * of the GIC to be set.
348 * @{
349 */
350 #define XSCUGIC_AHB_END_MASK 0x00000004U /**< 0-GIC uses little Endian,
351 1-GIC uses Big Endian */
352 #define XSCUGIC_AHB_ENDOVR_MASK 0x00000002U /**< 0-Uses CFGBIGEND control,
353 1-use the AHB_END bit */
354 #define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001U /**< State of CFGBIGEND */
356 /* @} */
358 /** @name Software Triggered Interrupt Register
359 * Controls issueing of software interrupts.
360 * @{
361 */
362 #define XSCUGIC_SFI_SELFTRIG_MASK 0x02010000U
363 #define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000U /**< Target List filter
364 b00-Use the target List
365 b01-All CPUs except requester
366 b10-To Requester
367 b11-reserved */
368 #define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000U /**< CPU Target list */
369 #define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000U /**< 0= Use a secure interrupt */
370 #define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000FU /**< Set to the INTID
371 signaled to the CPU*/
372 /* @} */
374 /** @name CPU Interface Register Map
375 *
376 * Define the offsets from the base address for all CPU registers of the
377 * interrupt controller, some registers may be reserved in the hardware device.
378 * @{
379 */
380 #define XSCUGIC_CONTROL_OFFSET 0x00000000U /**< CPU Interface Control
381 Register */
382 #define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004U /**< Priority Mask Reg */
383 #define XSCUGIC_BIN_PT_OFFSET 0x00000008U /**< Binary Point Register */
384 #define XSCUGIC_INT_ACK_OFFSET 0x0000000CU /**< Interrupt ACK Reg */
385 #define XSCUGIC_EOI_OFFSET 0x00000010U /**< End of Interrupt Reg */
386 #define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014U /**< Running Priority Reg */
387 #define XSCUGIC_HI_PEND_OFFSET 0x00000018U /**< Highest Pending Interrupt
388 Register */
389 #define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001CU /**< Aliased non-Secure
390 Binary Point Register */
392 /**< 0x00000020 to 0x00000FBC are reserved and should not be read or written
393 * to. */
394 /* @} */
397 /** @name Control Register
398 * CPU Interface Control register definitions
399 * All bits are defined here although some are not available in the non-secure
400 * mode.
401 * @{
402 */
403 #define XSCUGIC_CNTR_SBPR_MASK 0x00000010U /**< Secure Binary Pointer,
404 0=separate registers,
405 1=both use bin_pt_s */
406 #define XSCUGIC_CNTR_FIQEN_MASK 0x00000008U /**< Use nFIQ_C for secure
407 interrupts,
408 0= use IRQ for both,
409 1=Use FIQ for secure, IRQ for non*/
410 #define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004U /**< Ack control for secure or non secure */
411 #define XSCUGIC_CNTR_EN_NS_MASK 0x00000002U /**< Non Secure enable */
412 #define XSCUGIC_CNTR_EN_S_MASK 0x00000001U /**< Secure enable, 0=Disabled, 1=Enabled */
413 /* @} */
415 /** @name Priority Mask Register
416 * Priority Mask register definitions
417 * The CPU interface does not send interrupt if the level of the interrupt is
418 * lower than the level of the register.
419 * @{
420 */
421 /*#define XSCUGIC_PRIORITY_MASK 0x000000FFU*/ /**< All interrupts */
422 /* @} */
424 /** @name Binary Point Register
425 * Binary Point register definitions
426 * @{
427 */
429 #define XSCUGIC_BIN_PT_MASK 0x00000007U /**< Binary point mask value
430 Value Secure Non-secure
431 b000 0xFE 0xFF
432 b001 0xFC 0xFE
433 b010 0xF8 0xFC
434 b011 0xF0 0xF8
435 b100 0xE0 0xF0
436 b101 0xC0 0xE0
437 b110 0x80 0xC0
438 b111 0x00 0x80
439 */
440 /*@}*/
442 /** @name Interrupt Acknowledge Register
443 * Interrupt Acknowledge register definitions
444 * Identifies the current Pending interrupt, and the CPU ID for software
445 * interrupts.
446 */
447 #define XSCUGIC_ACK_INTID_MASK 0x000003FFU /**< Interrupt ID */
448 #define XSCUGIC_CPUID_MASK 0x00000C00U /**< CPU ID */
449 /* @} */
451 /** @name End of Interrupt Register
452 * End of Interrupt register definitions
453 * Allows the CPU to signal the GIC when it completes an interrupt service
454 * routine.
455 */
456 #define XSCUGIC_EOI_INTID_MASK 0x000003FFU /**< Interrupt ID */
458 /* @} */
460 /** @name Running Priority Register
461 * Running Priority register definitions
462 * Identifies the interrupt priority level of the highest priority active
463 * interrupt.
464 */
465 #define XSCUGIC_RUN_PRIORITY_MASK 0x000000FFU /**< Interrupt Priority */
466 /* @} */
468 /*
469 * Highest Pending Interrupt register definitions
470 * Identifies the interrupt priority of the highest priority pending interupt
471 */
472 #define XSCUGIC_PEND_INTID_MASK 0x000003FFU /**< Pending Interrupt ID */
473 /*#define XSCUGIC_CPUID_MASK 0x00000C00U */ /**< CPU ID */
474 /* @} */
476 /***************** Macros (Inline Functions) Definitions *********************/
478 /****************************************************************************/
479 /**
480 *
481 * Read the Interrupt Configuration Register offset for an interrupt id.
482 *
483 * @param InterruptID is the interrupt number.
484 *
485 * @return The 32-bit value of the offset
486 *
487 * @note
488 *
489 *****************************************************************************/
490 #define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
491 ((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U))
493 /****************************************************************************/
494 /**
495 *
496 * Read the Interrupt Priority Register offset for an interrupt id.
497 *
498 * @param InterruptID is the interrupt number.
499 *
500 * @return The 32-bit value of the offset
501 *
502 * @note
503 *
504 *****************************************************************************/
505 #define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
506 ((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U))
508 /****************************************************************************/
509 /**
510 *
511 * Read the SPI Target Register offset for an interrupt id.
512 *
513 * @param InterruptID is the interrupt number.
514 *
515 * @return The 32-bit value of the offset
516 *
517 * @note
518 *
519 *****************************************************************************/
520 #define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
521 ((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U))
523 /****************************************************************************/
524 /**
525 *
526 * Read the Interrupt Clear-Enable Register offset for an interrupt ID
527 *
528 * @param Register is the register offset for the clear/enable bank.
529 * @param InterruptID is the interrupt number.
530 *
531 * @return The 32-bit value of the offset
532 *
533 * @note
534 *
535 *****************************************************************************/
536 #define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \
537 ((Register) + (((InterruptID)/32U) * 4U))
539 /****************************************************************************/
540 /**
541 *
542 * Read the given Intc register.
543 *
544 * @param BaseAddress is the base address of the device.
545 * @param RegOffset is the register offset to be read
546 *
547 * @return The 32-bit value of the register
548 *
549 * @note
550 * C-style signature:
551 * u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
552 *
553 *****************************************************************************/
554 #define XScuGic_ReadReg(BaseAddress, RegOffset) \
555 (Xil_In32((BaseAddress) + (RegOffset)))
558 /****************************************************************************/
559 /**
560 *
561 * Write the given Intc register.
562 *
563 * @param BaseAddress is the base address of the device.
564 * @param RegOffset is the register offset to be written
565 * @param Data is the 32-bit value to write to the register
566 *
567 * @return None.
568 *
569 * @note
570 * C-style signature:
571 * void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
572 *
573 *****************************************************************************/
574 #define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
575 (Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data))))
578 /****************************************************************************/
579 /**
580 *
581 * Enable specific interrupt(s) in the interrupt controller.
582 *
583 * @param DistBaseAddress is the Distributor Register base address of the
584 * device
585 * @param Int_Id is the ID of the interrupt source and should be in the
586 * range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
587 *
588 * @return None.
589 *
590 * @note C-style signature:
591 * void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id)
592 *
593 *****************************************************************************/
594 #define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \
595 XScuGic_WriteReg((DistBaseAddress), \
596 XSCUGIC_ENABLE_SET_OFFSET + (((Int_Id) / 32U) * 4U), \
597 (0x00000001U << ((Int_Id) % 32U)))
599 /****************************************************************************/
600 /**
601 *
602 * Disable specific interrupt(s) in the interrupt controller.
603 *
604 * @param DistBaseAddress is the Distributor Register base address of the
605 * device
606 * @param Int_Id is the ID of the interrupt source and should be in the
607 * range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
608 *
609 *
610 * @return None.
611 *
612 * @note C-style signature:
613 * void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id)
614 *
615 *****************************************************************************/
616 #define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \
617 XScuGic_WriteReg((DistBaseAddress), \
618 XSCUGIC_DISABLE_OFFSET + (((Int_Id) / 32U) * 4U), \
619 (0x00000001U << ((Int_Id) % 32U)))
622 /************************** Function Prototypes ******************************/
624 void XScuGic_DeviceInterruptHandler(void *DeviceId);
625 s32 XScuGic_DeviceInitialize(u32 DeviceId);
626 void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
627 Xil_InterruptHandler Handler, void *CallBackRef);
628 void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
629 u8 Priority, u8 Trigger);
630 void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
631 u8 *Priority, u8 *Trigger);
632 /************************** Variable Definitions *****************************/
633 #ifdef __cplusplus
634 }
635 #endif
637 #endif /* end of protection macro */