index a7a157ad508fc1792f63aaf2a099e456d8e2136b..1d82e4d8c1421d870cfda4fbc32762bee5afd26f 100644 (file)
* boots on the same core may experience cache inconsistencies.
*
*/
- env_disable_cache();
+ /* env_disable_cache(); */
+
+ /*
+ * Flush and Invalidate the caches - When the application is built with
+ * Xilinx Standalone BSP, caches are invalidated as part of boot process.
+ * Even if the master boots firmware multiple times without hard reset on
+ * same core, caches are flushed and invalidated at the end of
+ * remoteproc_resource_deinit for this run and caches would be again
+ * invalidated before starting the main thread of the application on next
+ * run to avoid any cache inconsistencies.
+ */
+ env_flush_invalidate_all_caches();
+
return RPROC_SUCCESS;
}