Remove Zynq7 generic system implementation

As the Zynq7 generic system implementation is covered by libmetal,
removed the implementation in the OpenAMP repo.

Signed-off-by: Wendy Liang <jliang@xilinx.com>

diff --git a/lib/include/openamp/system/generic/machine/zynq7/machine_system.h b/lib/include/openamp/system/generic/machine/zynq7/machine_system.h
deleted file mode 100755 (executable)
index b0aa296..0000000
--- a/lib/include/openamp/system/generic/machine/zynq7/machine_system.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (c) 2014, Mentor Graphics Corporation
- * All rights reserved.
- *
- * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of the <ORGANIZATION> nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _MACHINE_SYSTEM_H
-#define _MACHINE_SYSTEM_H
-
-/* Memory barrier */
-#if (defined(__CC_ARM))
-#define MEM_BARRIER() __schedule_barrier()
-#elif (defined(__GNUC__))
-#define MEM_BARRIER() asm volatile("dsb" : : : "memory")
-#else
-#define MEM_BARRIER()
-#endif
-
-static inline unsigned int xchg(void* plock, unsigned int lockVal)
-{
-       volatile unsigned int tmpVal = 0;
-       volatile unsigned int tmpVal1 = 0;
-
-#ifdef __GNUC__
-
-       asm (
-               "1:                                \n\t"
-               "LDREX  %[tmpVal], [%[plock]]      \n\t"
-               "STREX  %[tmpVal1], %[lockVal], [%[plock]] \n\t"
-               "CMP    %[tmpVal1], #0                     \n\t"
-               "BNE    1b                         \n\t"
-               "DMB                               \n\t"
-               : [tmpVal] "=&r"(tmpVal)
-               : [tmpVal1] "r" (tmpVal1), [lockVal] "r"(lockVal), [plock] "r"(plock)
-               : "cc", "memory"
-       );
-
-#endif
-
-       return tmpVal;
-}
-
-
-#endif                         /* _MACHINE_SYSTEM_H */

diff --git a/lib/system/generic/machine/zynq7/CMakeLists.txt b/lib/system/generic/machine/zynq7/CMakeLists.txt
index 5558ac47df497d0395024baa6a1f29dfdacb276e..19b24cafed0bfcf2f4ebe5f87b0188f059832e72 100644 (file)
--- a/lib/system/generic/machine/zynq7/CMakeLists.txt
+++ b/lib/system/generic/machine/zynq7/CMakeLists.txt
@@ -1,2 +1,5 @@
 
-collect (PROJECT_LIB_SOURCES machine_system.c)
+#collect (PROJECT_LIB_SOURCES machine_system.c)
+
+find_path (LIBXIL_INCLUDE_DIR NAMES xparameters.h PATHS ${CMAKE_FIND_ROOT_PATH})
+collect (PROJECT_INC_DIRS ${LIBXIL_INCLUDE_DIR})

diff --git a/lib/system/generic/machine/zynq7/machine_system.c b/lib/system/generic/machine/zynq7/machine_system.c
deleted file mode 100755 (executable)
index be34ea0..0000000
--- a/lib/system/generic/machine/zynq7/machine_system.c
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * Copyright (c) 2014, Mentor Graphics Corporation
- * All rights reserved.
- *
- * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of the <ORGANIZATION> nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-#include <stdio.h>
-#include <string.h>
-#include "baremetal.h"
-#include "machine_system.h"
-#include "openamp/env.h"
-#include "openamp/hil.h"
-
-static inline unsigned int get_cpu_id_arm(void)
-{
-       unsigned long cpu_id = 0;
-
-       asm volatile ("MRC p15 ,"
-                     "0," "%0," "c0," "c0," "5":[cpu_id] "=&r"(cpu_id)
-                     : /* No inputs */ );
-
-       /*
-        * Return cpu id to caller, extract last two bits from Multiprocessor
-        * Affinity Register */
-       return (cpu_id & 0x03);
-}
-
-int platform_interrupt_enable(unsigned int vector_id, unsigned int polarity,
-                             unsigned int priority)
-{
-       unsigned long reg_offset;
-       unsigned long bit_shift;
-       unsigned long temp32 = 0;
-       unsigned long targ_cpu;
-
-       temp32 = get_cpu_id_arm();
-
-       /* Determine the necessary bit shift in this target / priority register
-          for this interrupt vector ID */
-       bit_shift = ((vector_id) % 4) * 8;
-
-       /* Build a target value based on the bit shift calculated above and the CPU core
-          that this code is executing on */
-       targ_cpu = (1 << temp32) << bit_shift;
-
-       /* Determine the Global interrupt controller target / priority register
-          offset for this interrupt vector ID
-          NOTE:  Each target / priority register supports 4 interrupts */
-       reg_offset = ((vector_id) / 4) * 4;
-
-       /* Read-modify-write the priority register for this interrupt */
-       temp32 = MEM_READ32(INT_GIC_DIST_BASE + INT_GIC_DIST_PRI + reg_offset);
-
-       /* Set new priority. */
-       temp32 |= (priority << (bit_shift + 4));
-       MEM_WRITE32(INT_GIC_DIST_BASE + INT_GIC_DIST_PRI + reg_offset, temp32);
-
-       /* Read-modify-write the target register for this interrupt to allow this
-          cpu to accept this interrupt */
-       temp32 =
-           MEM_READ32(INT_GIC_DIST_BASE + INT_GIC_DIST_TARGET + reg_offset);
-       temp32 |= targ_cpu;
-       MEM_WRITE32(INT_GIC_DIST_BASE + INT_GIC_DIST_TARGET + reg_offset,
-                   temp32);
-
-       /* Determine the Global interrupt controller enable set register offset
-          for this vector ID
-          NOTE:  There are 32 interrupts in each enable set register */
-       reg_offset = (vector_id / 32) * 4;
-
-       /* Write to the appropriate bit in the enable set register for this
-          vector ID to enable the interrupt */
-
-       temp32 = (1UL << (vector_id - (reg_offset * 0x08)));
-       MEM_WRITE32(INT_GIC_DIST_BASE + INT_GIC_DIST_ENABLE_SET + reg_offset,
-                   temp32);
-
-       /* Return the vector ID */
-       return (vector_id);
-}
-
-int platform_interrupt_disable(unsigned int vector_id)
-{
-       unsigned long reg_offset;
-       unsigned long bit_shift;
-       unsigned long temp32 = 0;
-       unsigned long targ_cpu;
-
-       temp32 = get_cpu_id_arm();
-
-       /* Determine the Global interrupt controller enable set register offset
-          for this vector ID
-          NOTE:  There are 32 interrupts in each enable set register */
-       reg_offset = (vector_id / 32) * 4;
-
-       /* Write to the appropriate bit in the enable clear register for this
-          vector ID to disable the interrupt */
-
-       MEM_WRITE32(INT_GIC_DIST_BASE + INT_GIC_DIST_ENABLE_CLEAR + reg_offset,
-                   (1UL << (vector_id - (reg_offset * 0x08))));
-
-       /* Determine the Global interrupt controller target register offset for
-          this interrupt vector ID
-          NOTE:  Each target register supports 4 interrupts */
-       reg_offset = (vector_id / 4) * 4;
-
-       /* Determine the necessary bit shift in this target register for this
-          vector ID */
-       bit_shift = (vector_id % 4) * 8;
-
-       /* Build a value based on the bit shift calculated above and the CPU core
-          that this code is executing on */
-       targ_cpu = (1 << temp32) << bit_shift;
-
-       /* Read-modify-write the target register for this interrupt and remove this cpu from
-          accepting this interrupt */
-       temp32 =
-           MEM_READ32(INT_GIC_DIST_BASE + INT_GIC_DIST_TARGET + reg_offset);
-       temp32 &= ~targ_cpu;
-
-       MEM_WRITE32(INT_GIC_DIST_BASE + INT_GIC_DIST_TARGET + reg_offset,
-                   temp32);
-
-       /* Return the vector ID */
-       return (vector_id);
-}
-
-int old_value = 0;
-
-void restore_global_interrupts()
-{
-       ARM_AR_INT_BITS_SET(old_value);
-}
-
-void disable_global_interrupts()
-{
-       int value = 0;
-       ARM_AR_INT_BITS_GET(&value);
-       if (value != old_value) {
-               ARM_AR_INT_BITS_SET(ARM_AR_INTERRUPTS_DISABLE_BITS);
-               old_value = value;
-       }
-}
-
-void platform_map_mem_region(unsigned int vrt_addr, unsigned int phy_addr,
-                            unsigned int size, unsigned int flags)
-{
-       int is_mem_mapped = 0;
-       int cache_type = 0;
-
-       if ((flags & (0x0f << 4)) == MEM_MAPPED) {
-               is_mem_mapped = 1;
-       }
-
-       if ((flags & 0x0f) == WB_CACHE) {
-               cache_type = WRITEBACK;
-       } else if ((flags & 0x0f) == WT_CACHE) {
-               cache_type = WRITETHROUGH;
-       } else {
-               cache_type = NOCACHE;
-       }
-
-       arm_ar_map_mem_region(vrt_addr, phy_addr, size, is_mem_mapped,
-                             cache_type);
-}
-
-void platform_cache_all_flush_invalidate()
-{
-       ARM_AR_MEM_DCACHE_ALL_OP(1);
-}
-
-void platform_cache_disable()
-{
-       ARM_AR_MEM_CACHE_DISABLE();
-}
-
-unsigned long platform_vatopa(void *addr)
-{
-       return (((unsigned long)addr & (~(0x0fff << 20))) | (0x08 << 24));
-}
-
-void *platform_patova(unsigned long addr)
-{
-       unsigned long laddr =
-               ((unsigned long)addr & (~(0x0fff << 20))) | (0x08 << 24);
-       return ((void *)laddr);
-
-}
-
-void platform_isr(int vect_id, void * data)
-{
-    (void)vect_id;
-    hil_isr(((struct proc_vring *)data));
-}
-
-