Split zynqmp_r5 machine.c
authorWendy Liang <jliang@xilinx.com>
Mon, 1 Feb 2016 21:52:13 +0000 (13:52 -0800)
committerWendy Liang <jliang@xilinx.com>
Tue, 9 Feb 2016 19:55:45 +0000 (11:55 -0800)
zynqmp_r5 machine.c includes OpenAMP and non-OpenAMP but baremetal specific application helper functions.
This patch split it into:
* lib/system/generic/machine/zynqmp_r5/machin_system.c for OpenAMP zynqmp_r5 generic implementation
* apps/system/generic/machine/zynqmp_r5/helper.c for zynqmp_r5 baremetal app helper functions.

Signed-off-by: Wendy Liang <jliang@xilinx.com>
apps/machine/zynqmp_r5/Makefile.include [new file with mode: 0644]
apps/machine/zynqmp_r5/platform_info.c [moved from apps/system/generic/machine/zynqmp_r5/platform_info.c with 100% similarity]
apps/machine/zynqmp_r5/rsc_table.c [moved from apps/system/generic/machine/zynqmp_r5/rsc_table.c with 100% similarity]
apps/machine/zynqmp_r5/rsc_table.h [moved from apps/system/generic/machine/zynqmp_r5/rsc_table.h with 100% similarity]
apps/system/generic/machine/zynqmp_r5/Makefile.include
apps/system/generic/machine/zynqmp_r5/helper.c [new file with mode: 0644]
lib/include/openamp/machine/zynqmp_r5/machine.h [new file with mode: 0755]
lib/include/openamp/system/generic/machine/zynqmp_r5/machine.h [deleted file]
lib/include/openamp/system/generic/machine/zynqmp_r5/machine_system.h [new file with mode: 0755]
lib/system/generic/machine/zynqmp_r5/machine.c

diff --git a/apps/machine/zynqmp_r5/Makefile.include b/apps/machine/zynqmp_r5/Makefile.include
new file mode 100644 (file)
index 0000000..20f2f3f
--- /dev/null
@@ -0,0 +1,6 @@
+CFLAGS += $(ARCH_CFLAGS)
+CFLAGS += -I"$(call local_dir,.)"
+
+C_COMMON_SRCS := $(call local_dir,platform_info.c)
+C_COMMON_SRCS += $(call local_dir,rsc_table.c)
+
index 8854d8fde53b741a6ab802e275dc3685de930e0a..89d10cc187d6de892576353b56f719980952fc80 100644 (file)
@@ -1,5 +1,3 @@
-CFLAGS += $(ARCH_CFLAGS)
-CFLAGS += -DZYNQMP_R5
 CFLAGS += -I"$(call local_dir,.)"
 DEPS := -lxil -lc -lm
 
@@ -9,7 +7,7 @@ else
 LINKERSCRIPT := $(call local_dir,linker_remote.ld)
 endif
 
-C_COMMON_SRCS := $(wildcard $(call local_dir,)*.c)
+C_COMMON_SRCS += $(wildcard $(call local_dir,)*.c)
 
 ifeq ($(EXTRA_INCLUDES),)
 EXTRA_INCLUDES += -I"$(OHOME)/obsolete/system/$(SYSTEM)/machine/$(MACHINE)/xil_standalone_lib"
diff --git a/apps/system/generic/machine/zynqmp_r5/helper.c b/apps/system/generic/machine/zynqmp_r5/helper.c
new file mode 100644 (file)
index 0000000..ce0a052
--- /dev/null
@@ -0,0 +1,96 @@
+
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ *
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of the <ORGANIZATION> nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <string.h>
+#include "xparameters.h"
+#include "xil_exception.h"
+#include "xscugic.h"
+
+#define INTC_DEVICE_ID         XPAR_SCUGIC_0_DEVICE_ID
+
+XScuGic InterruptController;
+
+extern void bm_env_isr(int vector);
+
+void zynqmp_r5_irq_isr()
+{
+
+       unsigned int raw_irq;
+       int irq_vector;
+       raw_irq =
+           (unsigned int)XScuGic_CPUReadReg(&InterruptController,
+                                            XSCUGIC_INT_ACK_OFFSET);
+       irq_vector = (int)(raw_irq & XSCUGIC_ACK_INTID_MASK);
+
+       bm_env_isr(irq_vector);
+
+       XScuGic_CPUWriteReg(&InterruptController, XSCUGIC_EOI_OFFSET, raw_irq);
+}
+
+int zynqmp_r5_gic_initialize()
+{
+       u32 Status;
+
+       Xil_ExceptionDisable();
+
+       XScuGic_Config *IntcConfig;     /* The configuration parameters of the interrupt controller */
+
+       /*
+        * Initialize the interrupt controller driver
+        */
+       IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
+       if (NULL == IntcConfig) {
+               return XST_FAILURE;
+       }
+
+       Status = XScuGic_CfgInitialize(&InterruptController, IntcConfig,
+                                      IntcConfig->CpuBaseAddress);
+       if (Status != XST_SUCCESS) {
+               return XST_FAILURE;
+       }
+
+       /*
+        * Register the interrupt handler to the hardware interrupt handling
+        * logic in the ARM processor.
+        */
+       Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
+                                    (Xil_ExceptionHandler) zynqmp_r5_irq_isr,
+                                    &InterruptController);
+
+       Xil_ExceptionEnable();
+
+       return 0;
+}
+
+void init_system()
+{
+       zynqmp_r5_gic_initialize();
+}
diff --git a/lib/include/openamp/machine/zynqmp_r5/machine.h b/lib/include/openamp/machine/zynqmp_r5/machine.h
new file mode 100755 (executable)
index 0000000..8b2d926
--- /dev/null
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of the <ORGANIZATION> nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _MACHINE_H
+#define _MACHINE_H
+
+/* IPI REGs OFFSET */
+#define IPI_TRIG_OFFSET          0x00000000    /* IPI trigger register offset */
+#define IPI_OBS_OFFSET           0x00000004    /* IPI observation register offset */
+#define IPI_ISR_OFFSET           0x00000010    /* IPI interrupt status register offset */
+#define IPI_IMR_OFFSET           0x00000014    /* IPI interrupt mask register offset */
+#define IPI_IER_OFFSET           0x00000018    /* IPI interrupt enable register offset */
+#define IPI_IDR_OFFSET           0x0000001C    /* IPI interrupt disable register offset */
+
+#include "openamp/machine/machine_common.h"
+
+#endif                         /* _MACHINE_H */
diff --git a/lib/include/openamp/system/generic/machine/zynqmp_r5/machine.h b/lib/include/openamp/system/generic/machine/zynqmp_r5/machine.h
deleted file mode 100755 (executable)
index bef54fc..0000000
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of the <ORGANIZATION> nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _BAREMETAL_H
-#define _BAREMETAL_H
-
-#include "xil_types.h"
-#include "xparameters.h"
-#include "xil_cache.h"
-#include "xreg_cortexr5.h"
-
-#define INTC_DEVICE_ID         XPAR_SCUGIC_0_DEVICE_ID
-
-/* IPI REGs OFFSET */
-#define IPI_TRIG_OFFSET          0x00000000    /* IPI trigger register offset */
-#define IPI_OBS_OFFSET           0x00000004    /* IPI observation register offset */
-#define IPI_ISR_OFFSET           0x00000010    /* IPI interrupt status register offset */
-#define IPI_IMR_OFFSET           0x00000014    /* IPI interrupt mask register offset */
-#define IPI_IER_OFFSET           0x00000018    /* IPI interrupt enable register offset */
-#define IPI_IDR_OFFSET           0x0000001C    /* IPI interrupt disable register offset */
-
-#define platform_dcache_all_flush() { Xil_DCacheFlush(); }
-
-#define platform_dcache_flush_range(addr, len) { Xil_DCacheFlushRange(addr, len); }
-
-#define CORTEXR5_CPSR_INTERRUPTS_BITS (XREG_CPSR_IRQ_ENABLE | XREG_CPSR_FIQ_ENABLE)
-
-/* This macro writes the current program status register (CPSR - all fields) */
-#define ARM_AR_CPSR_CXSF_WRITE(cpsr_cxsf_value) \
-       { \
-               asm volatile("    MSR     CPSR_cxsf, %0" \
-                       : /* No outputs */ \
-                       : "r" (cpsr_cxsf_value) ); \
-       }
-
-/* This macro sets the interrupt related bits in the status register / control
- register to the specified value. */
-#define ARM_AR_INT_BITS_SET(set_bits) \
-       { \
-               int     tmp_val; \
-               tmp_val = mfcpsr(); \
-               tmp_val &= ~((unsigned int)CORTEXR5_CPSR_INTERRUPTS_BITS); \
-               tmp_val |= set_bits; \
-               ARM_AR_CPSR_CXSF_WRITE(tmp_val); \
-       }
-
-/* This macro gets the interrupt related bits from the status register / control
- register. */
-#define ARM_AR_INT_BITS_GET(get_bits_ptr) \
-       { \
-               int     tmp_val; \
-               tmp_val = mfcpsr(); \
-               tmp_val &= CORTEXR5_CPSR_INTERRUPTS_BITS; \
-               *get_bits_ptr = tmp_val; \
-       }
-
-/* Memory barrier */
-#if (defined(__CC_ARM))
-#define MEM_BARRIER() __schedule_barrier()
-#elif (defined(__GNUC__))
-#define MEM_BARRIER() asm volatile("dsb" : : : "memory")
-#else
-#define MEM_BARRIER()
-#endif
-
-static inline unsigned int xchg(void* plock, unsigned int lockVal)
-{
-       volatile unsigned int tmpVal = 0;
-       volatile unsigned int tmpVal1 = 0;
-
-#ifdef __GNUC__
-
-       asm (
-               "1:                                \n\t"
-               "LDREX  %[tmpVal], [%[plock]]      \n\t"
-               "STREX  %[tmpVal1], %[lockVal], [%[plock]] \n\t"
-               "CMP    %[tmpVal1], #0                     \n\t"
-               "BNE    1b                         \n\t"
-               "DMB                               \n\t"
-               : [tmpVal] "=&r"(tmpVal)
-               : [tmpVal1] "r" (tmpVal1), [lockVal] "r"(lockVal), [plock] "r"(plock)
-               : "cc", "memory"
-       );
-
-#endif
-
-       return tmpVal;
-}
-
-void zynqMP_r5_map_mem_region(u32 addr, u32 size, u32 attrib);
-
-int zynqMP_r5_gic_initialize();
-void zynqMP_r5_irq_isr();
-
-void restore_global_interrupts();
-void disable_global_interrupts();
-int platform_interrupt_enable(unsigned int vector, unsigned int polarity,
-                             unsigned int priority);
-int platform_interrupt_disable(unsigned int vector);
-void platform_cache_all_flush_invalidate();
-void platform_cache_disable();
-void platform_map_mem_region(unsigned int va, unsigned int pa,
-                            unsigned int size, unsigned int flags);
-unsigned long platform_vatopa(void *addr);
-void *platform_patova(unsigned long addr);
-
-#endif                         /* _BAREMETAL_H */
diff --git a/lib/include/openamp/system/generic/machine/zynqmp_r5/machine_system.h b/lib/include/openamp/system/generic/machine/zynqmp_r5/machine_system.h
new file mode 100755 (executable)
index 0000000..f967873
--- /dev/null
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of the <ORGANIZATION> nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _MACHINE_SYSTEM_H
+#define _MACHINE_SYSTEM_H
+
+/* Memory barrier */
+#if (defined(__CC_ARM))
+#define MEM_BARRIER() __schedule_barrier()
+#elif (defined(__GNUC__))
+#define MEM_BARRIER() asm volatile("dsb" : : : "memory")
+#else
+#define MEM_BARRIER()
+#endif
+
+static inline unsigned int xchg(void* plock, unsigned int lockVal)
+{
+       volatile unsigned int tmpVal = 0;
+       volatile unsigned int tmpVal1 = 0;
+
+#ifdef __GNUC__
+
+       asm (
+               "1:                                \n\t"
+               "LDREX  %[tmpVal], [%[plock]]      \n\t"
+               "STREX  %[tmpVal1], %[lockVal], [%[plock]] \n\t"
+               "CMP    %[tmpVal1], #0                     \n\t"
+               "BNE    1b                         \n\t"
+               "DMB                               \n\t"
+               : [tmpVal] "=&r"(tmpVal)
+               : [tmpVal1] "r" (tmpVal1), [lockVal] "r"(lockVal), [plock] "r"(plock)
+               : "cc", "memory"
+       );
+
+#endif
+
+       return tmpVal;
+}
+
+#endif                         /* _MACHINE_SYSTEM_H */
index bc1cc9714a196fce387adb25bb0a6ffcd86cdb6b..2775c62c17aa32cd9fe6989da23cb55ea39e03f9 100755 (executable)
 #include "xil_mmu.h"
 #include "xil_mpu.h"
 #include "machine.h"
+#include "machine_system.h"
 #include "openamp/env.h"
 
-XScuGic InterruptController;
+#define CORTEXR5_CPSR_INTERRUPTS_BITS (XREG_CPSR_IRQ_ENABLE | XREG_CPSR_FIQ_ENABLE)
 
-int zynqMP_r5_gic_initialize()
-{
-       u32 Status;
-
-       Xil_ExceptionDisable();
-
-       XScuGic_Config *IntcConfig;     /* The configuration parameters of the interrupt controller */
-
-       /*
-        * Initialize the interrupt controller driver
-        */
-       IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
-       if (NULL == IntcConfig) {
-               return XST_FAILURE;
+/* This macro writes the current program status register (CPSR - all fields) */
+#define ARM_AR_CPSR_CXSF_WRITE(cpsr_cxsf_value) \
+       { \
+               asm volatile("    MSR     CPSR_cxsf, %0" \
+                       : /* No outputs */ \
+                       : "r" (cpsr_cxsf_value) ); \
        }
 
-       Status = XScuGic_CfgInitialize(&InterruptController, IntcConfig,
-                                      IntcConfig->CpuBaseAddress);
-       if (Status != XST_SUCCESS) {
-               return XST_FAILURE;
+/* This macro sets the interrupt related bits in the status register / control
+ register to the specified value. */
+#define ARM_AR_INT_BITS_SET(set_bits) \
+       { \
+               int     tmp_val; \
+               tmp_val = mfcpsr(); \
+               tmp_val &= ~((unsigned int)CORTEXR5_CPSR_INTERRUPTS_BITS); \
+               tmp_val |= set_bits; \
+               ARM_AR_CPSR_CXSF_WRITE(tmp_val); \
        }
 
-       /*
-        * Register the interrupt handler to the hardware interrupt handling
-        * logic in the ARM processor.
-        */
-       Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
-                                    (Xil_ExceptionHandler) zynqMP_r5_irq_isr,
-                                    &InterruptController);
-
-       Xil_ExceptionEnable();
-
-       return 0;
-}
-
-extern void bm_env_isr(int vector);
-
-void zynqMP_r5_irq_isr()
-{
-
-       unsigned int raw_irq;
-       int irq_vector;
-       raw_irq =
-           (unsigned int)XScuGic_CPUReadReg(&InterruptController,
-                                            XSCUGIC_INT_ACK_OFFSET);
-       irq_vector = (int)(raw_irq & XSCUGIC_ACK_INTID_MASK);
-
-       bm_env_isr(irq_vector);
-
-       XScuGic_CPUWriteReg(&InterruptController, XSCUGIC_EOI_OFFSET, raw_irq);
-}
+/* This macro gets the interrupt related bits from the status register / control
+ register. */
+#define ARM_AR_INT_BITS_GET(get_bits_ptr) \
+       { \
+               int     tmp_val; \
+               tmp_val = mfcpsr(); \
+               tmp_val &= CORTEXR5_CPSR_INTERRUPTS_BITS; \
+               *get_bits_ptr = tmp_val; \
+       }
 
 /*
  ***********************************************************************
@@ -207,6 +185,11 @@ int platform_interrupt_disable(unsigned int vector)
        return (vector);
 }
 
+void platform_dcache_all_flush()
+{
+       Xil_DCacheFlush();
+}
+
 void platform_cache_all_flush_invalidate()
 {
        Xil_DCacheFlush();