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raw | patch | inline | side by side (parent: 9993283)
raw | patch | inline | side by side (parent: 9993283)
| author | Wendy Liang <jliang@xilinx.com> | |
| Mon, 5 Jan 2015 02:32:51 +0000 (18:32 -0800) | ||
| committer | Wendy Liang <jliang@xilinx.com> | |
| Mon, 6 Apr 2015 07:23:08 +0000 (17:23 +1000) |
It passed compilation, however, the following questions remain:
* Interrupts implementation not tested
* memory mapping not final
* ATF will occupy OCM
* Should also allow run the code in TCM
* Code may need to run in DDR if it is large
* shared memory needs to be in DDR
* file operation syscalls cannot be redefined in application
* looks like they have strong definition in newlib
* as workaround, I apply "weak" attribute to those functions
for non-proxy OpenAMP application.
* _fstat(), _isatty(), _lseek(), _open(), _close(), _read() and write()
in baremetal.c have "weak" attribute for non proxy application.
Signed-off-by: Wendy Liang <jliang@xilinx.com>
* Interrupts implementation not tested
* memory mapping not final
* ATF will occupy OCM
* Should also allow run the code in TCM
* Code may need to run in DDR if it is large
* shared memory needs to be in DDR
* file operation syscalls cannot be redefined in application
* looks like they have strong definition in newlib
* as workaround, I apply "weak" attribute to those functions
for non-proxy OpenAMP application.
* _fstat(), _isatty(), _lseek(), _open(), _close(), _read() and write()
in baremetal.c have "weak" attribute for non proxy application.
Signed-off-by: Wendy Liang <jliang@xilinx.com>
52 files changed:
diff --git a/Makefile.commons.zynqMP_r5 b/Makefile.commons.zynqMP_r5
--- /dev/null
@@ -0,0 +1,17 @@
+CROSS := arm-none-eabi-
+CFLAGS := -Wall -O2 -g -MMD
+CXXFLAGS := -Wall -MMD
+ASFLAGS := -MMD
+ARFLAGS :=
+ARCH_CFLAGS := -mfloat-abi=soft -mcpu=cortex-r5
+ARCH_CXXFLAGS := -mfloat-abi=soft -mcpu=cortex-r5
+ARCH_ASFLAGS := -mfloat-abi=soft -mcpu=cortex-r5
+ARCH_ARFLAGS :=
+CC = $(CROSS)gcc
+CXX = $(CROSS)g++
+AS = $(CROSS)as
+AR = $(CROSS)ar
+LD = $(CROSS)gcc
+OBJCPY = $(CROSS)objcopy
+
+INCLUDE += -I$(OHOME)/libs/system/$(PLAT)/$(OS)/xil_standalone_lib
diff --git a/libs/system/zynqMP_r5/baremetal/Makefile b/libs/system/zynqMP_r5/baremetal/Makefile
--- /dev/null
@@ -0,0 +1,14 @@
+# Make file to create baremetal lib.
+
+
+all:
+ make -f make_xil_standalone_lib
+ make -f make_remote
+ make -f make_remote_rpc
+clean:
+ make -f make_xil_standalone_lib
+ make -f make_remote clean
+ make -f make_remote_rpc clean
+ rm -rf .build
+
+PHONY: all clean
diff --git a/libs/system/zynqMP_r5/baremetal/Makefile.commons b/libs/system/zynqMP_r5/baremetal/Makefile.commons
--- /dev/null
@@ -0,0 +1,17 @@
+CROSS := arm-none-eabi-
+CFLAGS := -Wall -O2 -g -MMD
+CXXFLAGS := -Wall -MMD
+ASFLAGS := -MMD
+ARFLAGS :=
+ARCH_CFLAGS := -mfloat-abi=soft -mcpu=cortex-r5
+ARCH_CXXFLAGS := -mfloat-abi=soft -mcpu=cortex-r5
+ARCH_ASFLAGS := -mfloat-abi=soft -mcpu=cortex-r5
+ARCH_ARFLAGS :=
+CC = $(CROSS)gcc
+CXX = $(CROSS)g++
+AS = $(CROSS)as
+AR = $(CROSS)ar
+LD = $(CROSS)gcc
+OBJCPY = $(CROSS)objcopy
+
+INCLUDE += -I./xil_standalone_lib
diff --git a/libs/system/zynqMP_r5/baremetal/baremetal.c b/libs/system/zynqMP_r5/baremetal/baremetal.c
--- /dev/null
@@ -0,0 +1,351 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of the <ORGANIZATION> nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <stdio.h>
+#include <string.h>
+#include "baremetal.h"
+#include "xparameters.h"
+#include "xil_io.h"
+#include "xil_exception.h"
+
+/** name CPU Interface Register Map
+ *
+ * Define the offsets from the base address for all CPU registers of the
+ * interrupt controller, some registers may be reserved in the hardware device.
+ */
+#define XSCUGIC_CONTROL_OFFSET 0x00000000U /**< CPU Interface Control
+ Register */
+#define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004U /**< Priority Mask Reg */
+#define XSCUGIC_BIN_PT_OFFSET 0x00000008U /**< Binary Point Register */
+#define XSCUGIC_INT_ACK_OFFSET 0x0000000CU /**< Interrupt ACK Reg */
+#define XSCUGIC_EOI_OFFSET 0x00000010U /**< End of Interrupt Reg */
+#define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014U /**< Running Priority Reg */
+#define XSCUGIC_HI_PEND_OFFSET 0x00000018U /**< Highest Pending Interrupt
+ Register */
+#define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001CU /**< Aliased non-Secure
+ Binary Point Register */
+
+/** name Distributor Interface Register Map
+ *
+ * Define the offsets from the base address for all Distributor registers of
+ * the interrupt controller, some registers may be reserved in the hardware
+ * device.
+ */
+#define XSCUGIC_DIST_EN_OFFSET 0x00000000U /**< Distributor Enable
+ Register */
+#define XSCUGIC_IC_TYPE_OFFSET 0x00000004U /**< Interrupt Controller
+ Type Register */
+#define XSCUGIC_DIST_IDENT_OFFSET 0x00000008U /**< Implementor ID
+ Register */
+#define XSCUGIC_SECURITY_OFFSET 0x00000080U /**< Interrupt Security
+ Register */
+#define XSCUGIC_ENABLE_SET_OFFSET 0x00000100U /**< Enable Set
+ Register */
+#define XSCUGIC_DISABLE_OFFSET 0x00000180U /**< Enable Clear Register */
+#define XSCUGIC_PENDING_SET_OFFSET 0x00000200U /**< Pending Set
+ Register */
+#define XSCUGIC_PENDING_CLR_OFFSET 0x00000280U /**< Pending Clear
+ Register */
+#define XSCUGIC_ACTIVE_OFFSET 0x00000300U /**< Active Status Register */
+#define XSCUGIC_PRIORITY_OFFSET 0x00000400U /**< Priority Level Register */
+#define XSCUGIC_SPI_TARGET_OFFSET 0x00000800U /**< SPI Target
+ Register 0x800-0x8FB */
+#define XSCUGIC_INT_CFG_OFFSET 0x00000C00U /**< Interrupt Configuration
+ Register 0xC00-0xCFC */
+#define XSCUGIC_PPI_STAT_OFFSET 0x00000D00U /**< PPI Status Register */
+#define XSCUGIC_SPI_STAT_OFFSET 0x00000D04U /**< SPI Status Register
+ 0xd04-0xd7C */
+#define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80U /**< AHB Configuration
+ Register */
+#define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00U /**< Software Triggered
+ Interrupt Register */
+#define XSCUGIC_PERPHID_OFFSET 0x00000FD0U /**< Peripheral ID Reg */
+#define XSCUGIC_PCELLID_OFFSET 0x00000FF0U /**< Pcell ID Register */
+
+
+#define XScuGic_CPUWriteReg(RegOffset, Data) \
+ (Xil_Out32((XPAR_SCUGIC_0_CPU_BASEADDR + RegOffset), Data))
+
+#define XScuGic_CPUReadReg(RegOffset) \
+ (Xil_In32(XPAR_SCUGIC_0_CPU_BASEADDR + RegOffset))
+
+#define XScuGic_DistWriteReg(RegOffset, Data) \
+ (Xil_Out32((XPAR_SCUGIC_0_DIST_BASEADDR + RegOffset), Data))
+
+#define XScuGic_DistReadReg(RegOffset) \
+ (Xil_In32(XPAR_SCUGIC_0_DIST_BASEADDR + RegOffset))
+
+void zynqMP_r5_irq_isr();
+
+int zynqMP_r5_gic_initialize() {
+
+ Xil_ExceptionDisable();
+
+ /* Assuming master has initialized the GIC distributor,
+ * do not initialize distributor from slave */
+
+ /* Program the priority mask of the CPU using the Priority mask register */
+ XScuGic_CPUWriteReg(XSCUGIC_CPU_PRIOR_OFFSET, 0xF0U);
+ XScuGic_CPUWriteReg(XSCUGIC_CONTROL_OFFSET, 0x07U);
+
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler)zynqMP_r5_irq_isr, NULL);
+
+ Xil_ExceptionEnable();
+
+ return 0;
+}
+
+extern void bm_env_isr(int vector);
+
+void zynqMP_r5_irq_isr() {
+
+ unsigned int raw_irq;
+ int irq_vector;
+ raw_irq = (unsigned int)XScuGic_CPUReadReg(XSCUGIC_INT_ACK_OFFSET);
+
+ irq_vector = (int) (raw_irq & INT_ACK_MASK);
+
+ bm_env_isr(irq_vector);
+
+ XScuGic_CPUWriteReg(XSCUGIC_EOI_OFFSET, raw_irq);
+}
+
+int zynqMP_r5_gic_interrupt_enable(int vector_id, INT_TRIG_TYPE trigger_type,
+ int priority) {
+ /* Not implement setting priority of interrupt */
+ unsigned int mask;
+
+ mask = 0x00000001U << ((unsigned int)(vector_id) % 32U);
+ /*
+ * Enable the selected interrupt source by setting the
+ * corresponding bit in the Enable Set register.
+ */
+ XScuGic_DistWriteReg((u32)XSCUGIC_ENABLE_SET_OFFSET + (((unsigned int)(vector_id) / 32U) * 4U), mask);
+ return vector_id;
+}
+
+int zynqMP_r5_gic_interrupt_disable(int vector_id) {
+
+ unsigned int mask;
+ /*
+ * The Int_Id is used to create the appropriate mask for the
+ * desired bit position. Int_Id currently limited to 0 - 31
+ */
+ mask = 0x00000001U << ((unsigned int)(vector_id) % 32U);
+
+ /*
+ * Disable the selected interrupt source by setting the
+ * corresponding bit in the IDR.
+ */
+ XScuGic_DistWriteReg((u32)XSCUGIC_DISABLE_OFFSET + (((unsigned int)(vector_id) / 32U) * 4U), mask);
+
+ return vector_id;
+}
+
+extern void bm_env_isr(int vector);
+
+
+unsigned int old_value = 0;
+
+void restore_global_interrupts() {
+ ARM_AR_INT_BITS_SET(old_value);
+}
+
+void disable_global_interrupts() {
+ unsigned int value = 0;
+ ARM_AR_INT_BITS_GET(&value);
+ if (value != old_value) {
+ ARM_AR_INT_BITS_SET(CORTEXR5_CPSR_INTERRUPTS_BITS);
+ old_value = value;
+ }
+}
+
+/***********************************************************************
+ *
+ *
+ * zynqMP_r5_map_mem_region
+ *
+ *
+ * This function sets-up the region of memory based on the given
+ * attributes
+ * There is no MMU for R5, no need to map phy address to vrt_addr
+ *
+ * @param vrt_addr - virtual address of region
+ * @param phy_addr - physical address of region
+ * @parma size - size of region
+ * @param is_mem_mapped - memory mapped or not
+
+ * @param cache_type - cache type of region
+ *
+ *
+ * OUTPUTS
+ *
+ * None
+ *
+ ***********************************************************************/
+void zynqMP_r5_map_mem_region(unsigned int vrt_addr, unsigned int phy_addr,
+ unsigned int size, int is_mem_mapped,
+ CACHE_TYPE cache_type) {
+ return;
+}
+
+/*==================================================================*/
+/* The function definitions below are provided to prevent the build */
+/* warnings for missing I/O function stubs in case of unhosted libs */
+/*==================================================================*/
+
+#include <sys/stat.h>
+
+/**
+ * _fstat
+ *
+ * Status of an open file. For consistency with other minimal
+ * implementations in these examples, all files are regarded
+ * as character special devices.
+ *
+ * @param file - Unused.
+ * @param st - Status structure.
+ *
+ *
+ * A constant value of 0.
+ *
+ **/
+__attribute__((weak)) int _fstat(int file, struct stat * st)
+{
+ return(0);
+}
+
+/**
+ * isatty
+ *
+ *
+ * Query whether output stream is a terminal. For consistency
+ * with the other minimal implementations, which only support
+ * output to stdout, this minimal implementation is suggested
+ *
+ * @param file - Unused
+ *
+ * @return s - A constant value of 1.
+ *
+ */
+__attribute__((weak)) int _isatty(int file)
+{
+ return(1);
+}
+
+/**
+ *_lseek
+ *
+ * Set position in a file. Minimal implementation.
+
+ *
+ * @param file - Unused
+ *
+ * @param ptr - Unused
+ *
+ * @param dir - Unused
+ *
+ * @return - A constant value of 0.
+ *
+ */
+__attribute__((weak)) int _lseek(int file, int ptr, int dir)
+{
+ return(0);
+}
+
+#if (RTL_RPC == 0)
+/**
+ * _open
+ *
+ * Open a file. Minimal implementation
+ *
+ * @param filename - Unused
+ * @param flags - Unused
+ * @param mode - Unused
+ *
+ * return - A constant value of 1.
+ *
+ */
+__attribute__((weak)) int _open(const char * filename, int flags, int mode)
+{
+ /* Any number will work. */
+ return(1);
+}
+
+/**
+ * _close
+ *
+ * Close a file. Minimal implementation.
+ *
+ *
+ * @param file - Unused
+ *
+ *
+ * return A constant value of -1.
+ *
+ */
+__attribute__((weak)) int _close(int file)
+{
+ return(-1);
+}
+
+/**
+ * _read
+ *
+ * Low level function to redirect IO to serial.
+ *
+ * @param fd - Unused
+ * @param buffer - Buffer where read data will be placed.
+ * @param buflen - Size (in bytes) of buffer.
+ *
+ * return - A constant value of 1.
+ *
+ */
+__attribute__((weak)) int _read(int fd, char * buffer, int buflen)
+{
+ return -1;
+}
+
+/**
+ * _write
+ *
+ * Low level function to redirect IO to serial.
+ *
+ *
+ * @param file - Unused
+ * @param CHAR *ptr - String to output
+ * @param len - Length of the string
+ *
+ * return len - The length of the string
+ *
+ */
+__attribute__((weak)) int _write (int file, const char * ptr, int len)
+{
+ return 0;
+}
+#endif
diff --git a/libs/system/zynqMP_r5/baremetal/baremetal.h b/libs/system/zynqMP_r5/baremetal/baremetal.h
--- /dev/null
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of the <ORGANIZATION> nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _BAREMETAL_H
+#define _BAREMETAL_H
+
+#include "xil_cache.h"
+#include "xreg_cortexr5.h"
+#include "xpseudo_asm_gcc.h"
+
+#define MEM_READ8(addr) *(volatile unsigned char *)(addr)
+#define MEM_READ16(addr) *(volatile unsigned short *)(addr)
+#define MEM_READ32(addr) *(volatile unsigned long *)(addr)
+#define MEM_WRITE8(addr,data) *(volatile unsigned char *)(addr) = (unsigned char)(data)
+#define MEM_WRITE16(addr,data) *(volatile unsigned short *)(addr) = (unsigned short)(data)
+#define MEM_WRITE32(addr,data) *(volatile unsigned long *)(addr) = (unsigned long)(data)
+
+#ifndef BAREMETAL_MASTER
+#define BAREMETAL_MASTER 0
+#endif
+
+/* Define Interrupt Ack Mask */
+#define INT_ACK_MASK 0x000003FF
+
+/* The vector table address is the same as image entry point */
+#define RAM_VECTOR_TABLE_ADDR ELF_START
+
+typedef enum {
+ TRIG_NOT_SUPPORTED,
+ TRIG_RISING_EDGE,
+ TRIG_FALLING_EDGE,
+ TRIG_LEVEL_LOW,
+ TRIG_LEVEL_HIGH,
+ TRIG_RISING_FALLING_EDGES,
+ TRIG_HIGH_LOW_RISING_FALLING_EDGES
+} INT_TRIG_TYPE;
+
+typedef enum {
+ NOCACHE,
+ WRITEBACK,
+ WRITETHROUGH
+} CACHE_TYPE;
+
+#define CORTEXR5_CPSR_INTERRUPTS_BITS (XREG_CPSR_IRQ_ENABLE | XREG_CPSR_FIQ_ENABLE)
+
+/* This macro writes the current program status register (CPSR - all fields) */
+#define ARM_AR_CPSR_CXSF_WRITE(cpsr_cxsf_value) \
+ { \
+ asm volatile(" MSR CPSR_cxsf, %0" \
+ : /* No outputs */ \
+ : "r" (cpsr_cxsf_value) ); \
+ }
+
+/* This macro sets the interrupt related bits in the status register / control
+ register to the specified value. */
+#define ARM_AR_INT_BITS_SET(set_bits) \
+ { \
+ int tmp_val; \
+ tmp_val = mfcpsr(); \
+ tmp_val &= ~((unsigned int)CORTEXR5_CPSR_INTERRUPTS_BITS); \
+ tmp_val |= set_bits; \
+ ARM_AR_CPSR_CXSF_WRITE(tmp_val); \
+ }
+
+/* This macro gets the interrupt related bits from the status register / control
+ register. */
+#define ARM_AR_INT_BITS_GET(get_bits_ptr) \
+ { \
+ int tmp_val; \
+ tmp_val = mfcpsr(); \
+ tmp_val &= CORTEXR5_CPSR_INTERRUPTS_BITS; \
+ *get_bits_ptr = tmp_val; \
+ }
+
+#define SWITCH_TO_SYS_MODE() \
+ { \
+ mtcpsr((mfcpsr() | XREG_CPSR_SYSTEM_MODE) & ~((unsigned int)CORTEXR5_CPSR_INTERRUPTS_BITS));\
+ }
+
+void zynqMP_r5_map_mem_region(unsigned int vrt_addr, unsigned int phy_addr,
+ unsigned int size, int is_mem_mapped, CACHE_TYPE cache_type);
+
+int zynqMP_r5_gic_interrupt_enable(int vector_id, INT_TRIG_TYPE trigger_type,
+ int priority);
+int zynqMP_r5_gic_interrupt_disable(int vector_id);
+void restore_global_interrupts();
+void disable_global_interrupts();
+
+/* define function macros for OpenAMP API */
+#define platform_cache_all_flush_invalidate() \
+ { \
+ Xil_DCacheFlush(); \
+ Xil_DCacheInvalidate(); \
+ Xil_ICacheInvalidate(); \
+ }
+
+#define platform_cache_disable() \
+ { \
+ Xil_DCacheDisable(); \
+ Xil_ICacheDisable(); \
+ }
+
+#define platform_interrupt_enable(...) zynqMP_r5_gic_interrupt_enable(__VA_ARGS__)
+#define platform_interrupt_disable(...) zynqMP_r5_gic_interrupt_disable(__VA_ARGS__)
+#define platform_map_mem_region(...)
+
+#endif /* _BAREMETAL_H */
diff --git a/libs/system/zynqMP_r5/baremetal/linker_remote.ld b/libs/system/zynqMP_r5/baremetal/linker_remote.ld
--- /dev/null
@@ -0,0 +1,305 @@
+/*******************************************************************/
+/* */
+/* This file is automatically generated by linker script generator.*/
+/* */
+/* Version: */
+/* */
+/* Copyright (c) 2010 Xilinx, Inc. All rights reserved. */
+/* */
+/* Description : Cortex-R5 Linker Script */
+/* */
+/*******************************************************************/
+
+_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
+_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
+
+_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
+_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
+_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
+_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
+_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
+
+/* Define Memories in the system */
+
+MEMORY
+{
+ ps8_bbram_0_S_AXI_BASEADDR : ORIGIN = 0xFFCC4000, LENGTH = 0x00001000
+ ps8_csu_ram_0_S_AXI_BASEADDR : ORIGIN = 0xFFC40000, LENGTH = 0x00008000
+ ps8_ocm_ram_0_S_AXI_BASEADDR : ORIGIN = 0xFFFC0000, LENGTH = 0x00020000
+ ps8_ocm_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x00010000
+ ps8_r5_tcm_ram_0_S_AXI_BASEADDR : ORIGIN = 0x00000050, LENGTH = 0x0001FFB1
+}
+
+/* Specify the default entry point to the program */
+
+ENTRY(_boot)
+
+/* Define the sections, and where they are mapped in memory */
+
+SECTIONS
+{
+.vectors 0x00000000 : {
+ KEEP (*(.vectors))
+}
+
+_binary_firmware1_start = 0;
+_binary_firmware1_end = 0;
+_binary_firmware2_start = 0;
+_binary_firmware2_end = 0;
+
+.text : {
+ *(.boot)
+ *(.text)
+ *(.text.*)
+ *(.gnu.linkonce.t.*)
+ *(.plt)
+ *(.gnu_warning)
+ *(.gcc_execpt_table)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.vfp11_veneer)
+ *(.ARM.extab)
+ *(.gnu.linkonce.armextab.*)
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+.init : {
+ KEEP (*(.init))
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+.fini : {
+ KEEP (*(.fini))
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+.interp : {
+ KEEP (*(.interp))
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+.note-ABI-tag : {
+ KEEP (*(.note-ABI-tag))
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+.rodata : {
+ __rodata_start = .;
+ *(.rodata)
+ *(.rodata.*)
+ *(.gnu.linkonce.r.*)
+ __rodata_end = .;
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+.rodata1 : {
+ __rodata1_start = .;
+ *(.rodata1)
+ *(.rodata1.*)
+ __rodata1_end = .;
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+.sdata2 : {
+ __sdata2_start = .;
+ *(.sdata2)
+ *(.sdata2.*)
+ *(.gnu.linkonce.s2.*)
+ __sdata2_end = .;
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+.sbss2 : {
+ __sbss2_start = .;
+ *(.sbss2)
+ *(.sbss2.*)
+ *(.gnu.linkonce.sb2.*)
+ __sbss2_end = .;
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+.data : {
+ __data_start = .;
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d.*)
+ *(.jcr)
+ *(.got)
+ *(.got.plt)
+ __data_end = .;
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
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+ __data1_start = .;
+ *(.data1)
+ *(.data1.*)
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+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+.got : {
+ *(.got)
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+.ctors : {
+ __CTOR_LIST__ = .;
+ ___CTORS_LIST___ = .;
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ ___CTORS_END___ = .;
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+.dtors : {
+ __DTOR_LIST__ = .;
+ ___DTORS_LIST___ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ ___DTORS_END___ = .;
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+.fixup : {
+ __fixup_start = .;
+ *(.fixup)
+ __fixup_end = .;
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+.eh_frame : {
+ *(.eh_frame)
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+.eh_framehdr : {
+ __eh_framehdr_start = .;
+ *(.eh_framehdr)
+ __eh_framehdr_end = .;
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+.gcc_except_table : {
+ *(.gcc_except_table)
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+.mmu_tbl (ALIGN(16384)) : {
+ __mmu_tbl_start = .;
+ *(.mmu_tbl)
+ __mmu_tbl_end = .;
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+.ARM.exidx : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ *(.gnu.linkonce.armexidix.*.*)
+ __exidx_end = .;
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+.preinit_array : {
+ __preinit_array_start = .;
+ KEEP (*(SORT(.preinit_array.*)))
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+.init_array : {
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+.fini_array : {
+ __fini_array_start = .;
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array))
+ __fini_array_end = .;
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+.ARM.attributes : {
+ __ARM.attributes_start = .;
+ *(.ARM.attributes)
+ __ARM.attributes_end = .;
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+.sdata : {
+ __sdata_start = .;
+ *(.sdata)
+ *(.sdata.*)
+ *(.gnu.linkonce.s.*)
+ __sdata_end = .;
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+.sbss (NOLOAD) : {
+ __sbss_start = .;
+ *(.sbss)
+ *(.sbss.*)
+ *(.gnu.linkonce.sb.*)
+ __sbss_end = .;
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+.tdata : {
+ __tdata_start = .;
+ *(.tdata)
+ *(.tdata.*)
+ *(.gnu.linkonce.td.*)
+ __tdata_end = .;
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+.tbss : {
+ __tbss_start = .;
+ *(.tbss)
+ *(.tbss.*)
+ *(.gnu.linkonce.tb.*)
+ __tbss_end = .;
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+.bss (NOLOAD) : {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
+
+_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
+
+/* Generate Stack and Heap definitions */
+
+.heap (NOLOAD) : {
+ . = ALIGN(16);
+ _heap = .;
+ HeapBase = .;
+ _heap_start = .;
+ . += _HEAP_SIZE;
+ _heap_end = .;
+ HeapLimit = .;
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+.stack (NOLOAD) : {
+ . = ALIGN(16);
+ _stack_end = .;
+ . += _STACK_SIZE;
+ _stack = .;
+ __stack = _stack;
+ . = ALIGN(16);
+ _irq_stack_end = .;
+ . += _IRQ_STACK_SIZE;
+ __irq_stack = .;
+ _supervisor_stack_end = .;
+ . += _SUPERVISOR_STACK_SIZE;
+ . = ALIGN(16);
+ __supervisor_stack = .;
+ _abort_stack_end = .;
+ . += _ABORT_STACK_SIZE;
+ . = ALIGN(16);
+ __abort_stack = .;
+ _fiq_stack_end = .;
+ . += _FIQ_STACK_SIZE;
+ . = ALIGN(16);
+ __fiq_stack = .;
+ _undef_stack_end = .;
+ . += _UNDEF_STACK_SIZE;
+ . = ALIGN(16);
+ __undef_stack = .;
+} > ps8_ocm_ram_0_S_AXI_BASEADDR
+
+_end = .;
+end = .;
+}
diff --git a/libs/system/zynqMP_r5/baremetal/make_remote b/libs/system/zynqMP_r5/baremetal/make_remote
--- /dev/null
@@ -0,0 +1,36 @@
+# Include commons make file to get platform and tool chain specific variables.
+include Makefile.commons
+
+LIB_REMOTE := libbaremetal_remote.a
+
+CFLAGS+=-D"BAREMETAL_MASTER=0"
+
+SRCFILES += \
+$(wildcard *.c)
+
+OBJDIR := .build/baremetal_remote
+
+OBJFILES := $(patsubst %.c, $(OBJDIR)/%.o, $(SRCFILES))
+
+DEPFILES := $(patsubst %.c, $(OBJDIR)/%.d, $(SRCFILES))
+
+INCLUDE += -I./xil_standalone_lib
+
+all: $(LIB_REMOTE)
+
+$(LIB_REMOTE): $(OBJFILES)
+
+ @echo AR $@
+ $(AR) -r $@ $(OBJFILES)
+
+$(OBJDIR)/%.o:%.c $(HEADERS) $(OBJDIR)
+ @echo CC $(<:.c=.o)
+ $(CC) $(CFLAGS) $(ARCH_CFLAGS) $(INCLUDE) -c $< -o $@
+
+$(OBJDIR):
+ mkdir -p $@
+
+clean:
+ -$(RM) -r $(LIB_REMOTE) $(OBJDIR)
+
+PHONY: all clean
diff --git a/libs/system/zynqMP_r5/baremetal/make_remote_rpc b/libs/system/zynqMP_r5/baremetal/make_remote_rpc
--- /dev/null
@@ -0,0 +1,34 @@
+# Include commons make file to get platform and tool chain specific variables.
+include Makefile.commons
+
+LIB_REMOTE := libbaremetal_remote_rpc.a
+
+CFLAGS+=-D"RTL_RPC=1"
+
+SRCFILES += \
+$(wildcard *.c)
+
+OBJDIR := .build/baremetal_remote_rpc
+
+OBJFILES := $(patsubst %.c, $(OBJDIR)/%.o, $(SRCFILES))
+
+DEPFILES := $(patsubst %.c, $(OBJDIR)/%.d, $(SRCFILES))
+
+all: $(LIB_REMOTE)
+
+$(LIB_REMOTE): $(OBJFILES)
+
+ @echo AR $@
+ @$(AR) -r $@ $(OBJFILES)
+
+$(OBJDIR)/%.o:%.c $(HEADERS) $(OBJDIR)
+ @echo CC $(<:.c=.o)
+ @$(CC) $(CFLAGS) $(ARCH_CFLAGS) $(INCLUDE) -c $< -o $@
+
+$(OBJDIR):
+ mkdir -p $@
+
+clean:
+ -$(RM) -r $(LIB_REMOTE) $(OBJDIR)
+
+PHONY: all clean
diff --git a/libs/system/zynqMP_r5/baremetal/make_xil_standalone_lib b/libs/system/zynqMP_r5/baremetal/make_xil_standalone_lib
--- /dev/null
@@ -0,0 +1,17 @@
+# Include commons make file to get platform and tool chain specific variables.
+include Makefile.commons
+
+XIL_DIR := ./xil_standalone_lib
+LIB := libxil.a
+
+all: $(LIB)
+ make -C $(XIL_DIR) all
+
+$(LIB):
+ ln -s $(XIL_DIR)/$(LIB) $@
+
+clean:
+ make -C $(XIL_DIR) clean
+ -$(RM) $(LIB)
+
+.PHONY: all clean
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/Makefile b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/Makefile
--- /dev/null
@@ -0,0 +1,53 @@
+include config.make
+AS=arm-none-eabi-as
+CC=arm-none-eabi-gcc
+AR=arm-none-eabi-ar
+CP=cp
+ARCHIVER=arm-none-eabi-ar
+COMPILER_FLAGS= -O2 -c
+EXTRA_COMPILER_FLAGS= -mcpu=cortex-r5
+LIB=libxil.a
+
+LIB=libxil.a
+
+CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS))
+ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS))
+
+ifeq ($(COMPILER) , arm-eabi-gcc)
+ ECC_FLAGS = += -nostartfiles
+endif
+
+#The following flags are required for PEEP. We can remove them later
+ECC_FLAGS += -mcpu=cortex-r5 \
+ -mfloat-abi=soft \
+
+#RELEASEDIR=../../../lib
+RELEASEDIR=./.
+#INCLUDEDIR=../../../include
+#INCLUDES=-I./. -I${INCLUDEDIR}
+INCLUDES=-I./.
+
+OUTS = *.o
+
+INCLUDEFILES=*.h
+
+libs: $(LIBS)
+
+all: libs
+
+standalone_libs: $(LIBSOURCES)
+ @echo "Compiling standalone"
+ $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^
+ @echo "AR standalone"
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+
+
+.PHONY: include
+include: standalone_includes
+
+standalone_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+
+clean:
+ rm -rf ${OUTS} $(LIBS)
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/_exit.c b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/_exit.c
--- /dev/null
@@ -0,0 +1,55 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+#include <unistd.h>
+
+/* _exit - Simple implementation. Does not return.
+*/
+__attribute__((weak)) void _exit (int status)
+{
+ (void)status;
+ while (1)
+ {
+ __asm__("wfi");
+ }
+}
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/_sbrk.c b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/_sbrk.c
--- /dev/null
@@ -0,0 +1,72 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+#include <sys/types.h>
+
+extern int _heap_start;
+extern int _heap_end;
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) caddr_t _sbrk ( int incr );
+}
+#endif
+
+__attribute__((weak)) caddr_t _sbrk ( int incr )
+{
+ static unsigned char *heap = NULL;
+ unsigned char *prev_heap;
+
+ if (heap == NULL) {
+ heap = (unsigned char *)&_heap_start;
+ }
+ prev_heap = heap;
+
+ heap += incr;
+
+ if ((unsigned)heap > (unsigned)&_heap_end){
+ return (caddr_t) -1;
+ }
+ return (caddr_t) prev_heap;
+}
+
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/abort.c b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/abort.c
--- /dev/null
@@ -0,0 +1,53 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+#include <stdlib.h>
+#include <unistd.h>
+
+/*
+ * abort -- go out via exit...
+ */
+__attribute__((weak)) void abort(void)
+{
+ _exit(1);
+}
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/asm_vectors.S b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/asm_vectors.S
--- /dev/null
@@ -0,0 +1,132 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file asm_vectors.s
+*
+* This file contains the initial vector table for the Cortex R5 processor
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------- -------- ---------------------------------------------------
+* 5.00 pkp 02/10/14 Initial version
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+.org 0
+.text
+
+.globl _boot
+.globl _vector_table
+
+.globl FIQInterrupt
+.globl IRQInterrupt
+.globl SWInterrupt
+.globl DataAbortInterrupt
+.globl PrefetchAbortInterrupt
+
+.globl IRQHandler
+.globl prof_pc
+
+.section .vectors, "a"
+_vector_table:
+ ldr pc,=_boot
+ ldr pc,=Undefined
+ ldr pc,=SVCHandler
+ ldr pc,=PrefetchAbortHandler
+ ldr pc,=DataAbortHandler
+ NOP /* Placeholder for address exception vector*/
+ ldr pc,=IRQHandler
+ ldr pc,=FIQHandler
+
+.text
+IRQHandler: /* IRQ vector handler */
+ stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code*/
+ bl IRQInterrupt /* IRQ vector */
+ ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
+ subs pc, lr, #4 /* adjust return */
+
+FIQHandler: /* FIQ vector handler */
+ stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
+FIQLoop:
+ bl FIQInterrupt /* FIQ vector */
+ ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
+ subs pc, lr, #4 /* adjust return */
+
+Undefined: /* Undefined handler */
+ stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
+ ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
+ b _prestart
+ movs pc, lr
+
+SVCHandler: /* SWI handler */
+ stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
+ tst r0, #0x20 /* check the T bit */
+ ldrneh r0, [lr,#-2] /* Thumb mode */
+ bicne r0, r0, #0xff00 /* Thumb mode */
+ ldreq r0, [lr,#-4] /* ARM mode */
+ biceq r0, r0, #0xff000000 /* ARM mode */
+ bl SWInterrupt /* SWInterrupt: call C function here */
+ ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
+ movs pc, lr /* adjust return */
+
+DataAbortHandler: /* Data Abort handler */
+ stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
+ bl DataAbortInterrupt /*DataAbortInterrupt :call C function here */
+ ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
+ subs pc, lr, #8 /* adjust return */
+
+PrefetchAbortHandler: /* Prefetch Abort handler */
+ stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
+ bl PrefetchAbortInterrupt /* PrefetchAbortInterrupt: call C function here */
+ ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
+ subs pc, lr, #4 /* adjust return */
+
+
+.end
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/boot.S b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/boot.S
--- /dev/null
@@ -0,0 +1,204 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file boot.S
+*
+* This file contains the initial startup code for the Cortex R5 processor
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 pkp 02/10/14 Initial version
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#include "xparameters.h"
+
+
+.global _prestart
+.global _boot
+.global __stack
+.global __irq_stack
+.global __supervisor_stack
+.global __abort_stack
+.global __fiq_stack
+.global __undef_stack
+.global _vector_table
+
+
+/* Stack Pointer locations for boot code */
+.set Undef_stack, __undef_stack
+.set FIQ_stack, __fiq_stack
+.set Abort_stack, __abort_stack
+.set SPV_stack, __supervisor_stack
+.set IRQ_stack, __irq_stack
+.set SYS_stack, __stack
+
+.set vector_base, _vector_table
+
+.section .boot,"axS"
+
+
+/* this initializes the various processor modes */
+
+_prestart:
+_boot:
+
+
+
+OKToRun:
+
+/* Disable MPU and caches */
+ mrc p15, 0, r0, c1, c0, 0 /* Read CP15 Control Register*/
+ bic r0, r0, #0x05 /* Disable MPU (M bit) and data cache (C bit) */
+ bic r0, r0, #0x1000 /* Disable instruction cache (I bit) */
+ dsb /* Ensure all previous loads/stores have completed */
+ mcr p15, 0, r0, c1, c0, 0 /* Write CP15 Control Register */
+ isb /* Ensure subsequent insts execute wrt new MPU settings */
+
+/* Disable Branch prediction */
+ mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR */
+ orr r0, r0, #(0x1 << 17) /* Enable RSDIS bit 17 to disable the return stack */
+ orr r0, r0, #(0x1 << 16) /* Clear BP bit 15 and set BP bit 16:*/
+ bic r0, r0, #(0x1 << 15) /* Branch always not taken and history table updates disabled*/
+ mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/
+ dsb /* Complete all outstanding explicit memory operations*/
+
+/* Invalidate caches */
+ mov r0,#0 /* r0 = 0 */
+ dsb
+ mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
+ mcr p15, 0, r0, c15, c5, 0 /* Invalidate entire data cache*/
+ isb
+
+/*TCM configuration*/
+ ldr r0, =0x00000 /* Set ATCM base address*/
+ orr r0, r0, #1 /* Enable it*/
+ mcr p15, 0, r0, c9, c1, 1 /* Write ATCM Region Register*/
+
+ ldr r0, =0x20000 /* Set BTCM base address*/
+ orr r0, r0, #1 /* Enable it*/
+ mcr p15, 0, r0, c9, c1, 0 /* Write BTCM Region Register*/
+
+/* Initialize stack pointer for various mode */
+ mrs r0, cpsr /* get the current PSR */
+ mvn r1, #0x1f /* set up the irq stack pointer */
+ and r2, r1, r0
+ orr r2, r2, #0x12 /* IRQ mode */
+ msr cpsr, r2
+ ldr r13,=IRQ_stack /* IRQ stack pointer */
+
+ mrs r0, cpsr /* get the current PSR */
+ mvn r1, #0x1f /* set up the supervisor stack pointer */
+ and r2, r1, r0
+ orr r2, r2, #0x13 /* supervisor mode */
+ msr cpsr, r2
+ ldr r13,=SPV_stack /* Supervisor stack pointer */
+
+ mrs r0, cpsr /* get the current PSR */
+ mvn r1, #0x1f /* set up the Abort stack pointer */
+ and r2, r1, r0
+ orr r2, r2, #0x17 /* Abort mode */
+ msr cpsr, r2
+ ldr r13,=Abort_stack /* Abort stack pointer */
+
+ mrs r0, cpsr /* get the current PSR */
+ mvn r1, #0x1f /* set up the FIQ stack pointer */
+ and r2, r1, r0
+ orr r2, r2, #0x11 /* FIQ mode */
+ msr cpsr, r2
+ ldr r13,=FIQ_stack /* FIQ stack pointer */
+
+ mrs r0, cpsr /* get the current PSR */
+ mvn r1, #0x1f /* set up the Undefine stack pointer */
+ and r2, r1, r0
+ orr r2, r2, #0x1b /* Undefine mode */
+ msr cpsr, r2
+ ldr r13,=Undef_stack /* Undefine stack pointer */
+
+ mrs r0, cpsr /* get the current PSR */
+ mvn r1, #0x1f /* set up the system stack pointer */
+ and r2, r1, r0
+ orr r2, r2, #0x1F /* SYS mode */
+ msr cpsr, r2
+ ldr r13,=SYS_stack /* SYS stack pointer */
+
+ bl Init_MPU /* Initialize MPU */
+
+/*set exception vector to LOVEC */
+ mrc p15, 0, r0, c1, c0, 0
+ mvn r1, #0x2000
+ and r0, r0, r1
+ mcr p15, 0, r0, c1, c0, 0
+
+
+/* Enable icahce and dcache */
+ mrc p15,0,r1,c1,c0,0
+ ldr r0, =0x1004
+ orr r1,r1,r0
+ mcr p15,0,r1,c1,c0,0 /* Enable cache */
+ dsb
+ isb /* isb flush prefetch buffer */
+
+/* Enable Branch prediction */
+ mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/
+ bic r0, r0, #(0x1 << 17) /* Clear RSDIS bit 17 to enable return stack*/
+ bic r0, r0, #(0x1 << 16) /* Clear BP bit 15 and BP bit 16:*/
+ bic r0, r0, #(0x1 << 15) /* Normal operation, BP is taken from the global history table.*/
+ mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/
+
+ b _startup /* jump to C startup code */
+
+
+.Ldone: b .Ldone /* Paranoia: we should never get here */
+
+
+.end
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/bspconfig.h b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/bspconfig.h
--- /dev/null
@@ -0,0 +1,40 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSM.
+* Version: 2014.4
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2014 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Configurations for Standalone BSP
+*
+*******************************************************************/
+
+#define MICROBLAZE_PVR_NONE
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/config.make b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/config.make
--- /dev/null
@@ -0,0 +1,2 @@
+LIBSOURCES = *.c *.S
+LIBS = standalone_libs
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/cpu_init.S b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/cpu_init.S
--- /dev/null
@@ -0,0 +1,90 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file cpu_init.s
+*
+* This file contains CPU specific initialization. Invoked from main CRT
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------- -------- ---------------------------------------------------
+* 5.00 pkp 02/10/14 Initial version
+*
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+ .text
+ .global __cpu_init
+ .align 2
+__cpu_init:
+
+/* Clear cp15 regs with unknown reset values */
+ mov r0, #0x0
+ mcr p15, 0, r0, c5, c0, 0 /* DFSR */
+ mcr p15, 0, r0, c5, c0, 1 /* IFSR */
+ mcr p15, 0, r0, c6, c0, 0 /* DFAR */
+ mcr p15, 0, r0, c6, c0, 2 /* IFAR */
+ mcr p15, 0, r0, c9, c13, 2 /* PMXEVCNTR */
+ mcr p15, 0, r0, c13, c0, 2 /* TPIDRURW */
+ mcr p15, 0, r0, c13, c0, 3 /* TPIDRURO */
+
+
+/* Reset and start Cycle Counter */
+ mov r2, #0x80000000 /* clear overflow */
+ mcr p15, 0, r2, c9, c12, 3
+ mov r2, #0xd /* D, C, E */
+ mcr p15, 0, r2, c9, c12, 0
+ mov r2, #0x80000000 /* enable cycle counter */
+ mcr p15, 0, r2, c9, c12, 1
+
+ bx lr
+
+.end
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/errno.c b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/errno.c
--- /dev/null
@@ -0,0 +1,61 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+/* The errno variable is stored in the reentrancy structure. This
+ function returns its address for use by the macro errno defined in
+ errno.h. */
+
+#include <errno.h>
+#include <reent.h>
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) int * __errno ();
+}
+#endif
+
+__attribute__((weak)) int *
+__errno ()
+{
+ return &_REENT->_errno;
+}
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/mpu.c b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/mpu.c
--- /dev/null
@@ -0,0 +1,133 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file mpu.c
+*
+* This file contains initial configuration of the MPU.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 pkp 02/20/14 First release
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#include "xparameters.h"
+
+
+
+#include <xil_mpu.h>
+#include "xil_types.h"
+#include "xreg_cortexr5.h"
+
+void Init_MPU(void);
+
+void Init_MPU(void)
+{
+
+ unsigned int addr, reg_size, attrib, reg;
+ int reg_num;
+
+ addr = 0xFFFF0000;
+ reg_size=REGION_64K;
+ reg_num=0;
+ attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW;
+ Xil_SetAttribute(addr,reg_size,reg_num, attrib);
+
+ addr = 0xFFFC0000;
+ reg_size=REGION_128K;
+ reg_num=1;
+ attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW ;
+ Xil_SetAttribute(addr,reg_size,reg_num, attrib);
+
+ addr = 0xFFFE0000;
+ reg_size=REGION_64K;
+ reg_num=2;
+ attrib = NORM_NSHARED_WB_WA| PRIV_RW_USER_RW ;
+ Xil_SetAttribute(addr,reg_size,reg_num, attrib);
+
+ addr = 0xFD000000;
+ reg_size=REGION_4M;
+ reg_num=3;
+ attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
+ Xil_SetAttribute(addr,reg_size,reg_num, attrib);
+
+ addr = 0xFEC00000;
+ reg_size=REGION_4M;
+ reg_num=4;
+ attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
+ Xil_SetAttribute(addr,reg_size,reg_num, attrib);
+
+
+ addr = 0xFF000000;
+ reg_size=REGION_4M;
+ reg_num=5;
+ attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
+ Xil_SetAttribute(addr,reg_size,reg_num, attrib);
+
+
+ addr = 0xFF400000;
+ reg_size=REGION_4M;
+ reg_num=6;
+ attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
+ Xil_SetAttribute(addr,reg_size,reg_num, attrib);
+
+
+ addr = 0xFF800000;
+ reg_size=REGION_4M;
+ reg_num=7;
+ attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
+ Xil_SetAttribute(addr,reg_size,reg_num, attrib);
+
+ Xil_EnableBackgroundRegion();
+ Xil_EnableMPU();
+
+}
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/sbrk.c b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/sbrk.c
--- /dev/null
@@ -0,0 +1,78 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+#include <errno.h>
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) char *sbrk (int nbytes);
+}
+#endif
+
+extern char _heap_start[];
+extern char _heap_end[];
+extern char HeapBase[];
+extern char HeapLimit[];
+
+static char *heap_ptr;
+
+__attribute__((weak)) char *sbrk (int nbytes)
+{
+ char *base;
+
+ if (!heap_ptr)
+ /*heap_ptr = (char *)&_heap_start;*/
+ heap_ptr = (char *)&HeapBase;
+
+ base = heap_ptr;
+ heap_ptr += nbytes;
+
+/* if (heap_ptr <= ((char *)&_heap_end + 1))*/
+ if (heap_ptr <= ((char *)&HeapLimit + 1))
+ return base;
+
+ else
+ {
+ errno = ENOMEM;
+ return ((char *)-1);
+ }
+}
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/vectors.c b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/vectors.c
--- /dev/null
@@ -0,0 +1,179 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file vectors.c
+*
+* This file contains the C level vectors for the ARM Cortex R5 core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 pkp 02/20/14 First release
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "xil_exception.h"
+#include "vectors.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+typedef struct {
+ Xil_ExceptionHandler Handler;
+ void *Data;
+} XExc_VectorTableEntry;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+extern XExc_VectorTableEntry XExc_VectorTable[];
+
+/************************** Function Prototypes ******************************/
+
+
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the FIQ interrupt called from the vectors.s
+* file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void FIQInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_FIQ_INT].Handler(XExc_VectorTable[
+ XIL_EXCEPTION_ID_FIQ_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the IRQ interrupt called from the vectors.s
+* file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void IRQInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_IRQ_INT].Handler(XExc_VectorTable[
+ XIL_EXCEPTION_ID_IRQ_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the SW Interrupt called from the vectors.s
+* file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void SWInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_SWI_INT].Handler(XExc_VectorTable[
+ XIL_EXCEPTION_ID_SWI_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the DataAbort Interrupt called from the
+* vectors.s file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void DataAbortInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Handler(
+ XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the PrefetchAbort Interrupt called from the
+* vectors.s file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void PrefetchAbortInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Handler(
+ XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Data);
+}
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/vectors.h b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/vectors.h
--- /dev/null
@@ -0,0 +1,92 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file vectors.h
+*
+* This file contains the C level vector prototypes for the ARM Cortex R5 core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 pkp 02/20/14 First release
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _VECTORS_H_
+#define _VECTORS_H_
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+void FIQInterrupt(void);
+void IRQInterrupt(void);
+void SWInterrupt(void);
+void DataAbortInterrupt(void);
+void PrefetchAbortInterrupt(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xbasic_types.h b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xbasic_types.h
--- /dev/null
@@ -0,0 +1,130 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xbasic_types.h
+*
+*
+* @note Dummy File for backwards compatibility
+*
+
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
+#define XBASIC_TYPES_H /* by using protection macros */
+
+/** @name Legacy types
+ * Deprecated legacy types.
+ * @{
+ */
+typedef unsigned char Xuint8; /**< unsigned 8-bit */
+typedef char Xint8; /**< signed 8-bit */
+typedef unsigned short Xuint16; /**< unsigned 16-bit */
+typedef short Xint16; /**< signed 16-bit */
+typedef unsigned long Xuint32; /**< unsigned 32-bit */
+typedef long Xint32; /**< signed 32-bit */
+typedef float Xfloat32; /**< 32-bit floating point */
+typedef double Xfloat64; /**< 64-bit double precision FP */
+typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
+
+#if !defined __XUINT64__
+typedef struct
+{
+ Xuint32 Upper;
+ Xuint32 Lower;
+} Xuint64;
+#endif
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XIL_TYPES_H
+typedef Xuint32 u32;
+typedef Xuint16 u16;
+typedef Xuint8 u8;
+#endif
+#else
+#include <linux/types.h>
+#endif
+
+#ifndef TRUE
+# define TRUE 1
+#endif
+
+#ifndef FALSE
+# define FALSE 0
+#endif
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+/*
+ * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
+ * Please use NULL, TRUE and FALSE
+ */
+#define XNULL NULL
+#define XTRUE TRUE
+#define XFALSE FALSE
+
+/*
+ * This file is deprecated and users
+ * should use xil_types.h and xil_assert.h\n\r
+ */
+#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
+#warning Please refer the Standalone BSP UG647 for further details
+
+
+#endif /* end of protection macro */
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xenv.h b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xenv.h
--- /dev/null
@@ -0,0 +1,199 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv.h
+*
+* Defines common services that are typically found in a host operating.
+* environment. This include file simply includes an OS specific file based
+* on the compile-time constant BUILD_ENV_*, where * is the name of the target
+* environment.
+*
+* All services are defined as macros.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b ch 10/24/02 Added XENV_LINUX
+* 1.00a rmm 04/17/02 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XENV_H /* prevent circular inclusions */
+#define XENV_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Select which target environment we are operating under
+ */
+
+/* VxWorks target environment */
+#if defined XENV_VXWORKS
+#include "xenv_vxworks.h"
+
+/* Linux target environment */
+#elif defined XENV_LINUX
+#include "xenv_linux.h"
+
+/* Unit test environment */
+#elif defined XENV_UNITTEST
+#include "ut_xenv.h"
+
+/* Integration test environment */
+#elif defined XENV_INTTEST
+#include "int_xenv.h"
+
+/* Standalone environment selected */
+#else
+#include "xenv_standalone.h"
+#endif
+
+
+/*
+ * The following comments specify the types and macro wrappers that are
+ * expected to be defined by the target specific header files
+ */
+
+/**************************** Type Definitions *******************************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP
+ *
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param DestPtr is the destination address to copy data to.
+ * @param SrcPtr is the source address to copy data from.
+ * @param Bytes is the number of bytes to copy.
+ *
+ * @return None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param DestPtr is the destination address to set.
+ * @param Data contains the value to set.
+ * @param Bytes is the number of bytes to set.
+ *
+ * @return None
+ */
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ *
+ * Samples the processor's or external timer's time base counter.
+ *
+ * @param StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param Stamp1Ptr - First sampled time stamp.
+ * @param Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return An unsigned int value with units of microseconds.
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param Stamp1Ptr - First sampled time stamp.
+ * @param Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return An unsigned int value with units of milliseconds.
+ */
+
+/*****************************************************************************//**
+ *
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds.
+ *
+ * @param delay is the number of microseconds to delay.
+ *
+ * @return None
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xenv_standalone.h b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xenv_standalone.h
--- /dev/null
@@ -0,0 +1,378 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv_standalone.h
+*
+* Defines common services specified by xenv.h.
+*
+* @note
+* This file is not intended to be included directly by driver code.
+* Instead, the generic xenv.h file is intended to be included by driver
+* code.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr 02/28/07 Added cache handling macros.
+* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being
+* used under Xilinx standalone BSP.
+* 1.00a xd 11/03/04 Improved support for doxygen.
+* 1.00a rmm 03/21/02 First release
+* 1.00a wgr 03/22/07 Converted to new coding style.
+* 1.00a rpm 06/29/07 Added udelay macro for standalone
+* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred
+* to in MICROBLAZE section
+* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality
+*
+* </pre>
+*
+*
+******************************************************************************/
+
+#ifndef XENV_STANDALONE_H
+#define XENV_STANDALONE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+/******************************************************************************
+ *
+ * Get the processor dependent includes
+ *
+ ******************************************************************************/
+
+#include <string.h>
+
+#if defined __MICROBLAZE__
+# include "mb_interface.h"
+# include "xparameters.h" /* XPAR constants used below in MB section */
+
+#elif defined __PPC__
+# include "sleep.h"
+# include "xcache_l.h" /* also include xcache_l.h for caching macros */
+#endif
+
+/******************************************************************************
+ *
+ * MEMCPY / MEMSET related macros.
+ *
+ * The following are straight forward implementations of memset and memcpy.
+ *
+ * NOTE: memcpy may not work if source and target memory area are overlapping.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param DestPtr
+ * Destination address to copy data to.
+ *
+ * @param SrcPtr
+ * Source address to copy data from.
+ *
+ * @param Bytes
+ * Number of bytes to copy.
+ *
+ * @return None.
+ *
+ * @note
+ * The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
+ *
+ * @note
+ * This implemention MAY BREAK work if source and target memory
+ * area are overlapping.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
+ memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
+
+
+
+/*****************************************************************************/
+/**
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param DestPtr
+ * Destination address to copy data to.
+ *
+ * @param Data
+ * Value to set.
+ *
+ * @param Bytes
+ * Number of bytes to copy.
+ *
+ * @return None.
+ *
+ * @note
+ * The use of XENV_MEM_FILL is deprecated. Use memset() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
+ memset((void *) DestPtr, (int) Data, (size_t) Bytes)
+
+
+
+/******************************************************************************
+ *
+ * TIME related macros
+ *
+ ******************************************************************************/
+
+/**
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+typedef int XENV_TIME_STAMP;
+
+/*****************************************************************************/
+/**
+ *
+ * Time is derived from the 64 bit PPC timebase register
+ *
+ * @param StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return None.
+ *
+ * @note
+ *
+ * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ * <br><br>
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_GET(StampPtr)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param Stamp1Ptr is the first sampled time stamp.
+ * @param Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return 0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param Stamp1Ptr is the first sampled time stamp.
+ * @param Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return 0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
+
+/*****************************************************************************/
+/**
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds. Not implemented without OS
+ * support.
+ *
+ * @param delay
+ * Number of microseconds to delay.
+ *
+ * @return None.
+ *
+ *****************************************************************************/
+
+#ifdef __PPC__
+#define XENV_USLEEP(delay) usleep(delay)
+#define udelay(delay) usleep(delay)
+#else
+#define XENV_USLEEP(delay)
+#define udelay(delay)
+#endif
+
+
+/******************************************************************************
+ *
+ * CACHE handling macros / mappings
+ *
+ ******************************************************************************/
+/******************************************************************************
+ *
+ * Processor independent macros
+ *
+ ******************************************************************************/
+
+#define XCACHE_ENABLE_CACHE() \
+ { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
+
+#define XCACHE_DISABLE_CACHE() \
+ { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
+
+
+/******************************************************************************
+ *
+ * MicroBlaze case
+ *
+ * NOTE: Currently the following macros will only work on systems that contain
+ * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
+ * system is built using a xparameters.h file.
+ *
+ ******************************************************************************/
+
+#if defined __MICROBLAZE__
+
+/* Check if MicroBlaze data cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
+# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache()
+# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache()
+# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
+
+# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+ microblaze_invalidate_dcache_range((int)(Addr), (int)(Len))
+
+#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
+# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
+# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+ microblaze_flush_dcache_range((int)(Addr), (int)(Len))
+#else
+# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
+# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+ microblaze_invalidate_dcache_range((int)(Addr), (int)(Len))
+#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
+
+#else
+# define XCACHE_ENABLE_DCACHE()
+# define XCACHE_DISABLE_DCACHE()
+# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
+# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
+#endif /*XPAR_MICROBLAZE_USE_DCACHE*/
+
+
+/* Check if MicroBlaze instruction cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
+# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache()
+# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache()
+
+# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
+
+# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
+ microblaze_invalidate_icache_range((int)(Addr), (int)(Len))
+
+#else
+# define XCACHE_ENABLE_ICACHE()
+# define XCACHE_DISABLE_ICACHE()
+#endif /*XPAR_MICROBLAZE_USE_ICACHE*/
+
+
+/******************************************************************************
+ *
+ * PowerPC case
+ *
+ * Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
+ * specific memory region (0x80000001). Each bit (0-30) in the regions
+ * bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
+ * range.
+ *
+ * regions --> cached address range
+ * ------------|--------------------------------------------------
+ * 0x80000000 | [0, 0x7FFFFFF]
+ * 0x00000001 | [0xF8000000, 0xFFFFFFFF]
+ * 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
+ *
+ ******************************************************************************/
+
+#elif defined __PPC__
+
+#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001)
+#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache()
+#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001)
+#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
+
+#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+ XCache_InvalidateDCacheRange((unsigned int)(Addr), (unsigned)(Len))
+
+#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+ XCache_FlushDCacheRange((unsigned int)(Addr), (unsigned)(Len))
+
+#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
+
+
+/******************************************************************************
+ *
+ * Unknown processor / architecture
+ *
+ ******************************************************************************/
+
+#else
+/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef XENV_STANDALONE_H */
+
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil-crt0.S b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil-crt0.S
--- /dev/null
@@ -0,0 +1,123 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil-crt0.S
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 pkp 02/10/14 First release
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+ .file "xil-crt0.S"
+ .section ".got2","aw"
+ .align 2
+
+ .text
+.Lsbss_start:
+ .long __sbss_start
+
+.Lsbss_end:
+ .long __sbss_end
+
+.Lbss_start:
+ .long __bss_start__
+
+.Lbss_end:
+ .long __bss_end__
+
+.Lstack:
+ .long __stack
+
+
+ .globl _startup
+
+_startup:
+ bl __cpu_init /* Initialize the CPU first (BSP provides this) */
+
+ mov r0, #0
+
+ /* clear sbss */
+ ldr r1,.Lsbss_start /* calculate beginning of the SBSS */
+ ldr r2,.Lsbss_end /* calculate end of the SBSS */
+
+.Lloop_sbss:
+ cmp r1,r2
+ bge .Lenclsbss /* If no SBSS, no clearing required */
+ str r0, [r1], #4
+ b .Lloop_sbss
+
+.Lenclsbss:
+ /* clear bss */
+ ldr r1,.Lbss_start /* calculate beginning of the BSS */
+ ldr r2,.Lbss_end /* calculate end of the BSS */
+
+.Lloop_bss:
+ cmp r1,r2
+ bge .Lenclbss /* If no BSS, no clearing required */
+ str r0, [r1], #4
+ b .Lloop_bss
+
+.Lenclbss:
+
+ /* set stack pointer */
+ ldr r13,.Lstack /* stack address */
+
+ bl main /* Jump to main C code */
+
+ bl _exit
+
+.Lexit: /* should never get here */
+ b .Lexit
+
+.Lstart:
+ .size _startup,.Lstart-_startup
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil_assert.c b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil_assert.c
--- /dev/null
@@ -0,0 +1,157 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.c
+*
+* This file contains basic assert related functions for Xilinx software IP.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/14/09 Initial release
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/**
+ * This variable allows testing to be done easier with asserts. An assert
+ * sets this variable such that a driver can evaluate this variable
+ * to determine if an assert occurred.
+ */
+unsigned int Xil_AssertStatus;
+
+/**
+ * This variable allows the assert functionality to be changed for testing
+ * such that it does not wait infinitely. Use the debugger to disable the
+ * waiting during testing of asserts.
+ */
+int Xil_AssertWait = TRUE;
+
+/* The callback function to be invoked when an assert is taken */
+static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Implement assert. Currently, it calls a user-defined callback function
+* if one has been set. Then, it potentially enters an infinite loop depending
+* on the value of the Xil_AssertWait variable.
+*
+* @param file is the name of the filename of the source
+* @param line is the linenumber within File
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void Xil_Assert(const char *File, int Line)
+{
+ /* if the callback has been set then invoke it */
+ if (Xil_AssertCallbackRoutine != 0) {
+ (*Xil_AssertCallbackRoutine)(File, Line);
+ }
+
+ /* if specified, wait indefinitely such that the assert will show up
+ * in testing
+ */
+ while (Xil_AssertWait) {
+ }
+}
+
+/*****************************************************************************/
+/**
+*
+* Set up a callback function to be invoked when an assert occurs. If there
+* was already a callback installed, then it is replaced.
+*
+* @param routine is the callback to be invoked when an assert is taken
+*
+* @return None.
+*
+* @note This function has no effect if NDEBUG is set
+*
+******************************************************************************/
+void Xil_AssertSetCallback(Xil_AssertCallback Routine)
+{
+ Xil_AssertCallbackRoutine = Routine;
+}
+
+/*****************************************************************************/
+/**
+*
+* Null handler function. This follows the XInterruptHandler signature for
+* interrupt handlers. It can be used to assign a null handler (a stub) to an
+* interrupt controller vector table.
+*
+* @param NullParameter is an arbitrary void pointer and not used.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XNullHandler(void *NullParameter)
+{
+ (void) NullParameter;
+}
+
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil_assert.h b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil_assert.h
--- /dev/null
@@ -0,0 +1,198 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.h
+*
+* This file contains assert related functions.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/14/09 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_ASSERT_H /* prevent circular inclusions */
+#define XIL_ASSERT_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+
+/************************** Constant Definitions *****************************/
+
+#define XIL_ASSERT_NONE 0
+#define XIL_ASSERT_OCCURRED 1
+#define XNULL NULL
+
+extern unsigned int Xil_AssertStatus;
+extern void Xil_Assert(const char *, int);
+void XNullHandler(void *NullParameter);
+
+/**
+ * This data type defines a callback to be invoked when an
+ * assert occurs. The callback is invoked only when asserts are enabled
+ */
+typedef void (*Xil_AssertCallback) (const char *File, int Line);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#ifndef NDEBUG
+
+/*****************************************************************************/
+/**
+* This assert macro is to be used for functions that do not return anything
+* (void). This in conjunction with the Xil_AssertWait boolean can be used to
+* accomodate tests so that asserts which fail allow execution to continue.
+*
+* @param expression is the expression to evaluate. If it evaluates to
+* false, the assert occurs.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_AssertVoid(Expression) \
+{ \
+ if (Expression) { \
+ Xil_AssertStatus = XIL_ASSERT_NONE; \
+ } else { \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return; \
+ } \
+}
+
+/*****************************************************************************/
+/**
+* This assert macro is to be used for functions that do return a value. This in
+* conjunction with the Xil_AssertWait boolean can be used to accomodate tests
+* so that asserts which fail allow execution to continue.
+*
+* @param expression is the expression to evaluate. If it evaluates to false,
+* the assert occurs.
+*
+* @return Returns 0 unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_AssertNonvoid(Expression) \
+{ \
+ if (Expression) { \
+ Xil_AssertStatus = XIL_ASSERT_NONE; \
+ } else { \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return 0; \
+ } \
+}
+
+/*****************************************************************************/
+/**
+* Always assert. This assert macro is to be used for functions that do not
+* return anything (void). Use for instances where an assert should always
+* occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_AssertVoidAlways() \
+{ \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return; \
+}
+
+/*****************************************************************************/
+/**
+* Always assert. This assert macro is to be used for functions that do return
+* a value. Use for instances where an assert should always occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_AssertNonvoidAlways() \
+{ \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return 0; \
+}
+
+
+#else
+
+#define Xil_AssertVoid(Expression)
+#define Xil_AssertVoidAlways()
+#define Xil_AssertNonvoid(Expression)
+#define Xil_AssertNonvoidAlways()
+
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_AssertSetCallback(Xil_AssertCallback Routine);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil_cache.c b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil_cache.c
--- /dev/null
@@ -0,0 +1,593 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.c
+*
+* Contains required functions for the ARM cache functionality.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00 pkp 02/20/14 First release
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xil_io.h"
+#include "xpseudo_asm.h"
+#include "xparameters.h"
+#include "xreg_cortexr5.h"
+#include "xil_exception.h"
+
+
+/************************** Variable Definitions *****************************/
+
+#define IRQ_FIQ_MASK 0xC0 /* Mask IRQ and FIQ interrupts in cpsr */
+
+
+extern int _stack_end;
+extern int _stack;
+
+/****************************************************************************
+/************************** Function Prototypes ******************************/
+
+/****************************************************************************
+*
+* Enable the Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheEnable(void)
+{
+ register unsigned int CtrlReg;
+
+ /* enable caches only if they are disabled */
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+
+ if ((CtrlReg & XREG_CP15_CONTROL_C_BIT)==0) {
+ /* invalidate the Data cache */
+ Xil_DCacheInvalidate();
+
+ /* enable the Data cache */
+ CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ }
+}
+
+/****************************************************************************
+*
+* Disable the Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheDisable(void)
+{
+ register unsigned int CtrlReg;
+
+ /* clean and invalidate the Data cache */
+ Xil_DCacheFlush();
+
+ /* disable the Data cache */
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+
+ CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************
+*
+* Invalidate the entire Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheInvalidate(void)
+{
+ unsigned int currmask;
+ unsigned int stack_start,stack_end,stack_size;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+
+ stack_end = (unsigned int )&_stack_end;
+ stack_start = (unsigned int )&_stack;
+ stack_size=stack_start-stack_end;
+
+ /*Flush stack memory to save return address*/
+ Xil_DCacheFlushRange(stack_end, stack_size);
+
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+ /*invalidate all D cache*/
+ mtcp(XREG_CP15_INVAL_DC_ALL, 0);
+
+ mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Invalidate a Data cache line. If the byte specified by the address (adr)
+* is cached by the Data cache, the cacheline containing that byte is
+* invalidated. If the cacheline is modified (dirty), the modified contents
+* are lost and are NOT written to system memory before the line is
+* invalidated.
+*
+* @param Address to be flushed.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheInvalidateLine(INTPTR adr)
+{
+ unsigned int currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+ mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F)));
+
+ /* Wait for invalidate to complete */
+ dsb();
+
+ mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Invalidate the Data cache for the given address range.
+* If the bytes specified by the address (adr) are cached by the Data cache,
+* the cacheline containing that byte is invalidated. If the cacheline
+* is modified (dirty), the modified contents are lost and are NOT
+* written to system memory before the line is invalidated.
+*
+* @param Start address of range to be invalidated.
+* @param Length of range to be invalidated in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheInvalidateRange(INTPTR adr, unsigned len)
+{
+ const unsigned cacheline = 32;
+ unsigned int end;
+ unsigned int tempadr = adr;
+ unsigned int tempend;
+ unsigned int currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ if (len != 0) {
+ end = tempadr + len;
+ tempend = end;
+ /* Select L1 Data cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+ if (tempadr & (cacheline-1)) {
+ tempadr &= ~(cacheline - 1);
+
+ Xil_DCacheFlushLine(tempadr);
+ }
+ if (tempend & (cacheline-1)) {
+ tempend &= ~(cacheline - 1);
+
+ Xil_DCacheFlushLine(tempend);
+ }
+
+ while (tempadr < tempend) {
+
+ /* Invalidate Data cache line */
+ __asm__ __volatile__("mcr " \
+ XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (tempadr));
+
+ tempadr += cacheline;
+ }
+ }
+
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Flush the entire Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheFlush(void)
+{
+ register unsigned int CsidReg, C7Reg;
+ unsigned int CacheSize, LineSize, NumWays;
+ unsigned int Way, WayIndex, Set, SetIndex, NumSet;
+ unsigned int currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ /* Select cache level 0 and D cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+ CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
+
+ /* Determine Cache Size */
+
+ CacheSize = (CsidReg >> 13) & 0x1FF;
+ CacheSize +=1;
+ CacheSize *=128; /* to get number of bytes */
+
+ /* Number of Ways */
+ NumWays = (CsidReg & 0x3ff) >> 3;
+ NumWays += 1;
+
+ /* Get the cacheline size, way size, index size from csidr */
+ LineSize = (CsidReg & 0x07) + 4;
+
+ NumSet = CacheSize/NumWays;
+ NumSet /= (1 << LineSize);
+
+ Way = 0UL;
+ Set = 0UL;
+
+ /* Invalidate all the cachelines */
+ for (WayIndex =0; WayIndex < NumWays; WayIndex++) {
+ for (SetIndex =0; SetIndex < NumSet; SetIndex++) {
+ C7Reg = Way | Set;
+ /* Flush by Set/Way */
+ __asm__ __volatile__("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (C7Reg));
+
+ Set += (1 << LineSize);
+ }
+ Set = 0UL;
+ Way += 0x40000000;
+ }
+
+ /* Wait for flush to complete */
+ dsb();
+ mtcpsr(currmask);
+
+ mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Flush a Data cache line. If the byte specified by the address (adr)
+* is cached by the Data cache, the cacheline containing that byte is
+* invalidated. If the cacheline is modified (dirty), the entire
+* contents of the cacheline are written to system memory before the
+* line is invalidated.
+*
+* @param Address to be flushed.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheFlushLine(INTPTR adr)
+{
+ unsigned int currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+ mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F)));
+
+ /* Wait for flush to complete */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************
+* Flush the Data cache for the given address range.
+* If the bytes specified by the address (adr) are cached by the Data cache,
+* the cacheline containing that byte is invalidated. If the cacheline
+* is modified (dirty), the written to system memory first before the
+* before the line is invalidated.
+*
+* @param Start address of range to be flushed.
+* @param Length of range to be flushed in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheFlushRange(INTPTR adr, unsigned len)
+{
+ const unsigned cacheline = 32;
+ unsigned int end;
+ unsigned int currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ if (len != 0) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = adr + len;
+ adr &= ~(cacheline - 1);
+
+ while (adr < end) {
+ /* Flush Data cache line */
+ __asm__ __volatile__("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (adr));
+
+ adr += cacheline;
+ }
+ }
+ dsb();
+ mtcpsr(currmask);
+}
+/****************************************************************************
+*
+* Store a Data cache line. If the byte specified by the address (adr)
+* is cached by the Data cache and the cacheline is modified (dirty),
+* the entire contents of the cacheline are written to system memory.
+* After the store completes, the cacheline is marked as unmodified
+* (not dirty).
+*
+* @param Address to be stored.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheStoreLine(INTPTR adr)
+{
+ unsigned int currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+ mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1F)));
+
+ /* Wait for store to complete */
+ dsb();
+ isb();
+
+ mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Enable the instruction cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_ICacheEnable(void)
+{
+ register unsigned int CtrlReg;
+
+ /* enable caches only if they are disabled */
+
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+
+ if ((CtrlReg & XREG_CP15_CONTROL_I_BIT)==0) {
+ /* invalidate the instruction cache */
+ mtcp(XREG_CP15_INVAL_IC_POU, 0);
+
+ /* enable the instruction cache */
+ CtrlReg |= (XREG_CP15_CONTROL_I_BIT);
+
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ }
+}
+
+/****************************************************************************
+*
+* Disable the instruction cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_ICacheDisable(void)
+{
+ register unsigned int CtrlReg;
+
+ dsb();
+
+ /* invalidate the instruction cache */
+ mtcp(XREG_CP15_INVAL_IC_POU, 0);
+
+ /* disable the instruction cache */
+
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+
+ CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT);
+
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************
+*
+* Invalidate the entire instruction cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_ICacheInvalidate(void)
+{
+ unsigned int currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 1);
+
+ /* invalidate the instruction cache */
+ mtcp(XREG_CP15_INVAL_IC_POU, 0);
+
+ /* Wait for invalidate to complete */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Invalidate an instruction cache line. If the instruction specified by the
+* parameter adr is cached by the instruction cache, the cacheline containing
+* that instruction is invalidated.
+*
+* @param None.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_ICacheInvalidateLine(INTPTR adr)
+{
+ unsigned int currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 1);
+ mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1F)));
+
+ /* Wait for invalidate to complete */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Invalidate the instruction cache for the given address range.
+* If the bytes specified by the address (adr) are cached by the Data cache,
+* the cacheline containing that byte is invalidated. If the cacheline
+* is modified (dirty), the modified contents are lost and are NOT
+* written to system memory before the line is invalidated.
+*
+* @param Start address of range to be invalidated.
+* @param Length of range to be invalidated in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_ICacheInvalidateRange(INTPTR adr, unsigned len)
+{
+ const unsigned cacheline = 32;
+ unsigned int end;
+ unsigned int currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+ if (len != 0) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = adr + len;
+ adr = adr & ~(cacheline - 1);
+
+ /* Select cache L0 I-cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 1);
+
+ while (adr < end) {
+
+ /* Invalidate L1 I-cache line */
+ __asm__ __volatile__("mcr " \
+ XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (adr));
+
+ adr += cacheline;
+ }
+ }
+
+ /* Wait for invalidate to complete */
+ dsb();
+ mtcpsr(currmask);
+}
\ No newline at end of file
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil_cache.h b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil_cache.h
--- /dev/null
@@ -0,0 +1,88 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.h
+*
+* Contains required functions for the ARM cache functionality
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00 pkp 02/20/14 First release
+* </pre>
+*
+******************************************************************************/
+#ifndef XIL_CACHE_H
+#define XIL_CACHE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void Xil_DCacheEnable(void);
+void Xil_DCacheDisable(void);
+void Xil_DCacheInvalidate(void);
+void Xil_DCacheInvalidateRange(INTPTR adr, unsigned len);
+void Xil_DCacheFlush(void);
+void Xil_DCacheFlushRange(INTPTR adr, unsigned len);
+void Xil_DCacheInvalidateLine(INTPTR adr);
+void Xil_DCacheFlushLine(INTPTR adr);
+void Xil_DCacheStoreLine(INTPTR adr);
+
+void Xil_ICacheEnable(void);
+void Xil_ICacheDisable(void);
+void Xil_ICacheInvalidate(void);
+void Xil_ICacheInvalidateRange(INTPTR adr, unsigned len);
+void Xil_ICacheInvalidateLine(INTPTR adr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil_cache_vxworks.h b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil_cache_vxworks.h
--- /dev/null
@@ -0,0 +1,105 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_vxworks.h
+*
+* Contains the cache related functions for VxWorks that is wrapped by
+* xil_cache.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 12/11/09 Initial release
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_CACHE_VXWORKS_H
+#define XIL_CACHE_VXWORKS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "vxWorks.h"
+#include "vxLib.h"
+#include "sysLibExtra.h"
+#include "cacheLib.h"
+
+#if (CPU_FAMILY==PPC)
+
+#define Xil_DCacheEnable() cacheEnable(DATA_CACHE)
+
+#define Xil_DCacheDisable() cacheDisable(DATA_CACHE)
+
+#define Xil_DCacheInvalidateRange(Addr, Len) \
+ cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_DCacheFlushRange(Addr, Len) \
+ cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheInvalidateRange(Addr, Len) \
+ cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
+
+
+#else
+#error "Unknown processor / architecture. Must be PPC for VxWorks."
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil_exception.c b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil_exception.c
--- /dev/null
@@ -0,0 +1,222 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xil_exception.c
+*
+* This file contains low-level driver functions for the Cortex R5 exception
+* Handler.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 pkp 02/20/14 First release
+*
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xpseudo_asm.h"
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+typedef struct {
+ Xil_ExceptionHandler Handler;
+ void *Data;
+} XExc_VectorTableEntry;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+static void Xil_ExceptionNullHandler(void *Data);
+/************************** Variable Definitions *****************************/
+/*
+ * Exception vector table to store handlers for each exception vector.
+ */
+XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
+{
+ {Xil_ExceptionNullHandler, NULL},
+ {Xil_ExceptionNullHandler, NULL},
+ {Xil_ExceptionNullHandler, NULL},
+ {Xil_PrefetchAbortHandler, NULL},
+ {Xil_DataAbortHandler, NULL},
+ {Xil_ExceptionNullHandler, NULL},
+ {Xil_ExceptionNullHandler, NULL},
+};
+
+/*****************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* This function is a stub Handler that is the default Handler that gets called
+* if the application has not setup a Handler for a specific exception. The
+* function interface has to match the interface specified for a Handler even
+* though none of the arguments are used.
+*
+* @param Data is unused by this function.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+static void Xil_ExceptionNullHandler(void *Data)
+{
+ (void)Data;
+DieLoop: goto DieLoop;
+}
+
+/****************************************************************************/
+/**
+* The function is a common API used to initialize exception handlers across all
+* processors supported. For ARM CortexR5, the exception handlers are being
+* initialized statically and hence this function does not do anything.
+*
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void Xil_ExceptionInit(void)
+{
+ return;
+}
+
+/*****************************************************************************/
+/**
+*
+* Makes the connection between the Id of the exception source and the
+* associated Handler that is to run when the exception is recognized. The
+* argument provided in this call as the Data is used as the argument
+* for the Handler when it is called.
+*
+* @param exception_id contains the ID of the exception source and should
+* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+ See xil_exception_l.h for further information.
+* @param Handler to the Handler for that exception.
+* @param Data is a reference to Data that will be passed to the
+* Handler when it gets called.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_ExceptionRegisterHandler(u32 exception_id,
+ Xil_ExceptionHandler Handler,
+ void *Data)
+{
+ XExc_VectorTable[exception_id].Handler = Handler;
+ XExc_VectorTable[exception_id].Data = Data;
+}
+
+/*****************************************************************************/
+/**
+*
+* Removes the Handler for a specific exception Id. The stub Handler is then
+* registered for this exception Id.
+*
+* @param exception_id contains the ID of the exception source and should
+* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+* See xil_exception_l.h for further information.
+
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_ExceptionRemoveHandler(u32 exception_id)
+{
+ Xil_ExceptionRegisterHandler(exception_id,
+ Xil_ExceptionNullHandler,
+ NULL);
+}
+/*****************************************************************************/
+/**
+*
+* Default Data abort handler which prints a debug message on console if
+* Debug flag is enabled
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+
+void Xil_DataAbortHandler(void *CallBackRef){
+
+ while(1);
+}
+
+/*****************************************************************************/
+/**
+*
+* Default Prefetch abort handler which printsa debug message on console if
+* Debug flag is enabled
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_PrefetchAbortHandler(void *CallBackRef){
+
+ while(1);
+}
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil_exception.h b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil_exception.h
--- /dev/null
@@ -0,0 +1,237 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_exception.h
+*
+* This header file contains ARM Cortex R5 specific exception related APIs.
+* For exception related functions that can be used across all Xilinx supported
+* processors, please use xil_exception.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 pkp 02/20/14 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
+#define XIL_EXCEPTION_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions ****************************/
+
+#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE
+#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE
+#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
+
+#define XIL_EXCEPTION_ID_FIRST 0
+#define XIL_EXCEPTION_ID_RESET 0
+#define XIL_EXCEPTION_ID_UNDEFINED_INT 1
+#define XIL_EXCEPTION_ID_SWI_INT 2
+#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3
+#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4
+#define XIL_EXCEPTION_ID_IRQ_INT 5
+#define XIL_EXCEPTION_ID_FIQ_INT 6
+#define XIL_EXCEPTION_ID_LAST 6
+
+/*
+ * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
+ */
+#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef is the exception handler function.
+ */
+typedef void (*Xil_ExceptionHandler)(void *data);
+typedef void (*Xil_InterruptHandler)(void *data);
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Enable Exceptions.
+*
+* @param Mask for exceptions to be enabled.
+*
+* @return None.
+*
+* @note If bit is 0, exception is enabled.
+* C-Style signature: void Xil_ExceptionEnableMask(Mask);
+*
+******************************************************************************/
+#ifdef __GNUC__
+#define Xil_ExceptionEnableMask(Mask) \
+ mtcpsr(mfcpsr() & ~ (Mask & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionEnableMask(Mask) \
+ { register unsigned int Reg __asm("cpsr"); \
+ mtcpsr(Reg & ~ (Mask & XIL_EXCEPTION_ALL)) }
+#endif
+
+/****************************************************************************/
+/**
+* Enable the IRQ exception.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_ExceptionEnable() \
+ Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
+
+/****************************************************************************/
+/**
+* Disable Exceptions.
+*
+* @param Mask for exceptions to be enabled.
+*
+* @return None.
+*
+* @note If bit is 1, exception is disabled.
+* C-Style signature: Xil_ExceptionDisableMask(Mask);
+*
+******************************************************************************/
+#ifdef __GNUC__
+#define Xil_ExceptionDisableMask(Mask) \
+ mtcpsr(mfcpsr() | (Mask & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionDisableMask(Mask) \
+ { register unsigned int Reg __asm("cpsr"); \
+ mtcpsr(Reg | (Mask & XIL_EXCEPTION_ALL)) }
+#endif
+
+/****************************************************************************/
+/**
+* Disable the IRQ exception.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_ExceptionDisable() \
+ Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
+
+/****************************************************************************/
+/**
+* Enable nested interrupts by clearing the I and F bits it CPSR
+*
+* @return None.
+*
+* @note This macro is supposed to be used from interrupt handlers. In the
+* interrupt handler the interrupts are disabled by default (I and F
+* are 1). To allow nesting of interrupts, this macro should be
+* used. It clears the I and F bits by changing the ARM mode to
+* system mode. Once these bits are cleared and provided the
+* preemption of interrupt conditions are met in the GIC, nesting of
+* interrupts will start happening.
+* Caution: This macro must be used with caution. Before calling this
+* macro, the user must ensure that the source of the current IRQ
+* is appropriately cleared. Otherwise, as soon as we clear the I and
+* F bits, there can be an infinite loop of interrupts with an
+* eventual crash (all the stack space getting consumed).
+******************************************************************************/
+#define Xil_EnableNestedInterrupts() \
+ __asm__ __volatile__ ("mrs lr, spsr"); \
+ __asm__ __volatile__ ("stmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \
+ __asm__ __volatile__ ("stmfd sp!, {lr}");
+
+/****************************************************************************/
+/**
+* Disable the nested interrupts by setting the I and F bits.
+*
+* @return None.
+*
+* @note This macro is meant to be called in the interrupt service routines.
+* This macro cannot be used independently. It can only be used when
+* nesting of interrupts have been enabled by using the macro
+* Xil_EnableNestedInterrupts(). In a typical flow, the user first
+* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
+* point. The user then must call this macro before exiting the interrupt
+* service routine. This macro puts the ARM back in IRQ/FIQ mode and
+* hence sets back the I and F bits.
+******************************************************************************/
+#define Xil_DisableNestedInterrupts() \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr cpsr_c, #0x92"); \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr spsr_cxsf, lr");
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+extern void Xil_ExceptionRegisterHandler(u32 id,
+ Xil_ExceptionHandler handler,
+ void *data);
+
+extern void Xil_ExceptionRemoveHandler(u32 id);
+
+extern void Xil_ExceptionInit(void);
+
+extern void Xil_DataAbortHandler(void *CallBackRef);
+
+extern void Xil_PrefetchAbortHandler(void *CallBackRef);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_EXCEPTION_H */
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil_hal.h b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil_hal.h
--- /dev/null
@@ -0,0 +1,73 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_hal.h
+*
+* Contains all the HAL header files.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/28/09 Initial release
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_HAL_H
+#define XIL_HAL_H
+
+#include "xil_cache.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xil_types.h"
+
+#endif
+
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil_io.c b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil_io.c
--- /dev/null
@@ -0,0 +1,387 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.c
+*
+* Contains I/O functions for memory-mapped or non-memory-mapped I/O
+* architectures. These functions encapsulate Cortex R5 architecture-specific
+* I/O requirements.
+*
+* @note
+*
+* This file contains architecture-dependent code.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 pkp 02/20/14 First release
+* </pre>
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xpseudo_asm.h"
+#include "xreg_cortexr5.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for an 8-bit memory location by reading from the
+* specified address and returning the Value read from that address.
+*
+* @param Addr contains the address to perform the input operation
+* at.
+*
+* @return The Value read from the specified input address.
+*
+* @note None.
+*
+******************************************************************************/
+u8 Xil_In8(INTPTR Addr)
+{
+ return *(volatile u8 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 16-bit memory location by reading from the
+* specified address and returning the Value read from that address.
+*
+* @param Addr contains the address to perform the input operation
+* at.
+*
+* @return The Value read from the specified input address.
+*
+* @note None.
+*
+******************************************************************************/
+u16 Xil_In16(INTPTR Addr)
+{
+ return *(volatile u16 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 32-bit memory location by reading from the
+* specified address and returning the Value read from that address.
+*
+* @param Addr contains the address to perform the input operation
+* at.
+*
+* @return The Value read from the specified input address.
+*
+* @note None.
+*
+******************************************************************************/
+u32 Xil_In32(INTPTR Addr)
+{
+ return *(volatile u32 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for an 8-bit memory location by writing the
+* specified Value to the the specified address.
+*
+* @param OutAddress contains the address to perform the output operation
+* at.
+* @param Value contains the Value to be output at the specified address.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void Xil_Out8(INTPTR OutAddress, u8 Value)
+{
+ *(volatile u8 *) OutAddress = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 16-bit memory location by writing the
+* specified Value to the the specified address.
+*
+* @param OutAddress contains the address to perform the output operation
+* at.
+* @param Value contains the Value to be output at the specified address.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void Xil_Out16(INTPTR OutAddress, u16 Value)
+{
+ *(volatile u16 *) OutAddress = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 32-bit memory location by writing the
+* specified Value to the the specified address.
+*
+* @param OutAddress contains the address to perform the output operation
+* at.
+* @param Value contains the Value to be output at the specified address.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void Xil_Out32(INTPTR OutAddress, u32 Value)
+{
+ *(volatile u32 *) OutAddress = Value;
+}
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 64-bit memory location by writing the
+* specified Value to the the specified address.
+*
+* @param OutAddress contains the address to perform the output operation
+* at.
+* @param Value contains the Value to be output at the specified address.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void Xil_Out64(INTPTR OutAddress, u64 Value)
+{
+ *(volatile u64 *) OutAddress = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 64-bit memory location by reading the
+* specified Value to the the specified address.
+*
+* @param OutAddress contains the address to perform the output operation
+* at.
+* @param Value contains the Value to be output at the specified address.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+u64 Xil_In64(INTPTR Addr)
+{
+ return *(volatile u64 *) Addr;
+}
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 16-bit memory location by reading from the
+* specified address and returning the byte-swapped Value read from that
+* address.
+*
+* @param Addr contains the address to perform the input operation
+* at.
+*
+* @return The byte-swapped Value read from the specified input address.
+*
+* @note None.
+*
+******************************************************************************/
+u16 Xil_In16BE(INTPTR Addr)
+{
+ u16 temp;
+ u16 result;
+
+ temp = Xil_In16(Addr);
+
+ result = Xil_EndianSwap16(temp);
+
+ return result;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 32-bit memory location by reading from the
+* specified address and returning the byte-swapped Value read from that
+* address.
+*
+* @param Addr contains the address to perform the input operation
+* at.
+*
+* @return The byte-swapped Value read from the specified input address.
+*
+* @note None.
+*
+******************************************************************************/
+u32 Xil_In32BE(INTPTR Addr)
+{
+ u32 temp;
+ u32 result;
+
+ temp = Xil_In32(Addr);
+
+ result = Xil_EndianSwap32(temp);
+
+ return result;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 16-bit memory location by writing the
+* specified Value to the the specified address. The Value is byte-swapped
+* before being written.
+*
+* @param OutAddress contains the address to perform the output operation
+* at.
+* @param Value contains the Value to be output at the specified address.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void Xil_Out16BE(INTPTR OutAddress, u16 Value)
+{
+ u16 temp;
+
+ temp = Xil_EndianSwap16(Value);
+
+ Xil_Out16(OutAddress, temp);
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 32-bit memory location by writing the
+* specified Value to the the specified address. The Value is byte-swapped
+* before being written.
+*
+* @param OutAddress contains the address to perform the output operation
+* at.
+* @param Value contains the Value to be output at the specified address.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void Xil_Out32BE(INTPTR OutAddress, u32 Value)
+{
+ u32 temp;
+
+ temp = Xil_EndianSwap32(Value);
+
+ Xil_Out32(OutAddress, temp);
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a 16-bit endian converion.
+*
+* @param Data contains the value to be converted.
+*
+* @return converted value.
+*
+* @note None.
+*
+******************************************************************************/
+u16 Xil_EndianSwap16(u16 Data)
+{
+ return (u16) (((Data & 0xFF00) >> 8) | ((Data & 0x00FF) << 8));
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a 32-bit endian converion.
+*
+* @param Data contains the value to be converted.
+*
+* @return converted value.
+*
+* @note None.
+*
+******************************************************************************/
+u32 Xil_EndianSwap32(u32 Data)
+{
+ u16 LoWord;
+ u16 HiWord;
+
+ /* get each of the half words from the 32 bit word */
+
+ LoWord = (u16) (Data & 0x0000FFFF);
+ HiWord = (u16) ((Data & 0xFFFF0000) >> 16);
+
+ /* byte swap each of the 16 bit half words */
+
+ LoWord = (((LoWord & 0xFF00) >> 8) | ((LoWord & 0x00FF) << 8));
+ HiWord = (((HiWord & 0xFF00) >> 8) | ((HiWord & 0x00FF) << 8));
+
+ /* swap the half words before returning the value */
+
+ return (u32) ((LoWord << 16) | HiWord);
+}
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil_io.h b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil_io.h
--- /dev/null
@@ -0,0 +1,254 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.h
+*
+* This file contains the interface for the general IO component, which
+* encapsulates the Input/Output functions for processors that do not
+* require any special I/O handling.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 pkp 02/20/14 First release
+* </pre>
+******************************************************************************/
+
+#ifndef XIL_IO_H /* prevent circular inclusions */
+#define XIL_IO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#if defined __GNUC__
+# define SYNCHRONIZE_IO dmb()
+# define INST_SYNC isb()
+# define DATA_SYNC dsb()
+#else
+# define SYNCHRONIZE_IO
+# define INST_SYNC
+# define DATA_SYNC
+#endif /* __GNUC__ */
+
+/*****************************************************************************/
+/**
+*
+* Perform an big-endian input operation for a 16-bit memory location
+* by reading from the specified address and returning the Value read from
+* that address.
+*
+* @param Addr contains the address to perform the input operation at.
+*
+* @return The Value read from the specified input address with the
+* proper endianness. The return Value has the same endianness
+* as that of the processor, i.e. if the processor is
+* little-engian, the return Value is the byte-swapped Value read
+* from the address.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_In16LE(Addr) Xil_In16(Addr)
+
+/*****************************************************************************/
+/**
+*
+* Perform a big-endian input operation for a 32-bit memory location
+* by reading from the specified address and returning the Value read from
+* that address.
+*
+* @param Addr contains the address to perform the input operation at.
+*
+* @return The Value read from the specified input address with the
+* proper endianness. The return Value has the same endianness
+* as that of the processor, i.e. if the processor is
+* little-engian, the return Value is the byte-swapped Value read
+* from the address.
+*
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_In32LE(Addr) Xil_In32(Addr)
+
+/*****************************************************************************/
+/**
+*
+* Perform a big-endian output operation for a 16-bit memory location
+* by writing the specified Value to the specified address.
+*
+* @param Addr contains the address to perform the output operation at.
+* @param Value contains the Value to be output at the specified address.
+* The Value has the same endianness as that of the processor.
+* If the processor is little-endian, the byte-swapped Value is
+* written to the address.
+*
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_Out16LE(Addr, Value) Xil_Out16(Addr, Value)
+
+/*****************************************************************************/
+/**
+*
+* Perform a big-endian output operation for a 32-bit memory location
+* by writing the specified Value to the specified address.
+*
+* @param Addr contains the address to perform the output operation at.
+* @param Value contains the Value to be output at the specified address.
+* The Value has the same endianness as that of the processor.
+* If the processor is little-endian, the byte-swapped Value is
+* written to the address.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_Out32LE(Addr, Value) Xil_Out32(Addr, Value)
+
+/*****************************************************************************/
+/**
+*
+* Convert a 32-bit number from host byte order to network byte order.
+*
+* @param Data the 32-bit number to be converted.
+*
+* @return The converted 32-bit number in network byte order.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_Htonl(Data) Xil_EndianSwap32(Data)
+
+/*****************************************************************************/
+/**
+*
+* Convert a 16-bit number from host byte order to network byte order.
+*
+* @param Data the 16-bit number to be converted.
+*
+* @return The converted 16-bit number in network byte order.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_Htons(Data) Xil_EndianSwap16(Data)
+
+/*****************************************************************************/
+/**
+*
+* Convert a 32-bit number from network byte order to host byte order.
+*
+* @param Data the 32-bit number to be converted.
+*
+* @return The converted 32-bit number in host byte order.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_Ntohl(Data) Xil_EndianSwap32(Data)
+
+/*****************************************************************************/
+/**
+*
+* Convert a 16-bit number from network byte order to host byte order.
+*
+* @param Data the 16-bit number to be converted.
+*
+* @return The converted 16-bit number in host byte order.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_Ntohs(Data) Xil_EndianSwap16(Data)
+
+/************************** Function Prototypes ******************************/
+
+/* The following functions allow the software to be transportable across
+ * processors which may use memory mapped I/O or I/O which is mapped into a
+ * seperate address space.
+ */
+u8 Xil_In8(INTPTR Addr);
+u16 Xil_In16(INTPTR Addr);
+u32 Xil_In32(INTPTR Addr);
+u64 Xil_In64(INTPTR Addr);
+
+void Xil_Out8(INTPTR Addr, u8 Value);
+void Xil_Out16(INTPTR Addr, u16 Value);
+void Xil_Out32(INTPTR Addr, u32 Value);
+void Xil_Out64(INTPTR Addr, u64 Value);
+
+u16 Xil_In16BE(INTPTR Addr);
+u32 Xil_In32BE(INTPTR Addr);
+void Xil_Out16BE(INTPTR Addr, u16 Value);
+void Xil_Out32BE(INTPTR Addr, u32 Value);
+
+u16 Xil_EndianSwap16(u16 Data);
+u32 Xil_EndianSwap32(u32 Data);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil_macroback.h b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil_macroback.h
--- /dev/null
@@ -0,0 +1,1063 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+/*********************************************************************/
+/**
+ * @file xil_macroback.h
+ *
+ * This header file is meant to bring back the removed _m macros.
+ * This header file must be included last.
+ * The following macros are not defined here due to the driver change:
+ * XGpio_mSetDataDirection
+ * XGpio_mGetDataReg
+ * XGpio_mSetDataReg
+ * XIIC_RESET
+ * XIIC_CLEAR_STATS
+ * XSpi_mReset
+ * XSysAce_mSetCfgAddr
+ * XSysAce_mIsCfgDone
+ * XTft_mSetPixel
+ * XTft_mGetPixel
+ * XWdtTb_mEnableWdt
+ * XWdtTb_mDisbleWdt
+ * XWdtTb_mRestartWdt
+ * XWdtTb_mGetTimebaseReg
+ * XWdtTb_mHasReset
+ *
+ * Please refer the corresonding driver document for replacement.
+ *
+ *********************************************************************/
+
+#ifndef XIL_MACROBACK_H
+#define XIL_MACROBACK_H
+
+/*********************************************************************/
+/**
+ * Macros for Driver XCan
+ *
+ *********************************************************************/
+#ifndef XCan_mReadReg
+#define XCan_mReadReg XCan_ReadReg
+#endif
+
+#ifndef XCan_mWriteReg
+#define XCan_mWriteReg XCan_WriteReg
+#endif
+
+#ifndef XCan_mIsTxDone
+#define XCan_mIsTxDone XCan_IsTxDone
+#endif
+
+#ifndef XCan_mIsTxFifoFull
+#define XCan_mIsTxFifoFull XCan_IsTxFifoFull
+#endif
+
+#ifndef XCan_mIsHighPriorityBufFull
+#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull
+#endif
+
+#ifndef XCan_mIsRxEmpty
+#define XCan_mIsRxEmpty XCan_IsRxEmpty
+#endif
+
+#ifndef XCan_mIsAcceptFilterBusy
+#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy
+#endif
+
+#ifndef XCan_mCreateIdValue
+#define XCan_mCreateIdValue XCan_CreateIdValue
+#endif
+
+#ifndef XCan_mCreateDlcValue
+#define XCan_mCreateDlcValue XCan_CreateDlcValue
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDmaCentral
+ *
+ *********************************************************************/
+#ifndef XDmaCentral_mWriteReg
+#define XDmaCentral_mWriteReg XDmaCentral_WriteReg
+#endif
+
+#ifndef XDmaCentral_mReadReg
+#define XDmaCentral_mReadReg XDmaCentral_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsAdc
+ *
+ *********************************************************************/
+#ifndef XDsAdc_mWriteReg
+#define XDsAdc_mWriteReg XDsAdc_WriteReg
+#endif
+
+#ifndef XDsAdc_mReadReg
+#define XDsAdc_mReadReg XDsAdc_ReadReg
+#endif
+
+#ifndef XDsAdc_mIsEmpty
+#define XDsAdc_mIsEmpty XDsAdc_IsEmpty
+#endif
+
+#ifndef XDsAdc_mSetFstmReg
+#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg
+#endif
+
+#ifndef XDsAdc_mGetFstmReg
+#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg
+#endif
+
+#ifndef XDsAdc_mEnableConversion
+#define XDsAdc_mEnableConversion XDsAdc_EnableConversion
+#endif
+
+#ifndef XDsAdc_mDisableConversion
+#define XDsAdc_mDisableConversion XDsAdc_DisableConversion
+#endif
+
+#ifndef XDsAdc_mGetFifoOccyReg
+#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsDac
+ *
+ *********************************************************************/
+#ifndef XDsDac_mWriteReg
+#define XDsDac_mWriteReg XDsDac_WriteReg
+#endif
+
+#ifndef XDsDac_mReadReg
+#define XDsDac_mReadReg XDsDac_ReadReg
+#endif
+
+#ifndef XDsDac_mIsEmpty
+#define XDsDac_mIsEmpty XDsDac_IsEmpty
+#endif
+
+#ifndef XDsDac_mFifoIsFull
+#define XDsDac_mFifoIsFull XDsDac_FifoIsFull
+#endif
+
+#ifndef XDsDac_mGetVacancy
+#define XDsDac_mGetVacancy XDsDac_GetVacancy
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XEmacLite
+ *
+ *********************************************************************/
+#ifndef XEmacLite_mReadReg
+#define XEmacLite_mReadReg XEmacLite_ReadReg
+#endif
+
+#ifndef XEmacLite_mWriteReg
+#define XEmacLite_mWriteReg XEmacLite_WriteReg
+#endif
+
+#ifndef XEmacLite_mGetTxStatus
+#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus
+#endif
+
+#ifndef XEmacLite_mSetTxStatus
+#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus
+#endif
+
+#ifndef XEmacLite_mGetRxStatus
+#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus
+#endif
+
+#ifndef XEmacLite_mSetRxStatus
+#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus
+#endif
+
+#ifndef XEmacLite_mIsTxDone
+#define XEmacLite_mIsTxDone XEmacLite_IsTxDone
+#endif
+
+#ifndef XEmacLite_mIsRxEmpty
+#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty
+#endif
+
+#ifndef XEmacLite_mNextTransmitAddr
+#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr
+#endif
+
+#ifndef XEmacLite_mNextReceiveAddr
+#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr
+#endif
+
+#ifndef XEmacLite_mIsMdioConfigured
+#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured
+#endif
+
+#ifndef XEmacLite_mIsLoopbackConfigured
+#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured
+#endif
+
+#ifndef XEmacLite_mGetReceiveDataLength
+#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength
+#endif
+
+#ifndef XEmacLite_mGetTxActive
+#define XEmacLite_mGetTxActive XEmacLite_GetTxActive
+#endif
+
+#ifndef XEmacLite_mSetTxActive
+#define XEmacLite_mSetTxActive XEmacLite_SetTxActive
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XGpio
+ *
+ *********************************************************************/
+#ifndef XGpio_mWriteReg
+#define XGpio_mWriteReg XGpio_WriteReg
+#endif
+
+#ifndef XGpio_mReadReg
+#define XGpio_mReadReg XGpio_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XHwIcap
+ *
+ *********************************************************************/
+#ifndef XHwIcap_mFifoWrite
+#define XHwIcap_mFifoWrite XHwIcap_FifoWrite
+#endif
+
+#ifndef XHwIcap_mFifoRead
+#define XHwIcap_mFifoRead XHwIcap_FifoRead
+#endif
+
+#ifndef XHwIcap_mSetSizeReg
+#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg
+#endif
+
+#ifndef XHwIcap_mGetControlReg
+#define XHwIcap_mGetControlReg XHwIcap_GetControlReg
+#endif
+
+#ifndef XHwIcap_mStartConfig
+#define XHwIcap_mStartConfig XHwIcap_StartConfig
+#endif
+
+#ifndef XHwIcap_mStartReadBack
+#define XHwIcap_mStartReadBack XHwIcap_StartReadBack
+#endif
+
+#ifndef XHwIcap_mGetStatusReg
+#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg
+#endif
+
+#ifndef XHwIcap_mIsTransferDone
+#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone
+#endif
+
+#ifndef XHwIcap_mIsDeviceBusy
+#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy
+#endif
+
+#ifndef XHwIcap_mIntrGlobalEnable
+#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable
+#endif
+
+#ifndef XHwIcap_mIntrGlobalDisable
+#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable
+#endif
+
+#ifndef XHwIcap_mIntrGetStatus
+#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus
+#endif
+
+#ifndef XHwIcap_mIntrDisable
+#define XHwIcap_mIntrDisable XHwIcap_IntrDisable
+#endif
+
+#ifndef XHwIcap_mIntrEnable
+#define XHwIcap_mIntrEnable XHwIcap_IntrEnable
+#endif
+
+#ifndef XHwIcap_mIntrGetEnabled
+#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled
+#endif
+
+#ifndef XHwIcap_mIntrClear
+#define XHwIcap_mIntrClear XHwIcap_IntrClear
+#endif
+
+#ifndef XHwIcap_mGetWrFifoVacancy
+#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy
+#endif
+
+#ifndef XHwIcap_mGetRdFifoOccupancy
+#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy
+#endif
+
+#ifndef XHwIcap_mSliceX2Col
+#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col
+#endif
+
+#ifndef XHwIcap_mSliceY2Row
+#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row
+#endif
+
+#ifndef XHwIcap_mSliceXY2Slice
+#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice
+#endif
+
+#ifndef XHwIcap_mReadReg
+#define XHwIcap_mReadReg XHwIcap_ReadReg
+#endif
+
+#ifndef XHwIcap_mWriteReg
+#define XHwIcap_mWriteReg XHwIcap_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIic
+ *
+ *********************************************************************/
+#ifndef XIic_mReadReg
+#define XIic_mReadReg XIic_ReadReg
+#endif
+
+#ifndef XIic_mWriteReg
+#define XIic_mWriteReg XIic_WriteReg
+#endif
+
+#ifndef XIic_mEnterCriticalRegion
+#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIic_mExitCriticalRegion
+#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_GINTR_DISABLE
+#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIIC_GINTR_ENABLE
+#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_IS_GINTR_ENABLED
+#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled
+#endif
+
+#ifndef XIIC_WRITE_IISR
+#define XIIC_WRITE_IISR XIic_WriteIisr
+#endif
+
+#ifndef XIIC_READ_IISR
+#define XIIC_READ_IISR XIic_ReadIisr
+#endif
+
+#ifndef XIIC_WRITE_IIER
+#define XIIC_WRITE_IIER XIic_WriteIier
+#endif
+
+#ifndef XIic_mClearIisr
+#define XIic_mClearIisr XIic_ClearIisr
+#endif
+
+#ifndef XIic_mSend7BitAddress
+#define XIic_mSend7BitAddress XIic_Send7BitAddress
+#endif
+
+#ifndef XIic_mDynSend7BitAddress
+#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress
+#endif
+
+#ifndef XIic_mDynSendStartStopAddress
+#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress
+#endif
+
+#ifndef XIic_mDynSendStop
+#define XIic_mDynSendStop XIic_DynSendStop
+#endif
+
+#ifndef XIic_mSend10BitAddrByte1
+#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1
+#endif
+
+#ifndef XIic_mSend10BitAddrByte2
+#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2
+#endif
+
+#ifndef XIic_mSend7BitAddr
+#define XIic_mSend7BitAddr XIic_Send7BitAddr
+#endif
+
+#ifndef XIic_mDisableIntr
+#define XIic_mDisableIntr XIic_DisableIntr
+#endif
+
+#ifndef XIic_mEnableIntr
+#define XIic_mEnableIntr XIic_EnableIntr
+#endif
+
+#ifndef XIic_mClearIntr
+#define XIic_mClearIntr XIic_ClearIntr
+#endif
+
+#ifndef XIic_mClearEnableIntr
+#define XIic_mClearEnableIntr XIic_ClearEnableIntr
+#endif
+
+#ifndef XIic_mFlushRxFifo
+#define XIic_mFlushRxFifo XIic_FlushRxFifo
+#endif
+
+#ifndef XIic_mFlushTxFifo
+#define XIic_mFlushTxFifo XIic_FlushTxFifo
+#endif
+
+#ifndef XIic_mReadRecvByte
+#define XIic_mReadRecvByte XIic_ReadRecvByte
+#endif
+
+#ifndef XIic_mWriteSendByte
+#define XIic_mWriteSendByte XIic_WriteSendByte
+#endif
+
+#ifndef XIic_mSetControlRegister
+#define XIic_mSetControlRegister XIic_SetControlRegister
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIntc
+ *
+ *********************************************************************/
+#ifndef XIntc_mMasterEnable
+#define XIntc_mMasterEnable XIntc_MasterEnable
+#endif
+
+#ifndef XIntc_mMasterDisable
+#define XIntc_mMasterDisable XIntc_MasterDisable
+#endif
+
+#ifndef XIntc_mEnableIntr
+#define XIntc_mEnableIntr XIntc_EnableIntr
+#endif
+
+#ifndef XIntc_mDisableIntr
+#define XIntc_mDisableIntr XIntc_DisableIntr
+#endif
+
+#ifndef XIntc_mAckIntr
+#define XIntc_mAckIntr XIntc_AckIntr
+#endif
+
+#ifndef XIntc_mGetIntrStatus
+#define XIntc_mGetIntrStatus XIntc_GetIntrStatus
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XLlDma
+ *
+ *********************************************************************/
+#ifndef XLlDma_mBdRead
+#define XLlDma_mBdRead XLlDma_BdRead
+#endif
+
+#ifndef XLlDma_mBdWrite
+#define XLlDma_mBdWrite XLlDma_BdWrite
+#endif
+
+#ifndef XLlDma_mWriteReg
+#define XLlDma_mWriteReg XLlDma_WriteReg
+#endif
+
+#ifndef XLlDma_mReadReg
+#define XLlDma_mReadReg XLlDma_ReadReg
+#endif
+
+#ifndef XLlDma_mBdClear
+#define XLlDma_mBdClear XLlDma_BdClear
+#endif
+
+#ifndef XLlDma_mBdSetStsCtrl
+#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdGetStsCtrl
+#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdSetLength
+#define XLlDma_mBdSetLength XLlDma_BdSetLength
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mBdSetId
+#define XLlDma_mBdSetId XLlDma_BdSetId
+#endif
+
+#ifndef XLlDma_mBdGetId
+#define XLlDma_mBdGetId XLlDma_BdGetId
+#endif
+
+#ifndef XLlDma_mBdSetBufAddr
+#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetBufAddr
+#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mGetTxRing
+#define XLlDma_mGetTxRing XLlDma_GetTxRing
+#endif
+
+#ifndef XLlDma_mGetRxRing
+#define XLlDma_mGetRxRing XLlDma_GetRxRing
+#endif
+
+#ifndef XLlDma_mGetCr
+#define XLlDma_mGetCr XLlDma_GetCr
+#endif
+
+#ifndef XLlDma_mSetCr
+#define XLlDma_mSetCr XLlDma_SetCr
+#endif
+
+#ifndef XLlDma_mBdRingCntCalc
+#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc
+#endif
+
+#ifndef XLlDma_mBdRingMemCalc
+#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc
+#endif
+
+#ifndef XLlDma_mBdRingGetCnt
+#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt
+#endif
+
+#ifndef XLlDma_mBdRingGetFreeCnt
+#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt
+#endif
+
+#ifndef XLlDma_mBdRingSnapShotCurrBd
+#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd
+#endif
+
+#ifndef XLlDma_mBdRingNext
+#define XLlDma_mBdRingNext XLlDma_BdRingNext
+#endif
+
+#ifndef XLlDma_mBdRingPrev
+#define XLlDma_mBdRingPrev XLlDma_BdRingPrev
+#endif
+
+#ifndef XLlDma_mBdRingGetSr
+#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr
+#endif
+
+#ifndef XLlDma_mBdRingSetSr
+#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr
+#endif
+
+#ifndef XLlDma_mBdRingGetCr
+#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr
+#endif
+
+#ifndef XLlDma_mBdRingSetCr
+#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr
+#endif
+
+#ifndef XLlDma_mBdRingBusy
+#define XLlDma_mBdRingBusy XLlDma_BdRingBusy
+#endif
+
+#ifndef XLlDma_mBdRingIntEnable
+#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable
+#endif
+
+#ifndef XLlDma_mBdRingIntDisable
+#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable
+#endif
+
+#ifndef XLlDma_mBdRingIntGetEnabled
+#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled
+#endif
+
+#ifndef XLlDma_mBdRingGetIrq
+#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq
+#endif
+
+#ifndef XLlDma_mBdRingAckIrq
+#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMbox
+ *
+ *********************************************************************/
+#ifndef XMbox_mWriteReg
+#define XMbox_mWriteReg XMbox_WriteReg
+#endif
+
+#ifndef XMbox_mReadReg
+#define XMbox_mReadReg XMbox_ReadReg
+#endif
+
+#ifndef XMbox_mWriteMBox
+#define XMbox_mWriteMBox XMbox_WriteMBox
+#endif
+
+#ifndef XMbox_mReadMBox
+#define XMbox_mReadMBox XMbox_ReadMBox
+#endif
+
+#ifndef XMbox_mFSLReadMBox
+#define XMbox_mFSLReadMBox XMbox_FSLReadMBox
+#endif
+
+#ifndef XMbox_mFSLWriteMBox
+#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox
+#endif
+
+#ifndef XMbox_mFSLIsEmpty
+#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty
+#endif
+
+#ifndef XMbox_mFSLIsFull
+#define XMbox_mFSLIsFull XMbox_FSLIsFull
+#endif
+
+#ifndef XMbox_mIsEmpty
+#define XMbox_mIsEmpty XMbox_IsEmptyHw
+#endif
+
+#ifndef XMbox_mIsFull
+#define XMbox_mIsFull XMbox_IsFullHw
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMpmc
+ *
+ *********************************************************************/
+#ifndef XMpmc_mReadReg
+#define XMpmc_mReadReg XMpmc_ReadReg
+#endif
+
+#ifndef XMpmc_mWriteReg
+#define XMpmc_mWriteReg XMpmc_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMutex
+ *
+ *********************************************************************/
+#ifndef XMutex_mWriteReg
+#define XMutex_mWriteReg XMutex_WriteReg
+#endif
+
+#ifndef XMutex_mReadReg
+#define XMutex_mReadReg XMutex_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XPcie
+ *
+ *********************************************************************/
+#ifndef XPcie_mReadReg
+#define XPcie_mReadReg XPcie_ReadReg
+#endif
+
+#ifndef XPcie_mWriteReg
+#define XPcie_mWriteReg XPcie_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSpi
+ *
+ *********************************************************************/
+#ifndef XSpi_mIntrGlobalEnable
+#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable
+#endif
+
+#ifndef XSpi_mIntrGlobalDisable
+#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable
+#endif
+
+#ifndef XSpi_mIsIntrGlobalEnabled
+#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled
+#endif
+
+#ifndef XSpi_mIntrGetStatus
+#define XSpi_mIntrGetStatus XSpi_IntrGetStatus
+#endif
+
+#ifndef XSpi_mIntrClear
+#define XSpi_mIntrClear XSpi_IntrClear
+#endif
+
+#ifndef XSpi_mIntrEnable
+#define XSpi_mIntrEnable XSpi_IntrEnable
+#endif
+
+#ifndef XSpi_mIntrDisable
+#define XSpi_mIntrDisable XSpi_IntrDisable
+#endif
+
+#ifndef XSpi_mIntrGetEnabled
+#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled
+#endif
+
+#ifndef XSpi_mSetControlReg
+#define XSpi_mSetControlReg XSpi_SetControlReg
+#endif
+
+#ifndef XSpi_mGetControlReg
+#define XSpi_mGetControlReg XSpi_GetControlReg
+#endif
+
+#ifndef XSpi_mGetStatusReg
+#define XSpi_mGetStatusReg XSpi_GetStatusReg
+#endif
+
+#ifndef XSpi_mSetSlaveSelectReg
+#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mGetSlaveSelectReg
+#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mEnable
+#define XSpi_mEnable XSpi_Enable
+#endif
+
+#ifndef XSpi_mDisable
+#define XSpi_mDisable XSpi_Disable
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysAce
+ *
+ *********************************************************************/
+#ifndef XSysAce_mGetControlReg
+#define XSysAce_mGetControlReg XSysAce_GetControlReg
+#endif
+
+#ifndef XSysAce_mSetControlReg
+#define XSysAce_mSetControlReg XSysAce_SetControlReg
+#endif
+
+#ifndef XSysAce_mOrControlReg
+#define XSysAce_mOrControlReg XSysAce_OrControlReg
+#endif
+
+#ifndef XSysAce_mAndControlReg
+#define XSysAce_mAndControlReg XSysAce_AndControlReg
+#endif
+
+#ifndef XSysAce_mGetErrorReg
+#define XSysAce_mGetErrorReg XSysAce_GetErrorReg
+#endif
+
+#ifndef XSysAce_mGetStatusReg
+#define XSysAce_mGetStatusReg XSysAce_GetStatusReg
+#endif
+
+#ifndef XSysAce_mWaitForLock
+#define XSysAce_mWaitForLock XSysAce_WaitForLock
+#endif
+
+#ifndef XSysAce_mEnableIntr
+#define XSysAce_mEnableIntr XSysAce_EnableIntr
+#endif
+
+#ifndef XSysAce_mDisableIntr
+#define XSysAce_mDisableIntr XSysAce_DisableIntr
+#endif
+
+#ifndef XSysAce_mIsReadyForCmd
+#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd
+#endif
+
+#ifndef XSysAce_mIsMpuLocked
+#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked
+#endif
+
+#ifndef XSysAce_mIsIntrEnabled
+#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysMon
+ *
+ *********************************************************************/
+#ifndef XSysMon_mIsEventSamplingModeSet
+#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet
+#endif
+
+#ifndef XSysMon_mIsDrpBusy
+#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy
+#endif
+
+#ifndef XSysMon_mIsDrpLocked
+#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked
+#endif
+
+#ifndef XSysMon_mRawToTemperature
+#define XSysMon_mRawToTemperature XSysMon_RawToTemperature
+#endif
+
+#ifndef XSysMon_mRawToVoltage
+#define XSysMon_mRawToVoltage XSysMon_RawToVoltage
+#endif
+
+#ifndef XSysMon_mTemperatureToRaw
+#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw
+#endif
+
+#ifndef XSysMon_mVoltageToRaw
+#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw
+#endif
+
+#ifndef XSysMon_mReadReg
+#define XSysMon_mReadReg XSysMon_ReadReg
+#endif
+
+#ifndef XSysMon_mWriteReg
+#define XSysMon_mWriteReg XSysMon_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XTmrCtr
+ *
+ *********************************************************************/
+#ifndef XTimerCtr_mReadReg
+#define XTimerCtr_mReadReg XTimerCtr_ReadReg
+#endif
+
+#ifndef XTmrCtr_mWriteReg
+#define XTmrCtr_mWriteReg XTmrCtr_WriteReg
+#endif
+
+#ifndef XTmrCtr_mSetControlStatusReg
+#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetControlStatusReg
+#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetTimerCounterReg
+#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mSetLoadReg
+#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg
+#endif
+
+#ifndef XTmrCtr_mGetLoadReg
+#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg
+#endif
+
+#ifndef XTmrCtr_mEnable
+#define XTmrCtr_mEnable XTmrCtr_Enable
+#endif
+
+#ifndef XTmrCtr_mDisable
+#define XTmrCtr_mDisable XTmrCtr_Disable
+#endif
+
+#ifndef XTmrCtr_mEnableIntr
+#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr
+#endif
+
+#ifndef XTmrCtr_mDisableIntr
+#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr
+#endif
+
+#ifndef XTmrCtr_mLoadTimerCounterReg
+#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mHasEventOccurred
+#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartLite
+ *
+ *********************************************************************/
+#ifndef XUartLite_mUpdateStats
+#define XUartLite_mUpdateStats XUartLite_UpdateStats
+#endif
+
+#ifndef XUartLite_mWriteReg
+#define XUartLite_mWriteReg XUartLite_WriteReg
+#endif
+
+#ifndef XUartLite_mReadReg
+#define XUartLite_mReadReg XUartLite_ReadReg
+#endif
+
+#ifndef XUartLite_mClearStats
+#define XUartLite_mClearStats XUartLite_ClearStats
+#endif
+
+#ifndef XUartLite_mSetControlReg
+#define XUartLite_mSetControlReg XUartLite_SetControlReg
+#endif
+
+#ifndef XUartLite_mGetStatusReg
+#define XUartLite_mGetStatusReg XUartLite_GetStatusReg
+#endif
+
+#ifndef XUartLite_mIsReceiveEmpty
+#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty
+#endif
+
+#ifndef XUartLite_mIsTransmitFull
+#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull
+#endif
+
+#ifndef XUartLite_mIsIntrEnabled
+#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled
+#endif
+
+#ifndef XUartLite_mEnableIntr
+#define XUartLite_mEnableIntr XUartLite_EnableIntr
+#endif
+
+#ifndef XUartLite_mDisableIntr
+#define XUartLite_mDisableIntr XUartLite_DisableIntr
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartNs550
+ *
+ *********************************************************************/
+#ifndef XUartNs550_mUpdateStats
+#define XUartNs550_mUpdateStats XUartNs550_UpdateStats
+#endif
+
+#ifndef XUartNs550_mReadReg
+#define XUartNs550_mReadReg XUartNs550_ReadReg
+#endif
+
+#ifndef XUartNs550_mWriteReg
+#define XUartNs550_mWriteReg XUartNs550_WriteReg
+#endif
+
+#ifndef XUartNs550_mClearStats
+#define XUartNs550_mClearStats XUartNs550_ClearStats
+#endif
+
+#ifndef XUartNs550_mGetLineStatusReg
+#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg
+#endif
+
+#ifndef XUartNs550_mGetLineControlReg
+#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg
+#endif
+
+#ifndef XUartNs550_mSetLineControlReg
+#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg
+#endif
+
+#ifndef XUartNs550_mEnableIntr
+#define XUartNs550_mEnableIntr XUartNs550_EnableIntr
+#endif
+
+#ifndef XUartNs550_mDisableIntr
+#define XUartNs550_mDisableIntr XUartNs550_DisableIntr
+#endif
+
+#ifndef XUartNs550_mIsReceiveData
+#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData
+#endif
+
+#ifndef XUartNs550_mIsTransmitEmpty
+#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUsb
+ *
+ *********************************************************************/
+#ifndef XUsb_mReadReg
+#define XUsb_mReadReg XUsb_ReadReg
+#endif
+
+#ifndef XUsb_mWriteReg
+#define XUsb_mWriteReg XUsb_WriteReg
+#endif
+
+#endif
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil_mpu.c b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil_mpu.c
--- /dev/null
@@ -0,0 +1,433 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.c
+*
+* This file provides APIs for enabling/disabling MMU and setting the memory
+* attributes for sections, in the MMU translation table.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 pkp 02/10/14 Initial version
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+#include "xil_mpu.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************
+*
+* Set the memory attributes for a section of memory with starting address addr
+* of the region size defined by reg_size having attributes attrib of region number
+* reg_num
+*
+* @param addr is the address for which attributes are to be set.
+* @param attrib specifies the attributes for that memory region.
+* @param reg_size specifies the size for that memory region.
+* @param reg_num specifies the number for that memory region.
+* @return None.
+*
+*
+******************************************************************************/
+void Xil_SetAttribute(u32 addr, u32 reg_size,int reg_num, u32 attrib)
+{
+ u32 CtrlReg, Alignment_Check=0x1;
+ int Index;
+ int DCacheStatus=0, ICacheStatus=0;
+ /* disbale caches only if they are enabled */
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ if (CtrlReg & XREG_CP15_CONTROL_C_BIT)
+ DCacheStatus=1;
+ if (CtrlReg & XREG_CP15_CONTROL_I_BIT)
+ ICacheStatus=1;
+
+ if(DCacheStatus)
+ Xil_DCacheDisable();
+ if(ICacheStatus){
+ Xil_ICacheDisable();
+ }
+ for (Index=0; Index<=reg_size;Index++)
+ Alignment_Check*=2;
+
+ /*If address is aligned with region size then it is configured*/
+
+ if(!(addr%Alignment_Check)){
+ reg_size = reg_size<<1;
+ reg_size|=REGION_EN;
+ mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num);
+ mtcp(XREG_CP15_MPU_REG_BASEADDR,addr); /* Set base address of a region */
+ mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL,attrib); /* Set the control attribute */
+ mtcp(XREG_CP15_MPU_REG_SIZE_EN,reg_size); /* set the region size and enable it*/
+ dsb(); /* ensure completion of the BP invalidation */
+ isb(); /* synchronize context on this processor */
+ }
+
+ /* enable caches only if they are disabled in routine*/
+ if(DCacheStatus)
+ Xil_DCacheEnable();
+ if(ICacheStatus)
+ Xil_ICacheEnable();
+}
+
+/*****************************************************************************
+*
+* Enable MPU for Cortex R5 processor. This function invalidates I cache and
+* flush the D Caches before enabling the MPU.
+*
+*
+* @param None.
+* @return None.
+*
+******************************************************************************/
+void Xil_EnableMPU(void)
+{
+ u32 CtrlReg, Reg;
+ int DCacheStatus=0, ICacheStatus=0;
+ /* enable caches only if they are disabled */
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ if (CtrlReg & XREG_CP15_CONTROL_C_BIT)
+ DCacheStatus=1;
+ if (CtrlReg & XREG_CP15_CONTROL_I_BIT)
+ ICacheStatus=1;
+
+ if(DCacheStatus)
+ Xil_DCacheDisable();
+ if(ICacheStatus){
+ Xil_ICacheDisable();
+ }
+ Reg = mfcp(XREG_CP15_SYS_CONTROL);
+ Reg |= 0x01;
+ dsb();
+ mtcp(XREG_CP15_SYS_CONTROL, Reg);
+ isb();
+ /* enable caches only if they are disabled in routine*/
+ if(DCacheStatus)
+ Xil_DCacheEnable();
+ if(ICacheStatus)
+ Xil_ICacheEnable();
+}
+
+/*****************************************************************************
+*
+* Disable MPU for Cortex R5 processors. This function invalidates I cache and
+* flush the D Caches before disabling the MPU.
+*
+* @param None.
+*
+* @return None.
+*
+******************************************************************************/
+void Xil_DisableMPU(void)
+{
+ u32 CtrlReg, Reg;
+ int DCacheStatus=0, ICacheStatus=0;
+ /* enable caches only if they are disabled */
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ if (CtrlReg & XREG_CP15_CONTROL_C_BIT)
+ DCacheStatus=1;
+ if (CtrlReg & XREG_CP15_CONTROL_I_BIT)
+ ICacheStatus=1;
+
+ if(DCacheStatus)
+ Xil_DCacheDisable();
+ if(ICacheStatus){
+ Xil_ICacheDisable();
+ }
+
+ mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0);
+ Reg = mfcp(XREG_CP15_SYS_CONTROL);
+ Reg &= ~0x01;
+ dsb();
+ mtcp(XREG_CP15_SYS_CONTROL, Reg);
+ isb();
+ /* enable caches only if they are disabled in routine*/
+ if(DCacheStatus)
+ Xil_DCacheEnable();
+ if(ICacheStatus)
+ Xil_ICacheEnable();
+}
+
+/*****************************************************************************
+*
+* Disable a Region in MPU for Cortex R5 processors. This function invalidates
+* I cache and flush the D Caches before disabling the MPU region.
+*
+* @param reg_num defines region number which is to be disabled.
+*
+* @return None.
+*
+******************************************************************************/
+
+void Xil_DisableRegion(int reg_num)
+{
+ u32 CtrlReg, Reg;
+ int DCacheStatus=0, ICacheStatus=0;
+ /* enable caches only if they are disabled */
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ if (CtrlReg & XREG_CP15_CONTROL_C_BIT)
+ DCacheStatus=1;
+ if (CtrlReg & XREG_CP15_CONTROL_I_BIT)
+ ICacheStatus=1;
+
+ if(DCacheStatus)
+ Xil_DCacheDisable();
+ if(ICacheStatus){
+ Xil_ICacheDisable();
+ }
+
+ mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0);
+ mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num);
+
+ Reg = mfcp(XREG_CP15_MPU_REG_SIZE_EN);
+
+ Reg &= ~REGION_EN;
+ dsb();
+ mtcp(XREG_CP15_MPU_REG_SIZE_EN, Reg);
+ isb();
+ /* enable caches only if they are disabled in routine*/
+ if(DCacheStatus)
+ Xil_DCacheEnable();
+ if(ICacheStatus)
+ Xil_ICacheEnable();
+}
+/*****************************************************************************
+*
+* Disable a SubRegion in MPU for Cortex R5 processors. This function invalidates
+* I cache and flush the D Caches before disabling
+* the MPU subregion.
+*
+* @param reg_num defines region number in which particular subregion
+* is to be disabled.
+* @param subreg_num defines the subregion number which is to be disabled.
+* @return None.
+*
+******************************************************************************/
+
+void Xil_DisableSubRegion(int reg_num, int subreg_num)
+{
+ u32 CtrlReg, Reg;
+ int DCacheStatus=0, ICacheStatus=0;
+ /* enable caches only if they are disabled */
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ if (CtrlReg & XREG_CP15_CONTROL_C_BIT)
+ DCacheStatus=1;
+ if (CtrlReg & XREG_CP15_CONTROL_I_BIT)
+ ICacheStatus=1;
+
+ if(DCacheStatus)
+ Xil_DCacheDisable();
+ if(ICacheStatus){
+ Xil_ICacheDisable();
+ }
+
+ mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0);
+ mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num);
+
+ Reg = mfcp(XREG_CP15_MPU_REG_SIZE_EN);
+ Reg |= ((0x1<<subreg_num)<<8);
+ dsb();
+ mtcp(XREG_CP15_MPU_REG_SIZE_EN, Reg);
+ isb();
+ /* enable caches only if they are disabled in routine*/
+ if(DCacheStatus)
+ Xil_DCacheEnable();
+ if(ICacheStatus)
+ Xil_ICacheEnable();
+}
+
+/*****************************************************************************
+*
+* Enable a SubRegion in MPU for Cortex R5 processors. This function invalidates
+* I cache and flush the D Caches before enabling the MPU subregion.
+*
+* @param reg_num defines region number in which particular subregion
+* is to be enabled.
+* @param subreg_num defines the subregion number which is to be enabled.
+* @return None.
+*
+******************************************************************************/
+
+void Xil_EnableSubRegion(int reg_num, int subreg_num)
+{
+ u32 CtrlReg, Reg;
+ int DCacheStatus=0, ICacheStatus=0;
+ /* enable caches only if they are disabled */
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ if (CtrlReg & XREG_CP15_CONTROL_C_BIT)
+ DCacheStatus=1;
+ if (CtrlReg & XREG_CP15_CONTROL_I_BIT)
+ ICacheStatus=1;
+
+ if(DCacheStatus)
+ Xil_DCacheDisable();
+ if(ICacheStatus){
+ Xil_ICacheDisable();
+ }
+
+ mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0);
+ mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num);
+ Reg = mfcp(XREG_CP15_MPU_REG_SIZE_EN);
+ Reg &=~((0x1<<subreg_num)<<8);
+ dsb();
+ mtcp(XREG_CP15_MPU_REG_SIZE_EN, Reg);
+ isb();
+ /* enable caches only if they are disabled in routine*/
+ if(DCacheStatus)
+ Xil_DCacheEnable();
+ if(ICacheStatus)
+ Xil_ICacheEnable();
+}
+/*****************************************************************************
+*
+* Enable a background Region in MPU with default memory attributes for Cortex R5
+* processor. This function invalidates I cache and flush the D Caches before
+* enabling a background Region.
+*
+* @param None.
+*
+* @return None.
+*
+*
+******************************************************************************/
+
+void Xil_EnableBackgroundRegion(void)
+{
+
+ u32 CtrlReg, Reg;
+ int DCacheStatus=0, ICacheStatus=0;
+ /* enable caches only if they are disabled */
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ if (CtrlReg & XREG_CP15_CONTROL_C_BIT)
+ DCacheStatus=1;
+ if (CtrlReg & XREG_CP15_CONTROL_I_BIT)
+ ICacheStatus=1;
+
+ if(DCacheStatus)
+ Xil_DCacheDisable();
+ if(ICacheStatus){
+ Xil_ICacheDisable();
+ }
+ mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0);
+ Reg=mfcp(XREG_CP15_SYS_CONTROL);
+ Reg |= 0x1<<17;
+
+ dsb();
+ mtcp(XREG_CP15_SYS_CONTROL,Reg);
+
+ isb();
+ /* enable caches only if they are disabled in routine*/
+ if(DCacheStatus)
+ Xil_DCacheEnable();
+ if(ICacheStatus)
+ Xil_ICacheEnable();
+}
+/*****************************************************************************
+*
+* Disable a background Region in MPU for Cortex R5 processor. This function
+* invalidates I cache and flush the D Caches before
+* disabling a background Region.
+*
+* @param None.
+*
+* @return None.
+*
+*
+******************************************************************************/
+
+void Xil_DisableBackgroundRegion(void)
+{
+
+ u32 CtrlReg, Reg;
+ int DCacheStatus=0, ICacheStatus=0;
+ /* enable caches only if they are disabled */
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ if (CtrlReg & XREG_CP15_CONTROL_C_BIT)
+ DCacheStatus=1;
+ if (CtrlReg & XREG_CP15_CONTROL_I_BIT)
+ ICacheStatus=1;
+
+ if(DCacheStatus)
+ Xil_DCacheDisable();
+ if(ICacheStatus){
+ Xil_ICacheDisable();
+ }
+ mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0);
+ Xil_DCacheFlush();
+ Reg=mfcp(XREG_CP15_SYS_CONTROL);
+ Reg &= ~(0x1<<17);
+
+ dsb();
+ mtcp(XREG_CP15_SYS_CONTROL,Reg);
+
+ isb();
+ /* enable caches only if they are disabled in routine*/
+ if(DCacheStatus)
+ Xil_DCacheEnable();
+ if(ICacheStatus)
+ Xil_ICacheEnable();
+}
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil_mpu.h b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil_mpu.h
--- /dev/null
@@ -0,0 +1,94 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.h
+*
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 pkp 02/10/14 Initial version
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef XIL_MPU_H
+#define XIL_MPU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#include "xil_types.h"
+/***************************** Include Files *********************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SetAttribute(u32 addr, u32 reg_size,int reg_num, u32 attrib);
+void Xil_EnableMPU(void);
+void Xil_DisableMPU(void);
+void Xil_DisableRegion(int reg_num);
+void Xil_DisableSubRegion(int reg_num, int subreg_num);
+void Xil_EnableSubRegion(int reg_num, int subreg_num);
+void Xil_EnableBackgroundRegion(void);
+void Xil_DisableBackgroundRegion(void);
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_MPU_H */
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil_types.h b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xil_types.h
--- /dev/null
@@ -0,0 +1,188 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_types.h
+*
+* This file contains basic types for Xilinx software IP.
+
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/14/09 First release
+* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+* 5.00 pkp 05/29/14 Made changes for 64 bit architecture
+* srt 07/14/14 Use standard definitions from stdint.h and stddef.h
+* Define LONG and ULONG datatypes and mask values
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_TYPES_H /* prevent circular inclusions */
+#define XIL_TYPES_H /* by using protection macros */
+
+#include <stdint.h>
+#include <stddef.h>
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+# define TRUE 1
+#endif
+
+#ifndef FALSE
+# define FALSE 0
+#endif
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+#define XIL_COMPONENT_IS_READY 0x11111111 /**< component has been initialized */
+#define XIL_COMPONENT_IS_STARTED 0x22222222 /**< component has been started */
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XBASIC_TYPES_H
+/**
+ * guarded against xbasic_types.h.
+ */
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+
+#define __XUINT64__
+typedef struct
+{
+ u32 Upper;
+ u32 Lower;
+} Xuint64;
+
+
+/*****************************************************************************/
+/**
+* Return the most significant half of the 64 bit data type.
+*
+* @param x is the 64 bit word.
+*
+* @return The upper 32 bits of the 64 bit word.
+*
+* @note None.
+*
+******************************************************************************/
+#define XUINT64_MSW(x) ((x).Upper)
+
+/*****************************************************************************/
+/**
+* Return the least significant half of the 64 bit data type.
+*
+* @param x is the 64 bit word.
+*
+* @return The lower 32 bits of the 64 bit word.
+*
+* @note None.
+*
+******************************************************************************/
+#define XUINT64_LSW(x) ((x).Lower)
+
+#endif /* XBASIC_TYPES_H */
+
+typedef int8_t s8;
+typedef int16_t s16;
+typedef int32_t s32;
+typedef int64_t s64;
+typedef uint64_t u64;
+typedef intptr_t INTPTR;
+typedef uintptr_t UINTPTR;
+typedef ptrdiff_t PTRDIFF;
+
+#if !defined(LONG) || !defined(ULONG)
+typedef long LONG;
+typedef unsigned long ULONG;
+#endif
+
+#define ULONG64_HI_MASK 0xFFFFFFFF00000000
+#define ULONG64_LO_MASK ~ULONG64_HI_MASK
+
+#else
+#include <linux/types.h>
+#endif
+
+
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/**
+ * This data type defines an exception handler for a processor.
+ * The argument points to the instance of the component
+ */
+typedef void (*XExceptionHandler) (void *InstancePtr);
+
+/*@}*/
+
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+#endif /* end of protection macro */
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xparameters.h b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xparameters.h
--- /dev/null
@@ -0,0 +1,685 @@
+/* Definition for CPU ID */
+#define XPAR_CPU_ID 0
+
+/* Definitions for peripheral PS8_CORTEXR5_0 */
+#define XPAR_PS8_CORTEXR5_0_CPU_CLK_FREQ_HZ 500000000
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS8_CORTEXR5_0 */
+#define XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ 500000000
+
+
+/******************************************************************/
+
+#include "xparameters_ps.h"
+
+#define STDIN_BASEADDRESS 0xFF000000
+#define STDOUT_BASEADDRESS 0xFF000000
+
+/******************************************************************/
+
+/* Definitions for driver CANPS */
+#define XPAR_XCANPS_NUM_INSTANCES 2
+
+/* Definitions for peripheral PS8_CAN_0 */
+#define XPAR_PS8_CAN_0_DEVICE_ID 0
+#define XPAR_PS8_CAN_0_BASEADDR 0xFF060000
+#define XPAR_PS8_CAN_0_HIGHADDR 0xFF060FFF
+#define XPAR_PS8_CAN_0_CAN_CLK_FREQ_HZ 100000000
+
+
+/* Definitions for peripheral PS8_CAN_1 */
+#define XPAR_PS8_CAN_1_DEVICE_ID 1
+#define XPAR_PS8_CAN_1_BASEADDR 0xFF070000
+#define XPAR_PS8_CAN_1_HIGHADDR 0xFF070FFF
+#define XPAR_PS8_CAN_1_CAN_CLK_FREQ_HZ 100000000
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS8_CAN_0 */
+#define XPAR_XCANPS_0_DEVICE_ID XPAR_PS8_CAN_0_DEVICE_ID
+#define XPAR_XCANPS_0_BASEADDR 0xFF060000
+#define XPAR_XCANPS_0_HIGHADDR 0xFF060FFF
+#define XPAR_XCANPS_0_CAN_CLK_FREQ_HZ 100000000
+
+/* Canonical definitions for peripheral PS8_CAN_1 */
+#define XPAR_XCANPS_1_DEVICE_ID XPAR_PS8_CAN_1_DEVICE_ID
+#define XPAR_XCANPS_1_BASEADDR 0xFF070000
+#define XPAR_XCANPS_1_HIGHADDR 0xFF070FFF
+#define XPAR_XCANPS_1_CAN_CLK_FREQ_HZ 100000000
+
+
+/******************************************************************/
+
+/* Definitions for driver EMACPS */
+#define XPAR_XEMACPS_NUM_INSTANCES 4
+
+/* Definitions for peripheral PS8_ETHERNET_0 */
+#define XPAR_PS8_ETHERNET_0_DEVICE_ID 0
+#define XPAR_PS8_ETHERNET_0_BASEADDR 0xFF0B0000
+#define XPAR_PS8_ETHERNET_0_HIGHADDR 0xFF0B0FFF
+#define XPAR_PS8_ETHERNET_0_ENET_CLK_FREQ_HZ 125000000
+#define XPAR_PS8_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 50000000
+#define XPAR_PS8_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 50000000
+#define XPAR_PS8_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 50000000
+#define XPAR_PS8_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 50000000
+#define XPAR_PS8_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 50000000
+#define XPAR_PS8_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50000000
+
+
+/* Definitions for peripheral PS8_ETHERNET_1 */
+#define XPAR_PS8_ETHERNET_1_DEVICE_ID 1
+#define XPAR_PS8_ETHERNET_1_BASEADDR 0xFF0C0000
+#define XPAR_PS8_ETHERNET_1_HIGHADDR 0xFF0C0FFF
+#define XPAR_PS8_ETHERNET_1_ENET_CLK_FREQ_HZ 125000000
+#define XPAR_PS8_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0 50000000
+#define XPAR_PS8_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1 50000000
+#define XPAR_PS8_ETHERNET_1_ENET_SLCR_100MBPS_DIV0 50000000
+#define XPAR_PS8_ETHERNET_1_ENET_SLCR_100MBPS_DIV1 50000000
+#define XPAR_PS8_ETHERNET_1_ENET_SLCR_10MBPS_DIV0 50000000
+#define XPAR_PS8_ETHERNET_1_ENET_SLCR_10MBPS_DIV1 50000000
+
+
+/* Definitions for peripheral PS8_ETHERNET_2 */
+#define XPAR_PS8_ETHERNET_2_DEVICE_ID 2
+#define XPAR_PS8_ETHERNET_2_BASEADDR 0xFF0D0000
+#define XPAR_PS8_ETHERNET_2_HIGHADDR 0xFF0D0FFF
+#define XPAR_PS8_ETHERNET_2_ENET_CLK_FREQ_HZ 125000000
+#define XPAR_PS8_ETHERNET_2_ENET_SLCR_1000MBPS_DIV0 50000000
+#define XPAR_PS8_ETHERNET_2_ENET_SLCR_1000MBPS_DIV1 50000000
+#define XPAR_PS8_ETHERNET_2_ENET_SLCR_100MBPS_DIV0 50000000
+#define XPAR_PS8_ETHERNET_2_ENET_SLCR_100MBPS_DIV1 50000000
+#define XPAR_PS8_ETHERNET_2_ENET_SLCR_10MBPS_DIV0 50000000
+#define XPAR_PS8_ETHERNET_2_ENET_SLCR_10MBPS_DIV1 50000000
+
+
+/* Definitions for peripheral PS8_ETHERNET_3 */
+#define XPAR_PS8_ETHERNET_3_DEVICE_ID 3
+#define XPAR_PS8_ETHERNET_3_BASEADDR 0xFF0E0000
+#define XPAR_PS8_ETHERNET_3_HIGHADDR 0xFF0E0FFF
+#define XPAR_PS8_ETHERNET_3_ENET_CLK_FREQ_HZ 125000000
+#define XPAR_PS8_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 50000000
+#define XPAR_PS8_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 50000000
+#define XPAR_PS8_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 50000000
+#define XPAR_PS8_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 50000000
+#define XPAR_PS8_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 50000000
+#define XPAR_PS8_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 50000000
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS8_ETHERNET_0 */
+#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS8_ETHERNET_0_DEVICE_ID
+#define XPAR_XEMACPS_0_BASEADDR 0xFF0B0000
+#define XPAR_XEMACPS_0_HIGHADDR 0xFF0B0FFF
+#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 125000000
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 50000000
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 50000000
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 50000000
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 50000000
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 50000000
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50000000
+
+/* Canonical definitions for peripheral PS8_ETHERNET_1 */
+#define XPAR_XEMACPS_1_DEVICE_ID XPAR_PS8_ETHERNET_1_DEVICE_ID
+#define XPAR_XEMACPS_1_BASEADDR 0xFF0C0000
+#define XPAR_XEMACPS_1_HIGHADDR 0xFF0C0FFF
+#define XPAR_XEMACPS_1_ENET_CLK_FREQ_HZ 125000000
+#define XPAR_XEMACPS_1_ENET_SLCR_1000Mbps_DIV0 50000000
+#define XPAR_XEMACPS_1_ENET_SLCR_1000Mbps_DIV1 50000000
+#define XPAR_XEMACPS_1_ENET_SLCR_100Mbps_DIV0 50000000
+#define XPAR_XEMACPS_1_ENET_SLCR_100Mbps_DIV1 50000000
+#define XPAR_XEMACPS_1_ENET_SLCR_10Mbps_DIV0 50000000
+#define XPAR_XEMACPS_1_ENET_SLCR_10Mbps_DIV1 50000000
+
+/* Canonical definitions for peripheral PS8_ETHERNET_2 */
+#define XPAR_XEMACPS_2_DEVICE_ID XPAR_PS8_ETHERNET_2_DEVICE_ID
+#define XPAR_XEMACPS_2_BASEADDR 0xFF0D0000
+#define XPAR_XEMACPS_2_HIGHADDR 0xFF0D0FFF
+#define XPAR_XEMACPS_2_ENET_CLK_FREQ_HZ 125000000
+#define XPAR_XEMACPS_2_ENET_SLCR_1000Mbps_DIV0 50000000
+#define XPAR_XEMACPS_2_ENET_SLCR_1000Mbps_DIV1 50000000
+#define XPAR_XEMACPS_2_ENET_SLCR_100Mbps_DIV0 50000000
+#define XPAR_XEMACPS_2_ENET_SLCR_100Mbps_DIV1 50000000
+#define XPAR_XEMACPS_2_ENET_SLCR_10Mbps_DIV0 50000000
+#define XPAR_XEMACPS_2_ENET_SLCR_10Mbps_DIV1 50000000
+
+/* Canonical definitions for peripheral PS8_ETHERNET_3 */
+#define XPAR_XEMACPS_3_DEVICE_ID XPAR_PS8_ETHERNET_3_DEVICE_ID
+#define XPAR_XEMACPS_3_BASEADDR 0xFF0E0000
+#define XPAR_XEMACPS_3_HIGHADDR 0xFF0E0FFF
+#define XPAR_XEMACPS_3_ENET_CLK_FREQ_HZ 125000000
+#define XPAR_XEMACPS_3_ENET_SLCR_1000Mbps_DIV0 50000000
+#define XPAR_XEMACPS_3_ENET_SLCR_1000Mbps_DIV1 50000000
+#define XPAR_XEMACPS_3_ENET_SLCR_100Mbps_DIV0 50000000
+#define XPAR_XEMACPS_3_ENET_SLCR_100Mbps_DIV1 50000000
+#define XPAR_XEMACPS_3_ENET_SLCR_10Mbps_DIV0 50000000
+#define XPAR_XEMACPS_3_ENET_SLCR_10Mbps_DIV1 50000000
+
+
+/******************************************************************/
+
+
+/* Definitions for peripheral PS8_ADMA_0 */
+#define XPAR_PS8_ADMA_0_S_AXI_BASEADDR 0xFF500000
+#define XPAR_PS8_ADMA_0_S_AXI_HIGHADDR 0xFF53FFFF
+
+
+/* Definitions for peripheral PS8_AFI_0 */
+#define XPAR_PS8_AFI_0_S_AXI_BASEADDR 0xFE501000
+#define XPAR_PS8_AFI_0_S_AXI_HIGHADDR 0xFE501FFF
+
+
+/* Definitions for peripheral PS8_AFI_1 */
+#define XPAR_PS8_AFI_1_S_AXI_BASEADDR 0xFE502000
+#define XPAR_PS8_AFI_1_S_AXI_HIGHADDR 0xFE502FFF
+
+
+/* Definitions for peripheral PS8_AFI_2 */
+#define XPAR_PS8_AFI_2_S_AXI_BASEADDR 0xFE503000
+#define XPAR_PS8_AFI_2_S_AXI_HIGHADDR 0xFE503FFF
+
+
+/* Definitions for peripheral PS8_AFI_3 */
+#define XPAR_PS8_AFI_3_S_AXI_BASEADDR 0xFE504000
+#define XPAR_PS8_AFI_3_S_AXI_HIGHADDR 0xFE504FFF
+
+
+/* Definitions for peripheral PS8_AFI_4 */
+#define XPAR_PS8_AFI_4_S_AXI_BASEADDR 0xFE505000
+#define XPAR_PS8_AFI_4_S_AXI_HIGHADDR 0xFE505FFF
+
+
+/* Definitions for peripheral PS8_AFI_5 */
+#define XPAR_PS8_AFI_5_S_AXI_BASEADDR 0xFE506000
+#define XPAR_PS8_AFI_5_S_AXI_HIGHADDR 0xFE506FFF
+
+
+/* Definitions for peripheral PS8_AFI_6 */
+#define XPAR_PS8_AFI_6_S_AXI_BASEADDR 0xFE504000
+#define XPAR_PS8_AFI_6_S_AXI_HIGHADDR 0xFE504FFF
+
+
+/* Definitions for peripheral PS8_APM_0 */
+#define XPAR_PS8_APM_0_S_AXI_BASEADDR 0xFD0B0000
+#define XPAR_PS8_APM_0_S_AXI_HIGHADDR 0xFD0B0300
+
+
+/* Definitions for peripheral PS8_APM_1 */
+#define XPAR_PS8_APM_1_S_AXI_BASEADDR 0xFFA00000
+#define XPAR_PS8_APM_1_S_AXI_HIGHADDR 0xFFA00300
+
+
+/* Definitions for peripheral PS8_APM_2 */
+#define XPAR_PS8_APM_2_S_AXI_BASEADDR 0xFFA10000
+#define XPAR_PS8_APM_2_S_AXI_HIGHADDR 0xFFA10300
+
+
+/* Definitions for peripheral PS8_APM_3 */
+#define XPAR_PS8_APM_3_S_AXI_BASEADDR 0xFFA20000
+#define XPAR_PS8_APM_3_S_AXI_HIGHADDR 0xFFA20300
+
+
+/* Definitions for peripheral PS8_APM_4 */
+#define XPAR_PS8_APM_4_S_AXI_BASEADDR 0xFFA30000
+#define XPAR_PS8_APM_4_S_AXI_HIGHADDR 0xFFA30300
+
+
+/* Definitions for peripheral PS8_BBRAM_0 */
+#define XPAR_PS8_BBRAM_0_S_AXI_BASEADDR 0xFFCC4000
+#define XPAR_PS8_BBRAM_0_S_AXI_HIGHADDR 0xFFCC4FFF
+
+
+/* Definitions for peripheral PS8_CSU_RAM_0 */
+#define XPAR_PS8_CSU_RAM_0_S_AXI_BASEADDR 0xFFC40000
+#define XPAR_PS8_CSU_RAM_0_S_AXI_HIGHADDR 0xFFC47FFF
+
+
+/* Definitions for peripheral PS8_DEV_CFG_0 */
+#define XPAR_PS8_DEV_CFG_0_S_AXI_BASEADDR 0xF8007000
+#define XPAR_PS8_DEV_CFG_0_S_AXI_HIGHADDR 0xF8007FFF
+
+
+/* Definitions for peripheral PS8_GDMA_0 */
+#define XPAR_PS8_GDMA_0_S_AXI_BASEADDR 0xFE570000
+#define XPAR_PS8_GDMA_0_S_AXI_HIGHADDR 0xFE5AFFFF
+
+
+/* Definitions for peripheral PS8_IOP_BUS_CONFIG_0 */
+#define XPAR_PS8_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000
+#define XPAR_PS8_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF
+
+
+/* Definitions for peripheral PS8_IOUSLCR_0 */
+#define XPAR_PS8_IOUSLCR_0_S_AXI_BASEADDR 0xFF180000
+#define XPAR_PS8_IOUSLCR_0_S_AXI_HIGHADDR 0xFF180FFF
+
+
+/* Definitions for peripheral PS8_OCM_RAM_0 */
+#define XPAR_PS8_OCM_RAM_0_S_AXI_BASEADDR 0xFFFC0000
+#define XPAR_PS8_OCM_RAM_0_S_AXI_HIGHADDR 0xFFFEFFFF
+
+
+/* Definitions for peripheral PS8_OCM_RAM_1 */
+#define XPAR_PS8_OCM_RAM_1_S_AXI_BASEADDR 0xFFFF0000
+#define XPAR_PS8_OCM_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
+
+
+/* Definitions for peripheral PS8_QSPI_LINEAR_0 */
+#define XPAR_PS8_QSPI_LINEAR_0_S_AXI_BASEADDR 0xC0000000
+#define XPAR_PS8_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xDFFFFFFF
+
+
+/* Definitions for peripheral PS8_R5_TCM_RAM_0 */
+#define XPAR_PS8_R5_TCM_RAM_0_S_AXI_BASEADDR 0x00000000
+#define XPAR_PS8_R5_TCM_RAM_0_S_AXI_HIGHADDR 0x00020000
+
+
+/* Definitions for peripheral PS8_SCUTIMER_0 */
+#define XPAR_PS8_SCUTIMER_0_S_AXI_BASEADDR 0xFD3FE600
+#define XPAR_PS8_SCUTIMER_0_S_AXI_HIGHADDR 0xFD3FE61F
+
+
+/* Definitions for peripheral PS8_SCUWDT_0 */
+#define XPAR_PS8_SCUWDT_0_S_AXI_BASEADDR 0xFD3FE620
+#define XPAR_PS8_SCUWDT_0_S_AXI_HIGHADDR 0xFD3FE6FF
+
+
+/******************************************************************/
+
+/* Definitions for driver GPIOPS */
+#define XPAR_XGPIOPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS8_GPIO_0 */
+#define XPAR_PS8_GPIO_0_DEVICE_ID 0
+#define XPAR_PS8_GPIO_0_BASEADDR 0xFF0A0000
+#define XPAR_PS8_GPIO_0_HIGHADDR 0xFF0A0FFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS8_GPIO_0 */
+#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS8_GPIO_0_DEVICE_ID
+#define XPAR_XGPIOPS_0_BASEADDR 0xFF0A0000
+#define XPAR_XGPIOPS_0_HIGHADDR 0xFF0A0FFF
+
+
+/******************************************************************/
+
+/* Definitions for driver IICPS */
+#define XPAR_XIICPS_NUM_INSTANCES 2
+
+/* Definitions for peripheral PS8_I2C_0 */
+#define XPAR_PS8_I2C_0_DEVICE_ID 0
+#define XPAR_PS8_I2C_0_BASEADDR 0xFF020000
+#define XPAR_PS8_I2C_0_HIGHADDR 0xFF020FFF
+#define XPAR_PS8_I2C_0_I2C_CLK_FREQ_HZ 100000000
+
+
+/* Definitions for peripheral PS8_I2C_1 */
+#define XPAR_PS8_I2C_1_DEVICE_ID 1
+#define XPAR_PS8_I2C_1_BASEADDR 0xFF030000
+#define XPAR_PS8_I2C_1_HIGHADDR 0xFF030FFF
+#define XPAR_PS8_I2C_1_I2C_CLK_FREQ_HZ 100000000
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS8_I2C_0 */
+#define XPAR_XIICPS_0_DEVICE_ID XPAR_PS8_I2C_0_DEVICE_ID
+#define XPAR_XIICPS_0_BASEADDR 0xFF020000
+#define XPAR_XIICPS_0_HIGHADDR 0xFF020FFF
+#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 100000000
+
+/* Canonical definitions for peripheral PS8_I2C_1 */
+#define XPAR_XIICPS_1_DEVICE_ID XPAR_PS8_I2C_1_DEVICE_ID
+#define XPAR_XIICPS_1_BASEADDR 0xFF030000
+#define XPAR_XIICPS_1_HIGHADDR 0xFF030FFF
+#define XPAR_XIICPS_1_I2C_CLK_FREQ_HZ 100000000
+
+
+/******************************************************************/
+
+/* Definitions for driver NANDPS8 */
+#define XPAR_XNANDPS8_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS8_NAND_0 */
+#define XPAR_PS8_NAND_0_DEVICE_ID 0
+#define XPAR_PS8_NAND_0_BASEADDR 0xFF100000
+#define XPAR_PS8_NAND_0_HIGHADDR 0xFF100FFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS8_NAND_0 */
+#define XPAR_XNANDPS8_0_DEVICE_ID XPAR_PS8_NAND_0_DEVICE_ID
+#define XPAR_XNANDPS8_0_BASEADDR 0xFF100000
+#define XPAR_XNANDPS8_0_HIGHADDR 0xFF100FFF
+
+
+/******************************************************************/
+
+/* Definitions for driver QSPIPS */
+#define XPAR_XQSPIPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS8_QSPI_0 */
+#define XPAR_PS8_QSPI_0_DEVICE_ID 0
+#define XPAR_PS8_QSPI_0_BASEADDR 0xFF0F0000
+#define XPAR_PS8_QSPI_0_HIGHADDR 0xFF0F0FFF
+#define XPAR_PS8_QSPI_0_QSPI_CLK_FREQ_HZ 300000000
+#define XPAR_PS8_QSPI_0_QSPI_MODE 0
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS8_QSPI_0 */
+#define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS8_QSPI_0_DEVICE_ID
+#define XPAR_XQSPIPS_0_BASEADDR 0xFF0F0000
+#define XPAR_XQSPIPS_0_HIGHADDR 0xFF0F0FFF
+#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 300000000
+#define XPAR_XQSPIPS_0_QSPI_MODE 0
+
+
+/******************************************************************/
+
+
+/***Definitions for Core_nIRQ/nFIQ interrupts ****/
+/* Definitions for driver SCUGIC */
+#define XPAR_XSCUGIC_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS8_SCUGIC_0 */
+#define XPAR_PS8_SCUGIC_0_DEVICE_ID 0
+#define XPAR_PS8_SCUGIC_0_BASEADDR 0xF9001000
+#define XPAR_PS8_SCUGIC_0_HIGHADDR 0xF9001FFF
+#define XPAR_PS8_SCUGIC_0_DIST_BASEADDR 0xF9000000
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS8_SCUGIC_0 */
+#define XPAR_SCUGIC_0_DEVICE_ID 0
+#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF9001000
+#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF9001FFF
+#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF9000000
+
+
+/******************************************************************/
+
+/* Definitions for driver SDPS */
+#define XPAR_XSDPS_NUM_INSTANCES 2
+
+/* Definitions for peripheral PS8_SD_0 */
+#define XPAR_PS8_SD_0_DEVICE_ID 0
+#define XPAR_PS8_SD_0_BASEADDR 0xFF160000
+#define XPAR_PS8_SD_0_HIGHADDR 0xFF160FFF
+#define XPAR_PS8_SD_0_SDIO_CLK_FREQ_HZ 200000000
+
+
+/* Definitions for peripheral PS8_SD_1 */
+#define XPAR_PS8_SD_1_DEVICE_ID 1
+#define XPAR_PS8_SD_1_BASEADDR 0xFF170000
+#define XPAR_PS8_SD_1_HIGHADDR 0xFF170FFF
+#define XPAR_PS8_SD_1_SDIO_CLK_FREQ_HZ 200000000
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS8_SD_0 */
+#define XPAR_XSDPS_0_DEVICE_ID XPAR_PS8_SD_0_DEVICE_ID
+#define XPAR_XSDPS_0_BASEADDR 0xFF160000
+#define XPAR_XSDPS_0_HIGHADDR 0xFF160FFF
+#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 200000000
+
+/* Canonical definitions for peripheral PS8_SD_1 */
+#define XPAR_XSDPS_1_DEVICE_ID XPAR_PS8_SD_1_DEVICE_ID
+#define XPAR_XSDPS_1_BASEADDR 0xFF170000
+#define XPAR_XSDPS_1_HIGHADDR 0xFF170FFF
+#define XPAR_XSDPS_1_SDIO_CLK_FREQ_HZ 200000000
+
+
+/******************************************************************/
+
+/* Definitions for driver SPIPS */
+#define XPAR_XSPIPS_NUM_INSTANCES 2
+
+/* Definitions for peripheral PS8_SPI_0 */
+#define XPAR_PS8_SPI_0_DEVICE_ID 0
+#define XPAR_PS8_SPI_0_BASEADDR 0xFF040000
+#define XPAR_PS8_SPI_0_HIGHADDR 0xFF040FFF
+#define XPAR_PS8_SPI_0_SPI_CLK_FREQ_HZ 214000000
+
+
+/* Definitions for peripheral PS8_SPI_1 */
+#define XPAR_PS8_SPI_1_DEVICE_ID 1
+#define XPAR_PS8_SPI_1_BASEADDR 0xFF050000
+#define XPAR_PS8_SPI_1_HIGHADDR 0xFF050FFF
+#define XPAR_PS8_SPI_1_SPI_CLK_FREQ_HZ 214000000
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS8_SPI_0 */
+#define XPAR_XSPIPS_0_DEVICE_ID XPAR_PS8_SPI_0_DEVICE_ID
+#define XPAR_XSPIPS_0_BASEADDR 0xFF040000
+#define XPAR_XSPIPS_0_HIGHADDR 0xFF040FFF
+#define XPAR_XSPIPS_0_SPI_CLK_FREQ_HZ 214000000
+
+/* Canonical definitions for peripheral PS8_SPI_1 */
+#define XPAR_XSPIPS_1_DEVICE_ID XPAR_PS8_SPI_1_DEVICE_ID
+#define XPAR_XSPIPS_1_BASEADDR 0xFF050000
+#define XPAR_XSPIPS_1_HIGHADDR 0xFF050FFF
+#define XPAR_XSPIPS_1_SPI_CLK_FREQ_HZ 214000000
+
+
+/******************************************************************/
+
+/* Definitions for driver TTCPS */
+#define XPAR_XTTCPS_NUM_INSTANCES 12
+
+/* Definitions for peripheral PS8_TTC_0 */
+#define XPAR_PS8_TTC_0_DEVICE_ID 0
+#define XPAR_PS8_TTC_0_BASEADDR 0XFF110000
+#define XPAR_PS8_TTC_0_TTC_CLK_FREQ_HZ 50000000
+#define XPAR_PS8_TTC_0_TTC_CLK_CLKSRC 0
+#define XPAR_PS8_TTC_1_DEVICE_ID 1
+#define XPAR_PS8_TTC_1_BASEADDR 0XFF110004
+#define XPAR_PS8_TTC_1_TTC_CLK_FREQ_HZ 50000000
+#define XPAR_PS8_TTC_1_TTC_CLK_CLKSRC 0
+#define XPAR_PS8_TTC_2_DEVICE_ID 2
+#define XPAR_PS8_TTC_2_BASEADDR 0XFF110008
+#define XPAR_PS8_TTC_2_TTC_CLK_FREQ_HZ 50000000
+#define XPAR_PS8_TTC_2_TTC_CLK_CLKSRC 0
+
+
+/* Definitions for peripheral PS8_TTC_1 */
+#define XPAR_PS8_TTC_3_DEVICE_ID 3
+#define XPAR_PS8_TTC_3_BASEADDR 0XFF120000
+#define XPAR_PS8_TTC_3_TTC_CLK_FREQ_HZ 50000000
+#define XPAR_PS8_TTC_3_TTC_CLK_CLKSRC 0
+#define XPAR_PS8_TTC_4_DEVICE_ID 4
+#define XPAR_PS8_TTC_4_BASEADDR 0XFF120004
+#define XPAR_PS8_TTC_4_TTC_CLK_FREQ_HZ 50000000
+#define XPAR_PS8_TTC_4_TTC_CLK_CLKSRC 0
+#define XPAR_PS8_TTC_5_DEVICE_ID 5
+#define XPAR_PS8_TTC_5_BASEADDR 0XFF120008
+#define XPAR_PS8_TTC_5_TTC_CLK_FREQ_HZ 50000000
+#define XPAR_PS8_TTC_5_TTC_CLK_CLKSRC 0
+
+
+/* Definitions for peripheral PS8_TTC_2 */
+#define XPAR_PS8_TTC_6_DEVICE_ID 6
+#define XPAR_PS8_TTC_6_BASEADDR 0XFF130000
+#define XPAR_PS8_TTC_6_TTC_CLK_FREQ_HZ 50000000
+#define XPAR_PS8_TTC_6_TTC_CLK_CLKSRC 0
+#define XPAR_PS8_TTC_7_DEVICE_ID 7
+#define XPAR_PS8_TTC_7_BASEADDR 0XFF130004
+#define XPAR_PS8_TTC_7_TTC_CLK_FREQ_HZ 50000000
+#define XPAR_PS8_TTC_7_TTC_CLK_CLKSRC 0
+#define XPAR_PS8_TTC_8_DEVICE_ID 8
+#define XPAR_PS8_TTC_8_BASEADDR 0XFF130008
+#define XPAR_PS8_TTC_8_TTC_CLK_FREQ_HZ 50000000
+#define XPAR_PS8_TTC_8_TTC_CLK_CLKSRC 0
+
+
+/* Definitions for peripheral PS8_TTC_3 */
+#define XPAR_PS8_TTC_9_DEVICE_ID 9
+#define XPAR_PS8_TTC_9_BASEADDR 0XFF140000
+#define XPAR_PS8_TTC_9_TTC_CLK_FREQ_HZ 50000000
+#define XPAR_PS8_TTC_9_TTC_CLK_CLKSRC 0
+#define XPAR_PS8_TTC_10_DEVICE_ID 10
+#define XPAR_PS8_TTC_10_BASEADDR 0XFF140004
+#define XPAR_PS8_TTC_10_TTC_CLK_FREQ_HZ 50000000
+#define XPAR_PS8_TTC_10_TTC_CLK_CLKSRC 0
+#define XPAR_PS8_TTC_11_DEVICE_ID 11
+#define XPAR_PS8_TTC_11_BASEADDR 0XFF140008
+#define XPAR_PS8_TTC_11_TTC_CLK_FREQ_HZ 50000000
+#define XPAR_PS8_TTC_11_TTC_CLK_CLKSRC 0
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS8_TTC_0 */
+#define XPAR_XTTCPS_0_DEVICE_ID XPAR_PS8_TTC_0_DEVICE_ID
+#define XPAR_XTTCPS_0_BASEADDR 0xFF110000
+#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 50000000
+#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0
+
+#define XPAR_XTTCPS_1_DEVICE_ID XPAR_PS8_TTC_1_DEVICE_ID
+#define XPAR_XTTCPS_1_BASEADDR 0xFF110004
+#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 50000000
+#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0
+
+#define XPAR_XTTCPS_2_DEVICE_ID XPAR_PS8_TTC_2_DEVICE_ID
+#define XPAR_XTTCPS_2_BASEADDR 0xFF110008
+#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 50000000
+#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0
+
+/* Canonical definitions for peripheral PS8_TTC_1 */
+#define XPAR_XTTCPS_3_DEVICE_ID XPAR_PS8_TTC_3_DEVICE_ID
+#define XPAR_XTTCPS_3_BASEADDR 0xFF120000
+#define XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ 50000000
+#define XPAR_XTTCPS_3_TTC_CLK_CLKSRC 0
+
+#define XPAR_XTTCPS_4_DEVICE_ID XPAR_PS8_TTC_4_DEVICE_ID
+#define XPAR_XTTCPS_4_BASEADDR 0xFF120004
+#define XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ 50000000
+#define XPAR_XTTCPS_4_TTC_CLK_CLKSRC 0
+
+#define XPAR_XTTCPS_5_DEVICE_ID XPAR_PS8_TTC_5_DEVICE_ID
+#define XPAR_XTTCPS_5_BASEADDR 0xFF120008
+#define XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ 50000000
+#define XPAR_XTTCPS_5_TTC_CLK_CLKSRC 0
+
+/* Canonical definitions for peripheral PS8_TTC_2 */
+#define XPAR_XTTCPS_6_DEVICE_ID XPAR_PS8_TTC_6_DEVICE_ID
+#define XPAR_XTTCPS_6_BASEADDR 0xFF130000
+#define XPAR_XTTCPS_6_TTC_CLK_FREQ_HZ 50000000
+#define XPAR_XTTCPS_6_TTC_CLK_CLKSRC 0
+
+#define XPAR_XTTCPS_7_DEVICE_ID XPAR_PS8_TTC_7_DEVICE_ID
+#define XPAR_XTTCPS_7_BASEADDR 0xFF130004
+#define XPAR_XTTCPS_7_TTC_CLK_FREQ_HZ 50000000
+#define XPAR_XTTCPS_7_TTC_CLK_CLKSRC 0
+
+#define XPAR_XTTCPS_8_DEVICE_ID XPAR_PS8_TTC_8_DEVICE_ID
+#define XPAR_XTTCPS_8_BASEADDR 0xFF130008
+#define XPAR_XTTCPS_8_TTC_CLK_FREQ_HZ 50000000
+#define XPAR_XTTCPS_8_TTC_CLK_CLKSRC 0
+
+/* Canonical definitions for peripheral PS8_TTC_3 */
+#define XPAR_XTTCPS_9_DEVICE_ID XPAR_PS8_TTC_9_DEVICE_ID
+#define XPAR_XTTCPS_9_BASEADDR 0xFF140000
+#define XPAR_XTTCPS_9_TTC_CLK_FREQ_HZ 50000000
+#define XPAR_XTTCPS_9_TTC_CLK_CLKSRC 0
+
+#define XPAR_XTTCPS_10_DEVICE_ID XPAR_PS8_TTC_10_DEVICE_ID
+#define XPAR_XTTCPS_10_BASEADDR 0xFF140004
+#define XPAR_XTTCPS_10_TTC_CLK_FREQ_HZ 50000000
+#define XPAR_XTTCPS_10_TTC_CLK_CLKSRC 0
+
+#define XPAR_XTTCPS_11_DEVICE_ID XPAR_PS8_TTC_11_DEVICE_ID
+#define XPAR_XTTCPS_11_BASEADDR 0xFF140008
+#define XPAR_XTTCPS_11_TTC_CLK_FREQ_HZ 50000000
+#define XPAR_XTTCPS_11_TTC_CLK_CLKSRC 0
+
+
+/******************************************************************/
+
+/* Definitions for driver UARTPS */
+#define XPAR_XUARTPS_NUM_INSTANCES 2
+
+/* Definitions for peripheral PS8_UART_0 */
+#define XPAR_PS8_UART_0_DEVICE_ID 0
+#define XPAR_PS8_UART_0_BASEADDR 0xFF000000
+#define XPAR_PS8_UART_0_HIGHADDR 0xFF000FFF
+#define XPAR_PS8_UART_0_UART_CLK_FREQ_HZ 100000000
+#define XPAR_PS8_UART_0_HAS_MODEM FALSE
+
+
+/* Definitions for peripheral PS8_UART_1 */
+#define XPAR_PS8_UART_1_DEVICE_ID 1
+#define XPAR_PS8_UART_1_BASEADDR 0xFF010000
+#define XPAR_PS8_UART_1_HIGHADDR 0xFF010FFF
+#define XPAR_PS8_UART_1_UART_CLK_FREQ_HZ 100000000
+#define XPAR_PS8_UART_1_HAS_MODEM FALSE
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS8_UART_0 */
+#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS8_UART_0_DEVICE_ID
+#define XPAR_XUARTPS_0_BASEADDR 0xFF000000
+#define XPAR_XUARTPS_0_HIGHADDR 0xFF000FFF
+#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 100000000
+#define XPAR_XUARTPS_0_HAS_MODEM FALSE
+
+/* Canonical definitions for peripheral PS8_UART_1 */
+#define XPAR_XUARTPS_1_DEVICE_ID XPAR_PS8_UART_1_DEVICE_ID
+#define XPAR_XUARTPS_1_BASEADDR 0xFF010000
+#define XPAR_XUARTPS_1_HIGHADDR 0xFF010FFF
+#define XPAR_XUARTPS_1_UART_CLK_FREQ_HZ 100000000
+#define XPAR_XUARTPS_1_HAS_MODEM FALSE
+
+
+/******************************************************************/
+
+/* Definitions for driver WDTPS */
+#define XPAR_XWDTPS_NUM_INSTANCES 2
+
+/* Definitions for peripheral PS8_WDT_0 */
+#define XPAR_PS8_WDT_0_DEVICE_ID 0
+#define XPAR_PS8_WDT_0_BASEADDR 0xFF150000
+#define XPAR_PS8_WDT_0_HIGHADDR 0xFF150FFF
+#define XPAR_PS8_WDT_0_WDT_CLK_FREQ_HZ 50000000
+
+
+/* Definitions for peripheral PS8_WDT_1 */
+#define XPAR_PS8_WDT_1_DEVICE_ID 1
+#define XPAR_PS8_WDT_1_BASEADDR 0xFD4D0000
+#define XPAR_PS8_WDT_1_HIGHADDR 0xFD4D0FFF
+#define XPAR_PS8_WDT_1_WDT_CLK_FREQ_HZ 50000000
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS8_WDT_0 */
+#define XPAR_XWDTPS_0_DEVICE_ID XPAR_PS8_WDT_0_DEVICE_ID
+#define XPAR_XWDTPS_0_BASEADDR 0xFF150000
+#define XPAR_XWDTPS_0_HIGHADDR 0xFF150FFF
+#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 50000000
+
+/* Canonical definitions for peripheral PS8_WDT_1 */
+#define XPAR_XWDTPS_1_DEVICE_ID XPAR_PS8_WDT_1_DEVICE_ID
+#define XPAR_XWDTPS_1_BASEADDR 0xFD4D0000
+#define XPAR_XWDTPS_1_HIGHADDR 0xFD4D0FFF
+#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 50000000
+
+
+/******************************************************************/
+
+/* Xilinx FAT File System Library (XilFFs) User Settings */
+#define FILE_SYSTEM_INTERFACE_SD
+#define FILE_SYSTEM_INTERFACE_SD
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xparameters_ps.h b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xparameters_ps.h
--- /dev/null
@@ -0,0 +1,369 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xparameters_ps.h
+*
+* This file contains the address definitions for the hard peripherals
+* attached to the ARM Cortex R5 core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------- -------- ---------------------------------------------------
+* 5.00 pkp 02/29/14 Initial version
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XPARAMETERS_PS_H_
+#define _XPARAMETERS_PS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock
+ */
+
+/* Canonical definitions for DDR MEMORY */
+#define XPAR_DDR_MEM_BASEADDR 0x00000000
+#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFF
+
+/* Canonical definitions for Interrupts */
+#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID
+#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID
+#define XPAR_XUSBPS_0_INTR XPS_USB0_INT_ID
+#define XPAR_XUSBPS_1_INTR XPS_USB1_INT_ID
+#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID
+#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID
+#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID
+#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID
+#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID
+#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID
+#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID
+#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID
+#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
+#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID
+#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
+#define XPAR_XEMACPS_2_INTR XPS_GEM2_INT_ID
+#define XPAR_XEMACPS_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID
+#define XPAR_XEMACPS_3_INTR XPS_GEM3_INT_ID
+#define XPAR_XEMACPS_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID
+#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
+#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
+#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
+#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID
+#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
+#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID
+#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID
+#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
+#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
+#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
+#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID
+#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID
+#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID
+#define XPAR_XTTCPS_6_INTR XPS_TTC2_0_INT_ID
+#define XPAR_XTTCPS_7_INTR XPS_TTC2_1_INT_ID
+#define XPAR_XTTCPS_8_INTR XPS_TTC2_2_INT_ID
+#define XPAR_XTTCPS_9_INTR XPS_TTC3_0_INT_ID
+#define XPAR_XTTCPS_10_INTR XPS_TTC3_1_INT_ID
+#define XPAR_XTTCPS_11_INTR XPS_TTC3_2_INT_ID
+#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID
+#define XPAR_XNANDPS8_0_INTR XPS_NAND_INT_ID
+
+
+#define XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR
+#define XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR
+
+
+
+/* Canonical definitions for DMAC */
+
+
+/* Canonical definitions for WDT */
+
+/* Canonical definitions for SLCR */
+#define XPAR_XSLCR_NUM_INSTANCES 1
+#define XPAR_XSLCR_0_DEVICE_ID 0
+#define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR
+
+/* Canonical definitions for SCU GIC */
+#define XPAR_SCUGIC_NUM_INSTANCES 1
+#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0
+#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x1000)
+#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x2000)
+#define XPAR_SCUGIC_ACK_BEFORE 0
+
+/* Canonical definitions for Global Timer */
+#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1
+#define XPAR_GLOBAL_TMR_DEVICE_ID 0
+#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x200)
+#define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID
+
+
+/* Xilinx Parallel Flash Library (XilFlash) User Settings */
+#define XPAR_AXI_EMC
+
+
+#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ
+
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock. These have been put for bacwards compatibilty
+ */
+
+#define XPS_PERIPHERAL_BASEADDR 0xE0000000
+#define XPS_UART0_BASEADDR 0xFF000000
+#define XPS_UART1_BASEADDR 0xFF010000
+#define XPS_I2C0_BASEADDR 0xFF020000
+#define XPS_I2C1_BASEADDR 0xFF030000
+#define XPS_SPI0_BASEADDR 0xFF040000
+#define XPS_SPI1_BASEADDR 0xFF050000
+#define XPS_CAN0_BASEADDR 0xFF060000
+#define XPS_CAN1_BASEADDR 0xFF070000
+#define XPS_GPIO_BASEADDR 0xFF0A0000
+#define XPS_GEM0_BASEADDR 0xFF0B0000
+#define XPS_GEM1_BASEADDR 0xFF0C0000
+#define XPS_GEM2_BASEADDR 0xFF0D0000
+#define XPS_GEM3_BASEADDR 0xFF0E0000
+#define XPS_QSPI_BASEADDR 0xFF0F0000
+#define XPS_NAND_BASEADDR 0xFF100000
+#define XPS_TTC0_BASEADDR 0xFF110000
+#define XPS_TTC1_BASEADDR 0xFF120000
+#define XPS_TTC2_BASEADDR 0xFF130000
+#define XPS_TTC3_BASEADDR 0xFF140000
+#define XPS_WDT_BASEADDR 0xFF150000
+#define XPS_SDIO0_BASEADDR 0xFF160000
+#define XPS_SDIO1_BASEADDR 0xFF170000
+#define XPS_SYS_CTRL_BASEADDR 0xFF180000
+#define XPAR_XNANDPS8_0_BASEADDR 0xFF100000
+
+
+#define XPS_PARPORT_CRTL_BASEADDR 0x0000000
+#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000
+#define XPS_PARPORT0_BASEADDR 0xE2000000
+#define XPS_PARPORT1_BASEADDR 0xE4000000
+#define XPS_QSPI_LINEAR_BASEADDR 0xF0000000
+#define XPS_DMAC0_NON_SEC_BASEADDR 0xFE507000
+#define XPS_DMAC0_SEC_BASEADDR 0xFE5F0000
+#define XPS_DDR_CTRL_BASEADDR 0xF8006000
+#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000
+#define XPS_AFI0_BASEADDR 0xF8008000
+#define XPS_AFI1_BASEADDR 0xF8009000
+#define XPS_AFI2_BASEADDR 0xF800A000
+#define XPS_AFI3_BASEADDR 0xF800B000
+#define XPS_OCM_BASEADDR 0xF800C000
+#define XPS_EFUSE_BASEADDR 0xF800D000
+#define XPS_CORESIGHT_BASEADDR 0xF8800000
+#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000
+#define XPS_SCU_PERIPH_BASE 0xF9000000
+#define XPS_L2CC_BASEADDR 0xFD3FD000
+#define XPS_SAM_RAM_BASEADDR 0xFFFC0000
+#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000
+#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000
+#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000
+#define XPS_PERIPH_APB_BASEADDR 0xF8000000
+#define XPS_USB0_BASEADDR 0xE0002000
+#define XPS_USB1_BASEADDR 0xE0003000
+
+
+/* Shared Peripheral Interrupts (SPI) */
+/* Shared Peripheral Interrupts (SPI) */
+
+#define XPS_USB1_INT_ID 76
+#define XPS_USB0_INT_ID 53
+
+#define XPS_NAND_INT_ID (32 + 32)
+
+#define XPS_FPGA1_INT_ID 62
+#define XPS_FPGA2_INT_ID 63
+#define XPS_FPGA3_INT_ID 64
+#define XPS_FPGA4_INT_ID 65
+#define XPS_FPGA5_INT_ID 66
+#define XPS_FPGA6_INT_ID 67
+#define XPS_FPGA7_INT_ID 68
+#define XPS_DMA4_INT_ID 72
+#define XPS_DMA5_INT_ID 73
+#define XPS_DMA6_INT_ID 74
+#define XPS_DMA7_INT_ID 75
+#define XPS_FPGA8_INT_ID 84
+#define XPS_FPGA9_INT_ID 85
+#define XPS_FPGA10_INT_ID 86
+#define XPS_FPGA11_INT_ID 87
+#define XPS_FPGA12_INT_ID 88
+#define XPS_FPGA13_INT_ID 89
+#define XPS_FPGA14_INT_ID 90
+#define XPS_FPGA15_INT_ID 91
+
+
+#define XPS_OCMINTR_INT_ID (28 + 32)
+#define XPS_QSPI_INT_ID (33 + 32)
+#define XPS_GPIO_INT_ID (34 + 32)
+#define XPS_WDT_INT_ID (106 + 32)
+#define XPS_LP_WDT_INT_ID (69 + 32)
+#define XPS_TTC0_0_INT_ID (53 + 32)
+#define XPS_TTC0_1_INT_ID (54 + 32)
+#define XPS_TTC0_2_INT_ID (55 + 32)
+#define XPS_SDIO0_INT_ID (65 + 32)
+#define XPS_I2C0_INT_ID (35 + 32)
+#define XPS_SPI0_INT_ID (37 + 32)
+#define XPS_UART0_INT_ID (39 + 32)
+#define XPS_CAN0_INT_ID (41 + 32)
+
+/* FIXME */
+//#define XPS_FPGA0_INT_ID 100
+
+#define XPS_TTC1_0_INT_ID (56 + 32)
+#define XPS_TTC1_1_INT_ID (57 + 32)
+#define XPS_TTC1_2_INT_ID (58 + 32)
+#define XPS_TTC2_0_INT_ID (59 + 32)
+#define XPS_TTC2_1_INT_ID (60 + 32)
+#define XPS_TTC2_2_INT_ID (61 + 32)
+#define XPS_TTC3_0_INT_ID (62 + 32)
+#define XPS_TTC3_1_INT_ID (63 + 32)
+#define XPS_TTC3_2_INT_ID (64 + 32)
+#define XPS_SDIO1_INT_ID (66 + 32)
+#define XPS_I2C1_INT_ID (36 + 32)
+#define XPS_SPI1_INT_ID (38 + 32)
+#define XPS_UART1_INT_ID (40 + 32)
+#define XPS_CAN1_INT_ID (42 + 32)
+#define XPS_GEM0_INT_ID (73 + 32)
+#define XPS_GEM0_WAKE_INT_ID (74 + 32)
+#define XPS_GEM1_INT_ID (75 + 32)
+#define XPS_GEM1_WAKE_INT_ID (76 + 32)
+#define XPS_GEM2_INT_ID (77 + 32)
+#define XPS_GEM2_WAKE_INT_ID (78 + 32)
+#define XPS_GEM3_INT_ID (79 + 32)
+#define XPS_GEM3_WAKE_INT_ID (80 + 32)
+
+/* Private Peripheral Interrupts (PPI) */
+//#define XPS_GLOBAL_TMR_INT_ID 27 /* SCU Global Timer interrupt */
+//#define XPS_FIQ_INT_ID 28 /* FIQ from FPGA fabric */
+//#define XPS_SCU_TMR_INT_ID 29 /* SCU Private Timer interrupt */
+//#define XPS_SCU_WDT_INT_ID 30 /* SCU Private WDT interrupt */
+//#define XPS_IRQ_INT_ID 31 /* IRQ from FPGA fabric */
+
+
+/* REDEFINES for TEST APP */
+/* Definitions for UART */
+#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID
+#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID
+#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID
+#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID
+#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID
+#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID
+#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID
+#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID
+#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID
+#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID
+#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID
+#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID
+#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
+#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID
+#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
+#define XPAR_PS7_ETHERNET_2_INTR XPS_GEM2_INT_ID
+#define XPAR_PS7_ETHERNET_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID
+#define XPAR_PS7_ETHERNET_3_INTR XPS_GEM3_INT_ID
+#define XPAR_PS7_ETHERNET_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID
+
+#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID
+#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID
+#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID
+#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
+#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID
+
+#define XPAR_XADCPS_NUM_INSTANCES 1
+#define XPAR_XADCPS_0_DEVICE_ID 0
+#define XPAR_XADCPS_0_BASEADDR (0xF8007000)
+#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
+
+/* For backwards compatibilty */
+#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
+#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
+#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
+#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
+#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
+
+#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
+
+#ifdef XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ
+#endif
+
+#ifdef XPAR_CPU_CORTEXR5_1_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXR5_1_CPU_CLK_FREQ_HZ
+#endif
+
+#define XPAR_SCUTIMER_DEVICE_ID 0
+#define XPAR_SCUWDT_DEVICE_ID 0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xpm_counter.c b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xpm_counter.c
--- /dev/null
@@ -0,0 +1,302 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpm_counter.c
+*
+* This file contains APIs for configuring and controlling the Cortex-R5
+* Performance Monitor Events. For more information about the event counters,
+* see xpm_counter.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00 pkp 02/10/14 Initial version
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xpm_counter.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+typedef const u32 PmcrEventCfg[XPM_CTRCOUNT];
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions *****************************/
+
+static PmcrEventCfg PmcrEvents[] = {
+ {
+ XPM_EVENT_SOFTINCR,
+ XPM_EVENT_INSRFETCH_CACHEREFILL,
+ XPM_EVENT_INSTRFECT_TLBREFILL,
+ XPM_EVENT_DATA_CACHEREFILL,
+ XPM_EVENT_DATA_CACHEACCESS,
+ XPM_EVENT_DATA_TLBREFILL
+ },
+ {
+ XPM_EVENT_DATA_READS,
+ XPM_EVENT_DATA_WRITE,
+ XPM_EVENT_EXCEPTION,
+ XPM_EVENT_EXCEPRETURN,
+ XPM_EVENT_CHANGECONTEXT,
+ XPM_EVENT_SW_CHANGEPC
+ },
+ {
+ XPM_EVENT_IMMEDBRANCH,
+ XPM_EVENT_UNALIGNEDACCESS,
+ XPM_EVENT_BRANCHMISS,
+ XPM_EVENT_CLOCKCYCLES,
+ XPM_EVENT_BRANCHPREDICT,
+ XPM_EVENT_JAVABYTECODE
+ },
+ {
+ XPM_EVENT_SWJAVABYTECODE,
+ XPM_EVENT_JAVABACKBRANCH,
+ XPM_EVENT_COHERLINEMISS,
+ XPM_EVENT_COHERLINEHIT,
+ XPM_EVENT_INSTRSTALL,
+ XPM_EVENT_DATASTALL
+ },
+ {
+ XPM_EVENT_MAINTLBSTALL,
+ XPM_EVENT_STREXPASS,
+ XPM_EVENT_STREXFAIL,
+ XPM_EVENT_DATAEVICT,
+ XPM_EVENT_NODISPATCH,
+ XPM_EVENT_ISSUEEMPTY
+ },
+ {
+ XPM_EVENT_INSTRRENAME,
+ XPM_EVENT_PREDICTFUNCRET,
+ XPM_EVENT_MAINEXEC,
+ XPM_EVENT_SECEXEC,
+ XPM_EVENT_LDRSTR,
+ XPM_EVENT_FLOATRENAME
+ },
+ {
+ XPM_EVENT_NEONRENAME,
+ XPM_EVENT_PLDSTALL,
+ XPM_EVENT_WRITESTALL,
+ XPM_EVENT_INSTRTLBSTALL,
+ XPM_EVENT_DATATLBSTALL,
+ XPM_EVENT_INSTR_uTLBSTALL
+ },
+ {
+ XPM_EVENT_DATA_uTLBSTALL,
+ XPM_EVENT_DMB_STALL,
+ XPM_EVENT_INT_CLKEN,
+ XPM_EVENT_DE_CLKEN,
+ XPM_EVENT_INSTRISB,
+ XPM_EVENT_INSTRDSB
+ },
+ {
+ XPM_EVENT_INSTRDMB,
+ XPM_EVENT_EXTINT,
+ XPM_EVENT_PLE_LRC,
+ XPM_EVENT_PLE_LRS,
+ XPM_EVENT_PLE_FLUSH,
+ XPM_EVENT_PLE_CMPL
+ },
+ {
+ XPM_EVENT_PLE_OVFL,
+ XPM_EVENT_PLE_PROG,
+ XPM_EVENT_PLE_LRC,
+ XPM_EVENT_PLE_LRS,
+ XPM_EVENT_PLE_FLUSH,
+ XPM_EVENT_PLE_CMPL
+ },
+ {
+ XPM_EVENT_DATASTALL,
+ XPM_EVENT_INSRFETCH_CACHEREFILL,
+ XPM_EVENT_INSTRFECT_TLBREFILL,
+ XPM_EVENT_DATA_CACHEREFILL,
+ XPM_EVENT_DATA_CACHEACCESS,
+ XPM_EVENT_DATA_TLBREFILL
+ },
+};
+
+/************************** Function Prototypes ******************************/
+
+void Xpm_DisableEventCounters(void);
+void Xpm_EnableEventCounters (void);
+void Xpm_ResetEventCounters (void);
+
+/******************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* This function disables the Cortex R5 event counters.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void Xpm_DisableEventCounters(void)
+{
+ /* Disable the event counters */
+ mtcp(XREG_CP15_COUNT_ENABLE_CLR, 0x3f);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the Cortex R5 event counters.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void Xpm_EnableEventCounters(void)
+{
+ /* Enable the event counters */
+ mtcp(XREG_CP15_COUNT_ENABLE_SET, 0x3f);
+}
+
+/****************************************************************************/
+/**
+*
+* This function resets the Cortex R5 event counters.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void Xpm_ResetEventCounters(void)
+{
+ u32 Reg;
+
+#ifdef __GNUC__
+ Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL);
+#else
+ { register unsigned int C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL);
+ Reg = C15Reg; }
+#endif
+ Reg |= (1 << 2); /* reset event counters */
+ mtcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function configures the Cortex R5 event counters controller, with the
+* event codes, in a configuration selected by the user and enables the counters.
+*
+* @param PmcrCfg is configuration value based on which the event counters
+* are configured.
+* Use XPM_CNTRCFG* values defined in xpm_counter.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void Xpm_SetEvents(int PmcrCfg)
+{
+ u32 Counter;
+ const u32 *Ptr = PmcrEvents[PmcrCfg];
+
+ Xpm_DisableEventCounters();
+
+ for(Counter = 0; Counter < XPM_CTRCOUNT; Counter++) {
+
+ /* Selecet event counter */
+ mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
+
+ /* Set the event */
+ mtcp(XREG_CP15_EVENT_TYPE_SEL, Ptr[Counter]);
+ }
+
+ Xpm_ResetEventCounters();
+ Xpm_EnableEventCounters();
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables the event counters and returns the counter values.
+*
+* @param PmCtrValue is a pointer to an array of type u32 PmCtrValue[6].
+* It is an output parameter which is used to return the PM
+* counter values.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void Xpm_GetEventCounters(u32 *PmCtrValue)
+{
+ u32 Counter;
+
+ Xpm_DisableEventCounters();
+
+ for(Counter = 0; Counter < XPM_CTRCOUNT; Counter++) {
+
+ mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
+#ifdef __GNUC__
+ PmCtrValue[Counter] = mfcp(XREG_CP15_PERF_MONITOR_COUNT);
+#else
+ { register unsigned int Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT);
+ PmCtrValue[Counter] = Cp15Reg; }
+#endif
+ }
+}
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xpm_counter.h b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xpm_counter.h
--- /dev/null
@@ -0,0 +1,582 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpm_counter.h
+*
+* This header file contains APIs for configuring and controlling the Cortex-R5
+* Performance Monitor Events.
+* Cortex-R5 Performance Monitor has 6 event counters which can be used to
+* count a variety of events described in Coretx-R5 TRM. This file defines
+* configurations, where value configures the event counters to count a
+* set of events.
+*
+* Xpm_SetEvents can be used to set the event counters to count a set of events
+* and Xpm_GetEventCounters can be used to read the counter values.
+*
+* @note
+*
+* This file doesn't handle the Cortex-R5 cycle counter, as the cycle counter is
+* being used for time keeping.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00 pkp 02/10/14 Initial version
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XPMCOUNTER_H /* prevent circular inclusions */
+#define XPMCOUNTER_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include <stdint.h>
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/* Number of performance counters */
+#define XPM_CTRCOUNT 6
+
+/* The following constants define the Cortex-R5 Performance Monitor Events */
+
+/*
+ * Software increment. The register is incremented only on writes to the
+ * Software Increment Register
+ */
+#define XPM_EVENT_SOFTINCR 0x00
+
+/*
+ * Instruction fetch that causes a refill at (at least) the lowest level(s) of
+ * instruction or unified cache. Includes the speculative linefills in the
+ * count
+ */
+#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01
+
+/*
+ * Instruction fetch that causes a TLB refill at (at least) the lowest level of
+ * TLB. Includes the speculative requests in the count
+ */
+#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02
+
+/*
+ * Data read or write operation that causes a refill at (at least) the lowest
+ * level(s)of data or unified cache. Counts the number of allocations performed
+ * in the Data Cache due to a read or a write
+ */
+#define XPM_EVENT_DATA_CACHEREFILL 0x03
+
+/*
+ * Data read or write operation that causes a cache access at (at least) the
+ * lowest level(s) of data or unified cache. This includes speculative reads
+ */
+#define XPM_EVENT_DATA_CACHEACCESS 0x04
+
+/*
+ * Data read or write operation that causes a TLB refill at (at least) the
+ * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI,
+ * CP15 Cache operation by MVA and CP15 VA to PA operations
+ */
+#define XPM_EVENT_DATA_TLBREFILL 0x05
+
+/*
+ * Data read architecturally executed. Counts the number of data read
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted LDR/LDM, as well as the reads due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_READS 0x06
+
+/*
+ * Data write architecturally executed. Counts the number of data write
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted STR/STM, as well as the writes due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_WRITE 0x07
+
+/* Exception taken. Counts the number of exceptions architecturally taken.*/
+#define XPM_EVENT_EXCEPTION 0x09
+
+/* Exception return architecturally executed.*/
+#define XPM_EVENT_EXCEPRETURN 0x0A
+
+/*
+ * Change to ContextID retired. Counts the number of instructions
+ * architecturally executed writing into the ContextID Register
+ */
+#define XPM_EVENT_CHANGECONTEXT 0x0B
+
+/*
+ * Software change of PC, except by an exception, architecturally executed.
+ * Count the number of PC changes architecturally executed, excluding the PC
+ * changes due to taken exceptions
+ */
+#define XPM_EVENT_SW_CHANGEPC 0x0C
+
+/*
+ * Immediate branch architecturally executed (taken or not taken). This includes
+ * the branches which are flushed due to a previous load/store which aborts
+ * late
+ */
+#define XPM_EVENT_IMMEDBRANCH 0x0D
+
+/*
+ * Unaligned access architecturally executed. Counts the number of aborted
+ * unaligned accessed architecturally executed, and the number of not-aborted
+ * unaligned accesses, including the speculative ones
+ */
+#define XPM_EVENT_UNALIGNEDACCESS 0x0F
+
+/*
+ * Branch mispredicted/not predicted. Counts the number of mispredicted or
+ * not-predicted branches executed. This includes the branches which are flushed
+ * due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHMISS 0x10
+
+/*
+ * Counts clock cycles when the Cortex-R5 processor is not in WFE/WFI. This
+ * event is not exported on the PMUEVENT bus
+ */
+#define XPM_EVENT_CLOCKCYCLES 0x11
+
+/*
+ * Branches or other change in program flow that could have been predicted by
+ * the branch prediction resources of the processor. This includes the branches
+ * which are flushed due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHPREDICT 0x12
+
+/*
+ * Java bytecode execute. Counts the number of Java bytecodes being decoded,
+ * including speculative ones
+ */
+#define XPM_EVENT_JAVABYTECODE 0x40
+
+/*
+ * Software Java bytecode executed. Counts the number of software java bytecodes
+ * being decoded, including speculative ones
+ */
+#define XPM_EVENT_SWJAVABYTECODE 0x41
+
+/*
+ * Jazelle backward branches executed. Counts the number of Jazelle taken
+ * branches being executed. This includes the branches which are flushed due
+ * to a previous load/store which aborts late
+ */
+#define XPM_EVENT_JAVABACKBRANCH 0x42
+
+/*
+ * Coherent linefill miss Counts the number of coherent linefill requests
+ * performed by the Cortex-R5 processor which also miss in all the other
+ * Cortex-R5 processors, meaning that the request is sent to the external
+ * memory
+ */
+#define XPM_EVENT_COHERLINEMISS 0x50
+
+/*
+ * Coherent linefill hit. Counts the number of coherent linefill requests
+ * performed by the Cortex-R5 processor which hit in another Cortex-R5
+ * processor, meaning that the linefill data is fetched directly from the
+ * relevant Cortex-R5 cache
+ */
+#define XPM_EVENT_COHERLINEHIT 0x51
+
+/*
+ * Instruction cache dependent stall cycles. Counts the number of cycles where
+ * the processor is ready to accept new instructions, but does not receive any
+ * due to the instruction side not being able to provide any and the
+ * instruction cache is currently performing at least one linefill
+ */
+#define XPM_EVENT_INSTRSTALL 0x60
+
+/*
+ * Data cache dependent stall cycles. Counts the number of cycles where the core
+ * has some instructions that it cannot issue to any pipeline, and the Load
+ * Store unit has at least one pending linefill request, and no pending
+ */
+#define XPM_EVENT_DATASTALL 0x61
+
+/*
+ * Main TLB miss stall cycles. Counts the number of cycles where the processor
+ * is stalled waiting for the completion of translation table walks from the
+ * main TLB. The processor stalls can be due to the instruction side not being
+ * able to provide the instructions, or to the data side not being able to
+ * provide the necessary data, due to them waiting for the main TLB translation
+ * table walk to complete
+ */
+#define XPM_EVENT_MAINTLBSTALL 0x62
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * passed
+ */
+#define XPM_EVENT_STREXPASS 0x63
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * failed
+ */
+#define XPM_EVENT_STREXFAIL 0x64
+
+/*
+ * Data eviction. Counts the number of eviction requests due to a linefill in
+ * the data cache
+ */
+#define XPM_EVENT_DATAEVICT 0x65
+
+/*
+ * Counts the number of cycles where the issue stage does not dispatch any
+ * instruction because it is empty or cannot dispatch any instructions
+ */
+#define XPM_EVENT_NODISPATCH 0x66
+
+/*
+ * Counts the number of cycles where the issue stage is empty
+ */
+#define XPM_EVENT_ISSUEEMPTY 0x67
+
+/*
+ * Counts the number of instructions going through the Register Renaming stage.
+ * This number is an approximate number of the total number of instructions
+ * speculatively executed, and even more approximate of the total number of
+ * instructions architecturally executed. The approximation depends mainly on
+ * the branch misprediction rate.
+ * The renaming stage can handle two instructions in the same cycle so the event
+ * is two bits long:
+ * - b00 no instructions renamed
+ * - b01 one instruction renamed
+ * - b10 two instructions renamed
+ */
+#define XPM_EVENT_INSTRRENAME 0x68
+
+/*
+ * Counts the number of procedure returns whose condition codes do not fail,
+ * excluding all returns from exception. This count includes procedure returns
+ * which are flushed due to a previous load/store which aborts late.
+ * Only the following instructions are reported:
+ * - BX R14
+ * - MOV PC LR
+ * - POP {..,pc}
+ * - LDR pc,[sp],#offset
+ * The following instructions are not reported:
+ * - LDMIA R9!,{..,PC} (ThumbEE state only)
+ * - LDR PC,[R9],#offset (ThumbEE state only)
+ * - BX R0 (Rm != R14)
+ * - MOV PC,R0 (Rm != R14)
+ * - LDM SP,{...,PC} (writeback not specified)
+ * - LDR PC,[SP,#offset] (wrong addressing mode)
+ */
+#define XPM_EVENT_PREDICTFUNCRET 0x6E
+
+/*
+ * Counts the number of instructions being executed in the main execution
+ * pipeline of the processor, the multiply pipeline and arithmetic logic unit
+ * pipeline. The counted instructions are still speculative
+ */
+#define XPM_EVENT_MAINEXEC 0x70
+
+/*
+ * Counts the number of instructions being executed in the processor second
+ * execution pipeline (ALU). The counted instructions are still speculative
+ */
+#define XPM_EVENT_SECEXEC 0x71
+
+/*
+ * Counts the number of instructions being executed in the Load/Store unit. The
+ * counted instructions are still speculative
+ */
+#define XPM_EVENT_LDRSTR 0x72
+
+/*
+ * Counts the number of Floating-point instructions going through the Register
+ * Rename stage. Instructions are still speculative in this stage.
+ *Two floating-point instructions can be renamed in the same cycle so the event
+ * is two bitslong:
+ *0b00 no floating-point instruction renamed
+ *0b01 one floating-point instruction renamed
+ *0b10 two floating-point instructions renamed
+ */
+#define XPM_EVENT_FLOATRENAME 0x73
+
+/*
+ * Counts the number of Neon instructions going through the Register Rename
+ * stage.Instructions are still speculative in this stage.
+ * Two NEON instructions can be renamed in the same cycle so the event is two
+ * bits long:
+ *0b00 no NEON instruction renamed
+ *0b01 one NEON instruction renamed
+ *0b10 two NEON instructions renamed
+ */
+#define XPM_EVENT_NEONRENAME 0x74
+
+/*
+ * Counts the number of cycles where the processor is stalled because PLD slots
+ * are all full
+ */
+#define XPM_EVENT_PLDSTALL 0x80
+
+/*
+ * Counts the number of cycles when the processor is stalled and the data side
+ * is stalled too because it is full and executing writes to the external
+ * memory
+ */
+#define XPM_EVENT_WRITESTALL 0x81
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the instruction side
+ */
+#define XPM_EVENT_INSTRTLBSTALL 0x82
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the data side
+ */
+#define XPM_EVENT_DATATLBSTALL 0x83
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the instruction
+ * side. This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_INSTR_uTLBSTALL 0x84
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the data side.
+ * This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_DATA_uTLBSTALL 0x85
+
+/*
+ * Counts the number of stall cycles because of the execution of a DMB memory
+ * barrier. This includes all DMB instructions being executed, even
+ * speculatively
+ */
+#define XPM_EVENT_DMB_STALL 0x86
+
+/*
+ * Counts the number of cycles during which the integer core clock is enabled
+ */
+#define XPM_EVENT_INT_CLKEN 0x8A
+
+/*
+ * Counts the number of cycles during which the Data Engine clock is enabled
+ */
+#define XPM_EVENT_DE_CLKEN 0x8B
+
+/*
+ * Counts the number of ISB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRISB 0x90
+
+/*
+ * Counts the number of DSB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRDSB 0x91
+
+/*
+ * Counts the number of DMB instructions speculatively executed
+ */
+#define XPM_EVENT_INSTRDMB 0x92
+
+/*
+ * Counts the number of external interrupts executed by the processor
+ */
+#define XPM_EVENT_EXTINT 0x93
+
+/*
+ * PLE cache line request completed
+ */
+#define XPM_EVENT_PLE_LRC 0xA0
+
+/*
+ * PLE cache line request skipped
+ */
+#define XPM_EVENT_PLE_LRS 0xA1
+
+/*
+ * PLE FIFO flush
+ */
+#define XPM_EVENT_PLE_FLUSH 0xA2
+
+/*
+ * PLE request complete
+ */
+#define XPM_EVENT_PLE_CMPL 0xA3
+
+/*
+ * PLE FIFO overflow
+ */
+#define XPM_EVENT_PLE_OVFL 0xA4
+
+/*
+ * PLE request programmed
+ */
+#define XPM_EVENT_PLE_PROG 0xA5
+
+/*
+ * The following constants define the configurations for Cortex-R5 Performance
+ * Monitor Events. Each configuration configures the event counters for a set
+ * of events.
+ * -----------------------------------------------
+ * Config PmCtr0... PmCtr5
+ * -----------------------------------------------
+ * XPM_CNTRCFG1 { XPM_EVENT_SOFTINCR,
+ * XPM_EVENT_INSRFETCH_CACHEREFILL,
+ * XPM_EVENT_INSTRFECT_TLBREFILL,
+ * XPM_EVENT_DATA_CACHEREFILL,
+ * XPM_EVENT_DATA_CACHEACCESS,
+ * XPM_EVENT_DATA_TLBREFILL }
+ *
+ * XPM_CNTRCFG2 { XPM_EVENT_DATA_READS,
+ * XPM_EVENT_DATA_WRITE,
+ * XPM_EVENT_EXCEPTION,
+ * XPM_EVENT_EXCEPRETURN,
+ * XPM_EVENT_CHANGECONTEXT,
+ * XPM_EVENT_SW_CHANGEPC }
+ *
+ * XPM_CNTRCFG3 { XPM_EVENT_IMMEDBRANCH,
+ * XPM_EVENT_UNALIGNEDACCESS,
+ * XPM_EVENT_BRANCHMISS,
+ * XPM_EVENT_CLOCKCYCLES,
+ * XPM_EVENT_BRANCHPREDICT,
+ * XPM_EVENT_JAVABYTECODE }
+ *
+ * XPM_CNTRCFG4 { XPM_EVENT_SWJAVABYTECODE,
+ * XPM_EVENT_JAVABACKBRANCH,
+ * XPM_EVENT_COHERLINEMISS,
+ * XPM_EVENT_COHERLINEHIT,
+ * XPM_EVENT_INSTRSTALL,
+ * XPM_EVENT_DATASTALL }
+ *
+ * XPM_CNTRCFG5 { XPM_EVENT_MAINTLBSTALL,
+ * XPM_EVENT_STREXPASS,
+ * XPM_EVENT_STREXFAIL,
+ * XPM_EVENT_DATAEVICT,
+ * XPM_EVENT_NODISPATCH,
+ * XPM_EVENT_ISSUEEMPTY }
+ *
+ * XPM_CNTRCFG6 { XPM_EVENT_INSTRRENAME,
+ * XPM_EVENT_PREDICTFUNCRET,
+ * XPM_EVENT_MAINEXEC,
+ * XPM_EVENT_SECEXEC,
+ * XPM_EVENT_LDRSTR,
+ * XPM_EVENT_FLOATRENAME }
+ *
+ * XPM_CNTRCFG7 { XPM_EVENT_NEONRENAME,
+ * XPM_EVENT_PLDSTALL,
+ * XPM_EVENT_WRITESTALL,
+ * XPM_EVENT_INSTRTLBSTALL,
+ * XPM_EVENT_DATATLBSTALL,
+ * XPM_EVENT_INSTR_uTLBSTALL }
+ *
+ * XPM_CNTRCFG8 { XPM_EVENT_DATA_uTLBSTALL,
+ * XPM_EVENT_DMB_STALL,
+ * XPM_EVENT_INT_CLKEN,
+ * XPM_EVENT_DE_CLKEN,
+ * XPM_EVENT_INSTRISB,
+ * XPM_EVENT_INSTRDSB }
+ *
+ * XPM_CNTRCFG9 { XPM_EVENT_INSTRDMB,
+ * XPM_EVENT_EXTINT,
+ * XPM_EVENT_PLE_LRC,
+ * XPM_EVENT_PLE_LRS,
+ * XPM_EVENT_PLE_FLUSH,
+ * XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG10 { XPM_EVENT_PLE_OVFL,
+ * XPM_EVENT_PLE_PROG,
+ * XPM_EVENT_PLE_LRC,
+ * XPM_EVENT_PLE_LRS,
+ * XPM_EVENT_PLE_FLUSH,
+ * XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG11 { XPM_EVENT_DATASTALL,
+ * XPM_EVENT_INSRFETCH_CACHEREFILL,
+ * XPM_EVENT_INSTRFECT_TLBREFILL,
+ * XPM_EVENT_DATA_CACHEREFILL,
+ * XPM_EVENT_DATA_CACHEACCESS,
+ * XPM_EVENT_DATA_TLBREFILL }
+ */
+#define XPM_CNTRCFG1 0
+#define XPM_CNTRCFG2 1
+#define XPM_CNTRCFG3 2
+#define XPM_CNTRCFG4 3
+#define XPM_CNTRCFG5 4
+#define XPM_CNTRCFG6 5
+#define XPM_CNTRCFG7 6
+#define XPM_CNTRCFG8 7
+#define XPM_CNTRCFG9 8
+#define XPM_CNTRCFG10 9
+#define XPM_CNTRCFG11 10
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/* Interface fuctions to access perfromance counters from abstraction layer */
+void Xpm_SetEvents(int PmcrCfg);
+void Xpm_GetEventCounters(u32 *PmCtrValue);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xpseudo_asm.h b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xpseudo_asm.h
--- /dev/null
@@ -0,0 +1,64 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm.h
+*
+* This header file contains macros for using inline assembler code.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00 pkp 02/10/14 Initial version
+* </pre>
+*
+******************************************************************************/
+#include "xreg_cortexr5.h"
+#ifdef __GNUC__
+ #include "xpseudo_asm_gcc.h"
+#else
+ #include "xpseudo_asm_rvct.h"
+#endif
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xpseudo_asm_gcc.h b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xpseudo_asm_gcc.h
--- /dev/null
@@ -0,0 +1,185 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm_gcc.h
+*
+* This header file contains macros for using inline assembler code. It is
+* written specifically for the GNU compiler.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 pkp 05/29/14 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */
+#define XPSEUDO_ASM_GCC_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/* necessary for pre-processor */
+#define stringify(s) tostring(s)
+#define tostring(s) #s
+
+/* pseudo assembler instructions */
+#define mfcpsr() ({unsigned int rval; \
+ __asm__ __volatile__(\
+ "mrs %0, cpsr\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+
+#define mtcpsr(v) __asm__ __volatile__(\
+ "msr cpsr,%0\n"\
+ : : "r" (v)\
+ )
+
+#define cpsiei() __asm__ __volatile__("cpsie i\n")
+#define cpsidi() __asm__ __volatile__("cpsid i\n")
+
+#define cpsief() __asm__ __volatile__("cpsie f\n")
+#define cpsidf() __asm__ __volatile__("cpsid f\n")
+
+
+
+#define mtgpr(rn, v) __asm__ __volatile__(\
+ "mov r" stringify(rn) ", %0 \n"\
+ : : "r" (v)\
+ )
+
+#define mfgpr(rn) ({unsigned int rval; \
+ __asm__ __volatile__(\
+ "mov %0,r" stringify(rn) "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
+
+
+/* Memory Operations */
+#define ldr(adr) ({unsigned long rval; \
+ __asm__ __volatile__(\
+ "ldr %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#define ldrb(adr) ({unsigned char rval; \
+ __asm__ __volatile__(\
+ "ldrb %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#define str(adr, val) __asm__ __volatile__(\
+ "str %0,[%1]\n"\
+ : : "r" (val), "r" (adr)\
+ )
+
+#define strb(adr, val) __asm__ __volatile__(\
+ "strb %0,[%1]\n"\
+ : : "r" (val), "r" (adr)\
+ )
+
+/* Count leading zeroes (clz) */
+#define clz(arg) ({unsigned char rval; \
+ __asm__ __volatile__(\
+ "clz %0,%1"\
+ : "=r" (rval) : "r" (arg)\
+ );\
+ rval;\
+ })
+
+/* CP15 operations */
+#define mtcp(rn, v) __asm__ __volatile__(\
+ "mcr " rn "\n"\
+ : : "r" (v)\
+ );
+
+#define mfcp(rn) ({unsigned int rval; \
+ __asm__ __volatile__(\
+ "mrc " rn "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XPSEUDO_ASM_GCC_H */
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xreg_cortexr5.h b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xreg_cortexr5.h
--- /dev/null
@@ -0,0 +1,604 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xreg_cortexr5.h
+*
+* This header file contains definitions for using inline assembler code. It is
+* written specifically for the GNU, IAR, ARMCC compiler.
+*
+* All of the ARM Cortex R5 GPRs, SPRs, and Debug Registers are defined along
+* with the positions of the bits within the registers.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 pkp 02/10/14 Initial version
+* </pre>
+*
+******************************************************************************/
+#ifndef XREG_CORTEXR5_H
+#define XREG_CORTEXR5_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* GPRs */
+#define XREG_GPR0 r0
+#define XREG_GPR1 r1
+#define XREG_GPR2 r2
+#define XREG_GPR3 r3
+#define XREG_GPR4 r4
+#define XREG_GPR5 r5
+#define XREG_GPR6 r6
+#define XREG_GPR7 r7
+#define XREG_GPR8 r8
+#define XREG_GPR9 r9
+#define XREG_GPR10 r10
+#define XREG_GPR11 r11
+#define XREG_GPR12 r12
+#define XREG_GPR13 r13
+#define XREG_GPR14 r14
+#define XREG_GPR15 r15
+#define XREG_CPSR cpsr
+
+/* Coprocessor number defines */
+#define XREG_CP0 0
+#define XREG_CP1 1
+#define XREG_CP2 2
+#define XREG_CP3 3
+#define XREG_CP4 4
+#define XREG_CP5 5
+#define XREG_CP6 6
+#define XREG_CP7 7
+#define XREG_CP8 8
+#define XREG_CP9 9
+#define XREG_CP10 10
+#define XREG_CP11 11
+#define XREG_CP12 12
+#define XREG_CP13 13
+#define XREG_CP14 14
+#define XREG_CP15 15
+
+/* Coprocessor control register defines */
+#define XREG_CR0 cr0
+#define XREG_CR1 cr1
+#define XREG_CR2 cr2
+#define XREG_CR3 cr3
+#define XREG_CR4 cr4
+#define XREG_CR5 cr5
+#define XREG_CR6 cr6
+#define XREG_CR7 cr7
+#define XREG_CR8 cr8
+#define XREG_CR9 cr9
+#define XREG_CR10 cr10
+#define XREG_CR11 cr11
+#define XREG_CR12 cr12
+#define XREG_CR13 cr13
+#define XREG_CR14 cr14
+#define XREG_CR15 cr15
+
+/* Current Processor Status Register (CPSR) Bits */
+#define XREG_CPSR_THUMB_MODE 0x20
+#define XREG_CPSR_MODE_BITS 0x1F
+#define XREG_CPSR_SYSTEM_MODE 0x1F
+#define XREG_CPSR_UNDEFINED_MODE 0x1B
+#define XREG_CPSR_DATA_ABORT_MODE 0x17
+#define XREG_CPSR_SVC_MODE 0x13
+#define XREG_CPSR_IRQ_MODE 0x12
+#define XREG_CPSR_FIQ_MODE 0x11
+#define XREG_CPSR_USER_MODE 0x10
+
+#define XREG_CPSR_IRQ_ENABLE 0x80
+#define XREG_CPSR_FIQ_ENABLE 0x40
+
+#define XREG_CPSR_N_BIT 0x80000000
+#define XREG_CPSR_Z_BIT 0x40000000
+#define XREG_CPSR_C_BIT 0x20000000
+#define XREG_CPSR_V_BIT 0x10000000
+
+/*MPU region definitions*/
+#define REGION_32B 0x4
+#define REGION_64B 0x5
+#define REGION_128B 0x6
+#define REGION_256B 0x7
+#define REGION_512B 0x8
+#define REGION_1K 0x9
+#define REGION_2K 0xA
+#define REGION_4K 0xB
+#define REGION_8K 0xC
+#define REGION_16K 0xD
+#define REGION_32K 0xE
+#define REGION_64K 0xF
+#define REGION_128K 0x10
+#define REGION_256K 0x11
+#define REGION_512K 0x12
+#define REGION_1M 0x13
+#define REGION_2M 0x14
+#define REGION_4M 0x15
+#define REGION_8M 0x16
+#define REGION_16M 0x17
+#define REGION_32M 0x18
+#define REGION_64M 0x19
+#define REGION_128M 0x1A
+#define REGION_256M 0x1B
+#define REGION_512M 0x1C
+#define REGION_1G 0x1D
+#define REGION_2G 0x1E
+#define REGION_4G 0x1F
+
+#define REGION_EN 0x1
+
+
+
+#define SHAREABLE 0x04 /*shareable */
+#define STRONG_ORDERD_SHARED 0x00 /*strongly ordered, always shareable*/
+
+#define DEVICE_SHARED 0x01 /*device, shareable*/
+#define DEVICE_NONSHARED 0x10 /*device, non shareable*/
+
+#define NORM_NSHARED_WT_NWA 0x02 /*Outer and Inner write-through, no write-allocate non-shareable*/
+#define NORM_SHARED_WT_NWA 0x06 /*Outer and Inner write-through, no write-allocate shareable*/
+
+#define NORM_NSHARED_WB_NWA 0x03 /*Outer and Inner write-back, no write-allocate non shareable*/
+#define NORM_SHARED_WB_NWA 0x07 /*Outer and Inner write-back, no write-allocate shareable*/
+
+#define NORM_NSHARED_NCACHE 0x08 /*Outer and Inner Non cacheable non shareable*/
+#define NORM_SHARED_NCACHE 0x0C /*Outer and Inner Non cacheable shareable*/
+
+#define NORM_NSHARED_WB_WA 0xB /*Outer and Inner write-back non shared*/
+#define NORM_SHARED_WB_WA 0xF /*Outer and Inner write-back shared*/
+
+/* inner and outer cache policies can be combined for different combinations */
+
+#define NORM_IN_POLICY_NCACHE 0x20 /*inner non cacheable*/
+#define NORM_IN_POLICY_WB_WA 0x21 /*inner write back write allocate*/
+#define NORM_IN_POLICY_WT_NWA 0x22 /*inner write through no write allocate*/
+#define NORM_IN_POLICY_WB_NWA 0x23 /*inner write back no write allocate*/
+
+#define NORM_OUT_POLICY_NCACHE 0x20 /*outer non cacheable*/
+#define NORM_OUT_POLICY_WB_WA 0x28 /*outer write back write allocate*/
+#define NORM_OUT_POLICY_WT_NWA 0x30 /*outer write through no write allocate*/
+#define NORM_OUT_POLICY_WB_NWA 0x38 /*outer write back no write allocate*/
+
+#define NO_ACCESS 0x00<<8 /*No access*/
+#define PRIV_RW_USER_NA 0x01<<8 /*Privileged access only*/
+#define PRIV_RW_USER_RO 0x02<<8 /*Writes in User mode generate permission faults*/
+#define PRIV_RW_USER_RW 0x03<<8 /*Full Access*/
+#define PRIV_RO_USER_NA 0x05<<8 /*Privileged eead only*/
+#define PRIV_RO_USER_RO 0x06<<8 /*Privileged/User read-only*/
+
+#define EXECUTE_NEVER 0x01<<12 /* Bit 12*/
+
+
+/* CP15 defines */
+#if defined (__GNUC__) || defined (__ICCARM__)
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0"
+#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1"
+#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2"
+#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3"
+#define XREG_CP15_MPU_TYPE "p15, 0, %0, c0, c0, 4"
+#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5"
+
+#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0"
+#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1"
+#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2"
+#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4"
+#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5"
+#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6"
+#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7"
+
+#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0"
+#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1"
+#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2"
+#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3"
+#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4"
+#define XREG_CP15_INST_FEATURE_5 "p15, 0, %0, c0, c2, 5"
+
+#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0"
+#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1"
+#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7"
+
+#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0"
+#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1"
+#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2"
+
+
+
+#else /* RVCT */
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID "cp15:0:c0:c0:0"
+#define XREG_CP15_CACHE_TYPE "cp15:0:c0:c0:1"
+#define XREG_CP15_TCM_TYPE "cp15:0:c0:c0:2"
+#define XREG_CP15_TLB_TYPE "cp15:0:c0:c0:3"
+#define XREG_CP15_MPU_TYPE "cp15:0:c0:c0:4"
+#define XREG_CP15_MULTI_PROC_AFFINITY "cp15:0:c0:c0:5"
+
+#define XREG_CP15_PROC_FEATURE_0 "cp15:0:c0:c1:0"
+#define XREG_CP15_PROC_FEATURE_1 "cp15:0:c0:c1:1"
+#define XREG_CP15_DEBUG_FEATURE_0 "cp15:0:c0:c1:2"
+#define XREG_CP15_MEMORY_FEATURE_0 "cp15:0:c0:c1:4"
+#define XREG_CP15_MEMORY_FEATURE_1 "cp15:0:c0:c1:5"
+#define XREG_CP15_MEMORY_FEATURE_2 "cp15:0:c0:c1:6"
+#define XREG_CP15_MEMORY_FEATURE_3 "cp15:0:c0:c1:7"
+
+#define XREG_CP15_INST_FEATURE_0 "cp15:0:c0:c2:0"
+#define XREG_CP15_INST_FEATURE_1 "cp15:0:c0:c2:1"
+#define XREG_CP15_INST_FEATURE_2 "cp15:0:c0:c2:2"
+#define XREG_CP15_INST_FEATURE_3 "cp15:0:c0:c2:3"
+#define XREG_CP15_INST_FEATURE_4 "cp15:0:c0:c2:4"
+#define XREG_CP15_INST_FEATURE_5 "cp15:0:c0:c2:5"
+
+#define XREG_CP15_CACHE_SIZE_ID "cp15:1:c0:c0:0"
+#define XREG_CP15_CACHE_LEVEL_ID "cp15:1:c0:c0:1"
+#define XREG_CP15_AUXILARY_ID "cp15:1:c0:c0:7"
+
+#define XREG_CP15_CACHE_SIZE_SEL "cp15:2:c0:c0:0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL "cp15:0:c1:c0:0"
+#define XREG_CP15_AUX_CONTROL "cp15:0:c1:c0:1"
+#define XREG_CP15_CP_ACCESS_CONTROL "cp15:0:c1:c0:2"
+
+#endif
+
+/* XREG_CP15_CONTROL bit defines */
+#define XREG_CP15_CONTROL_TE_BIT 0x40000000
+#define XREG_CP15_CONTROL_AFE_BIT 0x20000000
+#define XREG_CP15_CONTROL_TRE_BIT 0x10000000
+#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000
+#define XREG_CP15_CONTROL_EE_BIT 0x02000000
+#define XREG_CP15_CONTROL_HA_BIT 0x00020000
+#define XREG_CP15_CONTROL_RR_BIT 0x00004000
+#define XREG_CP15_CONTROL_V_BIT 0x00002000
+#define XREG_CP15_CONTROL_I_BIT 0x00001000
+#define XREG_CP15_CONTROL_Z_BIT 0x00000800
+#define XREG_CP15_CONTROL_SW_BIT 0x00000400
+#define XREG_CP15_CONTROL_B_BIT 0x00000080
+#define XREG_CP15_CONTROL_C_BIT 0x00000004
+#define XREG_CP15_CONTROL_A_BIT 0x00000002
+#define XREG_CP15_CONTROL_M_BIT 0x00000001
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+/* C2 Register Defines */
+/* Not Used */
+
+/* C3 Register Defines */
+/* Not Used */
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0"
+#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0"
+#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2"
+
+#define XREG_CP15_MPU_REG_BASEADDR "p15, 0, %0, c6, c1, 0"
+#define XREG_CP15_MPU_REG_SIZE_EN "p15, 0, %0, c6, c1, 2"
+#define XREG_CP15_MPU_REG_ACCESS_CTRL "p15, 0, %0, c6, c1, 4"
+
+#define XREG_CP15_MPU_MEMORY_REG_NUMBER "p15, 0, %0, c6, c2, 0"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4"
+
+#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex R5.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_LINE "p15, 0, %0, c7, c5, 7"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1"
+#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2"
+
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1"
+#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2"
+
+#define XREG_CP15_INVAL_DC_ALL "p15, 0, %0, c15, c5, 0"
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex R5.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4"
+#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1"
+
+#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2"
+
+/* C8 Register Defines */
+/* Not Used */
+
+
+/* C9 Register Defines */
+
+#define XREG_CP15_ATCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 1"
+#define XREG_CP15_BTCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 0"
+#define XREG_CP15_TCM_SELECTION "p15, 0, %0, c9, c2, 0"
+
+#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0"
+#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1"
+#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2"
+#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3"
+#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4"
+#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0"
+#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1"
+#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2"
+
+#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0"
+#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1"
+#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2"
+
+/* C10 Register Defines */
+/* Not used */
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+/* Not used */
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1"
+#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2"
+#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3"
+#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_SEC_AUX_CTRL "p15, 0, %0, c15, c0, 0"
+
+
+#else
+/* C2 Register Defines */
+/* Not Used */
+
+/* C3 Register Defines */
+/* Not Used */
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS "cp15:0:c5:c0:0"
+#define XREG_CP15_INST_FAULT_STATUS "cp15:0:c5:c0:1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS "cp15:0:c5:c1:0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS "cp15:0:c5:c1:1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS "cp15:0:c6:c0:0"
+#define XREG_CP15_INST_FAULT_ADDRESS "cp15:0:c6:c0:2"
+
+#define XREG_CP15_MPU_REG_BASEADDR "cp15:0:c6:c1:0"
+#define XREG_CP15_MPU_REG_SIZE_EN "cp15:0:c6:c1:2"
+#define XREG_CP15_MPU_REG_ACCESS_CTRL "cp15:0:c6:c1:4"
+
+#define XREG_CP15_MPU_MEMORY_REG_NUMBER "cp15:0:c6:c2:0"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP "cp15:0:c7:c0:4"
+
+#define XREG_CP15_INVAL_IC_POU "cp15:0:c7:c5:0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU "cp15:0:c7:c5:1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex R5.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER "cp15:0:c7:c5:4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY "cp15:0:c7:c5:6"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_LINE "cp15:0:c7:c5:7"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c6:1"
+#define XREG_CP15_INVAL_DC_LINE_SW "cp15:0:c7:c6:2"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "cp15:0:c7:c10:1"
+#define XREG_CP15_CLEAN_DC_LINE_SW "cp15:0:c7:c10:2"
+
+#define XREG_CP15_INVAL_DC_ALL "cp15:0:c15:c5:0"
+
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex R5.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER "cp15:0:c7:c10:4"
+#define XREG_CP15_DATA_MEMORY_BARRIER "cp15:0:c7:c10:5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "cp15:0:c7:c11:1"
+
+#define XREG_CP15_NOP2 "cp15:0:c7:c13:1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c14:1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "cp15:0:c7:c14:2"
+
+/* C8 Register Defines */
+/* Not Used */
+
+
+/* C9 Register Defines */
+#define XREG_CP15_ATCM_REG_SIZE_ADDR "cp15:0:c9:c1:1"
+#define XREG_CP15_BTCM_REG_SIZE_ADDR "cp15:0:c9:c1:0"
+#define XREG_CP15_TCM_SELECTION "cp15:0:c9:c2:0"
+
+
+#define XREG_CP15_PERF_MONITOR_CTRL "cp15:0:c9:c12:0"
+#define XREG_CP15_COUNT_ENABLE_SET "cp15:0:c9:c12:1"
+#define XREG_CP15_COUNT_ENABLE_CLR "cp15:0:c9:c12:2"
+#define XREG_CP15_V_FLAG_STATUS "cp15:0:c9:c12:3"
+#define XREG_CP15_SW_INC "cp15:0:c9:c12:4"
+#define XREG_CP15_EVENT_CNTR_SEL "cp15:0:c9:c12:5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER "cp15:0:c9:c13:0"
+#define XREG_CP15_EVENT_TYPE_SEL "cp15:0:c9:c13:1"
+#define XREG_CP15_PERF_MONITOR_COUNT "cp15:0:c9:c13:2"
+
+#define XREG_CP15_USER_ENABLE "cp15:0:c9:c14:0"
+#define XREG_CP15_INTR_ENABLE_SET "cp15:0:c9:c14:1"
+#define XREG_CP15_INTR_ENABLE_CLR "cp15:0:c9:c14:2"
+
+/* C10 Register Defines */
+/* Not Used */
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+/* Not Used */
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID "cp15:0:c13:c0:1"
+#define USER_RW_THREAD_PID "cp15:0:c13:c0:2"
+#define USER_RO_THREAD_PID "cp15:0:c13:c0:3"
+#define USER_PRIV_THREAD_PID "cp15:0:c13:c0:4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_SEC_AUX_CTRL "cp15:0:c15:c0:0"
+
+#endif
+
+
+/* MPE register definitions */
+#define XREG_FPSID c0
+#define XREG_FPSCR c1
+#define XREG_MVFR1 c6
+#define XREG_MVFR0 c7
+#define XREG_FPEXC c8
+#define XREG_FPINST c9
+#define XREG_FPINST2 c10
+
+/* FPSID bits */
+#define XREG_FPSID_IMPLEMENTER_BIT (24)
+#define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT)
+#define XREG_FPSID_SOFTWARE (1<<23)
+#define XREG_FPSID_ARCH_BIT (16)
+#define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT)
+#define XREG_FPSID_PART_BIT (8)
+#define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT)
+#define XREG_FPSID_VARIANT_BIT (4)
+#define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT)
+#define XREG_FPSID_REV_BIT (0)
+#define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT)
+
+/* FPSCR bits */
+#define XREG_FPSCR_N_BIT (1 << 31)
+#define XREG_FPSCR_Z_BIT (1 << 30)
+#define XREG_FPSCR_C_BIT (1 << 29)
+#define XREG_FPSCR_V_BIT (1 << 28)
+#define XREG_FPSCR_QC (1 << 27)
+#define XREG_FPSCR_AHP (1 << 26)
+#define XREG_FPSCR_DEFAULT_NAN (1 << 25)
+#define XREG_FPSCR_FLUSHTOZERO (1 << 24)
+#define XREG_FPSCR_ROUND_NEAREST (0 << 22)
+#define XREG_FPSCR_ROUND_PLUSINF (1 << 22)
+#define XREG_FPSCR_ROUND_MINUSINF (2 << 22)
+#define XREG_FPSCR_ROUND_TOZERO (3 << 22)
+#define XREG_FPSCR_RMODE_BIT (22)
+#define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT)
+#define XREG_FPSCR_STRIDE_BIT (20)
+#define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT)
+#define XREG_FPSCR_LENGTH_BIT (16)
+#define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)
+#define XREG_FPSCR_IDC (1 << 7)
+#define XREG_FPSCR_IXC (1 << 4)
+#define XREG_FPSCR_UFC (1 << 3)
+#define XREG_FPSCR_OFC (1 << 2)
+#define XREG_FPSCR_DZC (1 << 1)
+#define XREG_FPSCR_IOC (1 << 0)
+
+/* MVFR0 bits */
+#define XREG_MVFR0_RMODE_BIT (28)
+#define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT)
+#define XREG_MVFR0_SHORT_VEC_BIT (24)
+#define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT)
+#define XREG_MVFR0_SQRT_BIT (20)
+#define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT)
+#define XREG_MVFR0_DIVIDE_BIT (16)
+#define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT)
+#define XREG_MVFR0_EXEC_TRAP_BIT (12)
+#define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT)
+#define XREG_MVFR0_DP_BIT (8)
+#define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT)
+#define XREG_MVFR0_SP_BIT (4)
+#define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT)
+#define XREG_MVFR0_A_SIMD_BIT (0)
+#define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT)
+
+/* FPEXC bits */
+#define XREG_FPEXC_EX (1 << 31)
+#define XREG_FPEXC_EN (1 << 30)
+#define XREG_FPEXC_DEX (1 << 29)
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XREG_CORTEXR5_H */
diff --git a/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xstatus.h b/libs/system/zynqMP_r5/baremetal/xil_standalone_lib/xstatus.h
--- /dev/null
@@ -0,0 +1,441 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law:
+* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
+* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and
+* (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage of
+* any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought
+* by a third party) even if such damage or loss was reasonably foreseeable
+* or Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or environmental
+* damage (individually and collectively, "Critical Applications").
+* Customer assumes the sole risk and liability of any use of Xilinx products in
+* Critical Applications, subject only to applicable laws and regulations
+* governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xstatus.h
+*
+* This file contains Xilinx software status codes. Status codes have their
+* own data type called int. These codes are used throughout the Xilinx
+* device drivers.
+*
+******************************************************************************/
+
+#ifndef XSTATUS_H /* prevent circular inclusions */
+#define XSTATUS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/*********************** Common statuses 0 - 500 *****************************/
+
+#define XST_SUCCESS 0L
+#define XST_FAILURE 1L
+#define XST_DEVICE_NOT_FOUND 2L
+#define XST_DEVICE_BLOCK_NOT_FOUND 3L
+#define XST_INVALID_VERSION 4L
+#define XST_DEVICE_IS_STARTED 5L
+#define XST_DEVICE_IS_STOPPED 6L
+#define XST_FIFO_ERROR 7L /* an error occurred during an
+ operation with a FIFO such as
+ an underrun or overrun, this
+ error requires the device to
+ be reset */
+#define XST_RESET_ERROR 8L /* an error occurred which requires
+ the device to be reset */
+#define XST_DMA_ERROR 9L /* a DMA error occurred, this error
+ typically requires the device
+ using the DMA to be reset */
+#define XST_NOT_POLLED 10L /* the device is not configured for
+ polled mode operation */
+#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put
+ the specified data into */
+#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough
+ to hold the expected data */
+#define XST_NO_DATA 13L /* there was no data available */
+#define XST_REGISTER_ERROR 14L /* a register did not contain the
+ expected value */
+#define XST_INVALID_PARAM 15L /* an invalid parameter was passed
+ into the function */
+#define XST_NOT_SGDMA 16L /* the device is not configured for
+ scatter-gather DMA operation */
+#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */
+#define XST_NO_CALLBACK 18L /* a callback has not yet been
+ registered */
+#define XST_NO_FEATURE 19L /* device is not configured with
+ the requested feature */
+#define XST_NOT_INTERRUPT 20L /* device is not configured for
+ interrupt mode operation */
+#define XST_DEVICE_BUSY 21L /* device is busy */
+#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device
+ have maxed out */
+#define XST_IS_STARTED 23L /* used when part of device is
+ already started i.e.
+ sub channel */
+#define XST_IS_STOPPED 24L /* used when part of device is
+ already stopped i.e.
+ sub channel */
+#define XST_DATA_LOST 26L /* driver defined error */
+#define XST_RECV_ERROR 27L /* generic receive error */
+#define XST_SEND_ERROR 28L /* generic transmit error */
+#define XST_NOT_ENABLED 29L /* a requested service is not
+ available because it has not
+ been enabled */
+
+/***************** Utility Component statuses 401 - 500 *********************/
+
+#define XST_MEMTEST_FAILED 401L /* memory test failed */
+
+
+/***************** Common Components statuses 501 - 1000 *********************/
+
+/********************* Packet Fifo statuses 501 - 510 ************************/
+
+#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */
+#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */
+#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value
+ was invalid after reset */
+#define XST_PFIFO_ERROR 504L /* generic packet FIFO error */
+#define XST_PFIFO_DEADLOCK 505L /* packet FIFO is reporting
+ * empty and full simultaneously
+ */
+
+/************************** DMA statuses 511 - 530 ***************************/
+
+#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer
+ failed */
+#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value
+ was invalid after reset */
+#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains
+ no buffer descriptors ready
+ to be processed */
+#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */
+#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */
+#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of
+ the scatter gather list are
+ being used */
+#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer
+ descriptor which is to be
+ copied over in the scatter
+ list is locked */
+#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been
+ put into the scatter gather
+ list to be commited */
+#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold
+ specified was larger than the
+ total # of buffer descriptors
+ in the scatter gather list */
+#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has
+ already been created */
+#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has
+ been created */
+#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was
+ being started was not committed
+ to the list */
+#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start
+ has already been used by the
+ hardware so it can't be reused
+ */
+#define XST_DMA_SG_LIST_ERROR 526L /* general purpose list access
+ error */
+#define XST_DMA_BD_ERROR 527L /* general buffer descriptor
+ error */
+
+/************************** IPIF statuses 531 - 550 ***************************/
+
+#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width
+ was passed into the function */
+#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at
+ reset was not valid */
+#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt
+ status register did not read
+ back correctly */
+#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status
+ register did not reset when
+ acked */
+#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable
+ register was not updated when
+ other registers changed */
+#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt
+ status register did not read
+ back correctly */
+#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register
+ did not reset when acked */
+#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was
+ not updated correctly when other
+ registers changed */
+#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending
+ register did not indicate the
+ expected value */
+#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register
+ did not indicate the expected
+ value */
+#define XST_IPIF_ERROR 541L /* generic ipif error */
+
+/****************** Device specific statuses 1001 - 4095 *********************/
+
+/********************* Ethernet statuses 1001 - 1050 *************************/
+
+#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough
+ * to hold the minimum number of
+ * buffers or descriptors */
+#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */
+#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */
+#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */
+#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Driver is out of buffers */
+#define XST_EMAC_PARSE_ERROR 1006L /* Invalid driver init string */
+#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late
+ * collision on polled send */
+
+/*********************** UART statuses 1051 - 1075 ***************************/
+#define XST_UART
+
+#define XST_UART_INIT_ERROR 1051L
+#define XST_UART_START_ERROR 1052L
+#define XST_UART_CONFIG_ERROR 1053L
+#define XST_UART_TEST_FAIL 1054L
+#define XST_UART_BAUD_ERROR 1055L
+#define XST_UART_BAUD_RANGE 1056L
+
+
+/************************ IIC statuses 1076 - 1100 ***************************/
+
+#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */
+#define XST_IIC_BUS_BUSY 1077 /* bus found busy */
+#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */
+ /* general call address */
+#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */
+ /* value after reset not valid */
+#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */
+ /* value after reset not valid */
+#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */
+ /* value after reset not valid */
+#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */
+ /* value after reset not valid */
+#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */
+ /* didn't return value written */
+#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */
+ /* didn't return value written */
+#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */
+ /* didn't return value written */
+#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */
+ /* didn't return value written */
+#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */
+ /* didn't return written value */
+#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */
+
+/*********************** ATMC statuses 1101 - 1125 ***************************/
+
+#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM
+ controller hit the max value
+ which requires the statistics
+ to be cleared */
+
+/*********************** Flash statuses 1126 - 1150 **************************/
+
+#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming
+ */
+#define XST_FLASH_READY 1127L /* Flash is ready for commands */
+#define XST_FLASH_ERROR 1128L /* Flash had detected an internal
+ error. Use XFlash_DeviceControl
+ to retrieve device specific codes
+ */
+#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state
+ */
+#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state
+ */
+#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by
+ driver */
+#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */
+#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */
+#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation
+ aborted due to a timeout */
+#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its
+ addressible range */
+#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */
+#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from
+ write/erase function with
+ XFL_NON_BLOCKING_WRITE/ERASE
+ option cleared */
+#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */
+
+/*********************** SPI statuses 1151 - 1175 ****************************/
+
+#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */
+#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */
+#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */
+#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */
+#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */
+#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being
+ * selected */
+#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */
+#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only
+ */
+#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */
+#define XST_SPI_SLAVE_MODE 1160 /* device has been addressed as slave */
+#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /* device received data in slave mode */
+
+#define XST_SPI_COMMAND_ERROR 1162 /* unrecognised command - qspi only */
+
+/********************** OPB Arbiter statuses 1176 - 1200 *********************/
+
+#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either
+ * one master assigned to two or more
+ * priorities, or one master not
+ * assigned to any priority
+ */
+#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the
+ * priority levels without first
+ * suspending the use of priority
+ * levels
+ */
+#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but
+ * bus parking was not enabled
+ */
+#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed
+ * priority mode to allow the
+ * priorities to be changed
+ */
+
+/************************ Intc statuses 1201 - 1225 **************************/
+
+#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */
+#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */
+
+/********************** TmrCtr statuses 1226 - 1250 **************************/
+
+#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */
+
+/********************** WdtTb statuses 1251 - 1275 ***************************/
+
+#define XST_WDTTB_TIMER_FAILED 1251L
+
+/********************** PlbArb statuses 1276 - 1300 **************************/
+
+#define XST_PLBARB_FAIL_SELFTEST 1276L
+
+/********************** Plb2Opb statuses 1301 - 1325 *************************/
+
+#define XST_PLB2OPB_FAIL_SELFTEST 1301L
+
+/********************** Opb2Plb statuses 1326 - 1350 *************************/
+
+#define XST_OPB2PLB_FAIL_SELFTEST 1326L
+
+/********************** SysAce statuses 1351 - 1360 **************************/
+
+#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */
+
+/********************** PCI Bridge statuses 1361 - 1375 **********************/
+
+#define XST_PCI_INVALID_ADDRESS 1361L
+
+/********************** FlexRay constants 1400 - 1409 *************************/
+
+#define XST_FR_TX_ERROR 1400
+#define XST_FR_TX_BUSY 1401
+#define XST_FR_BUF_LOCKED 1402
+#define XST_FR_NO_BUF 1403
+
+/****************** USB constants 1410 - 1420 *******************************/
+
+#define XST_USB_ALREADY_CONFIGURED 1410
+#define XST_USB_BUF_ALIGN_ERROR 1411
+#define XST_USB_NO_DESC_AVAILABLE 1412
+#define XST_USB_BUF_TOO_BIG 1413
+#define XST_USB_NO_BUF 1414
+
+/****************** HWICAP constants 1421 - 1429 *****************************/
+
+#define XST_HWICAP_WRITE_DONE 1421
+
+
+/****************** AXI VDMA constants 1430 - 1440 *****************************/
+
+#define XST_VDMA_MISMATCH_ERROR 1430
+
+/*********************** NAND Flash statuses 1441 - 1459 *********************/
+
+#define XST_NAND_BUSY 1441L /* Flash is erasing or
+ * programming
+ */
+#define XST_NAND_READY 1442L /* Flash is ready for commands
+ */
+#define XST_NAND_ERROR 1443L /* Flash had detected an
+ * internal error.
+ */
+#define XST_NAND_PART_NOT_SUPPORTED 1444L /* Flash type not supported by
+ * driver
+ */
+#define XST_NAND_OPT_NOT_SUPPORTED 1445L /* Operation not supported
+ */
+#define XST_NAND_TIMEOUT_ERROR 1446L /* Programming or erase
+ * operation aborted due to a
+ * timeout
+ */
+#define XST_NAND_ADDRESS_ERROR 1447L /* Accessed flash outside its
+ * addressible range
+ */
+#define XST_NAND_ALIGNMENT_ERROR 1448L /* Write alignment error
+ */
+#define XST_NAND_PARAM_PAGE_ERROR 1449L /* Failed to read parameter
+ * page of the device
+ */
+#define XST_NAND_CACHE_ERROR 1450L /* Flash page buffer error
+ */
+
+#define XST_NAND_WRITE_PROTECTED 1451L /* Flash is write protected
+ */
+
+/**************************** Type Definitions *******************************/
+
+typedef int XStatus;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/porting/zynqMP_r5/platform.c b/porting/zynqMP_r5/platform.c
--- /dev/null
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Mentor Graphics Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**************************************************************************
+ * FILE NAME
+ *
+ * platform.c
+ *
+ * DESCRIPTION
+ *
+ * This file is the Implementation of IPC hardware layer interface
+ * for Xilinx Zynq ZC702EVK platform.
+ *
+ **************************************************************************/
+
+#include "platform.h"
+
+/*--------------------------- Globals ---------------------------------- */
+struct hil_platform_ops proc_ops = {
+ .enable_interrupt = _enable_interrupt,
+ .notify = _notify,
+ .boot_cpu = _boot_cpu,
+ .shutdown_cpu = _shutdown_cpu,
+};
+
+int _enable_interrupt(struct proc_vring *vring_hw) {
+
+ /* Register ISR*/
+ env_register_isr(vring_hw->intr_info.vect_id, vring_hw, platform_isr);
+
+ /* Enable the interrupts */
+ env_enable_interrupt(vring_hw->intr_info.vect_id,
+ vring_hw->intr_info.priority,
+ vring_hw->intr_info.trigger_type);
+ return 0;
+}
+
+void _notify(int cpu_id, struct proc_intr *intr_info) {
+
+ unsigned long mask = 0;
+
+ /* FIX ME -- TO be implemented */
+}
+
+int _boot_cpu(int cpu_id, unsigned int load_addr) {
+ return -1;
+}
+
+void _shutdown_cpu(int cpu_id) {
+ return;
+}
+
+void platform_isr(int vect_id, void *data) {
+ hil_isr(((struct proc_vring *) data));
+}
diff --git a/porting/zynqMP_r5/platform.h b/porting/zynqMP_r5/platform.h
--- /dev/null
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Mentor Graphics Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef PLATFORM_H_
+#define PLATFORM_H_
+
+#include <stdio.h>
+#include "../common/hil/hil.h"
+
+/* ------------------------- Macros --------------------------*/
+
+/********************/
+/* Register offsets */
+/********************/
+
+/* -- FIX ME: ipi info is to be defined -- */
+struct ipi_info {
+ uint32_t preserved;
+};
+
+int _enable_interrupt(struct proc_vring *vring_hw);
+void _notify(int cpu_id, struct proc_intr *intr_info);
+int _boot_cpu(int cpu_id, unsigned int load_addr);
+void _shutdown_cpu(int cpu_id);
+void platform_isr(int vect_id, void *data);
+
+#endif /* PLATFORM_H_ */
diff --git a/porting/zynqMP_r5/platform_info.c b/porting/zynqMP_r5/platform_info.c
--- /dev/null
@@ -0,0 +1,237 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of Mentor Graphics Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**************************************************************************
+ * FILE NAME
+ *
+ * platform_info.c
+ *
+ * DESCRIPTION
+ *
+ * This file implements APIs to get platform specific
+ * information for OpenAMP.
+ *
+ **************************************************************************/
+
+#include "platform.h"
+
+/* Reference implementation that show cases platform_get_cpu_info and
+ platform_get_for_firmware API implementation for Bare metal environment */
+
+extern struct hil_platform_ops proc_ops;
+
+/* IPC Device parameters */
+#define SHM_ADDR (void *)0xFFFCD000
+#define SHM_SIZE 0x8000
+#define VRING0_IPI_VECT 6
+#define VRING1_IPI_VECT 3
+#define MASTER_CPU_ID 0
+#define REMOTE_CPU_ID 1
+
+static struct ipi_info vring0_ipi_info = {0};
+static struct ipi_info vring1_ipi_info = {1};
+
+/**
+ * This array provdes defnition of CPU nodes for master and remote
+ * context. It contains two nodes beacuse the same file is intended
+ * to use with both master and remote configurations. On zynq platform
+ * only one node defintion is required for master/remote as there
+ * are only two cores present in the platform.
+ *
+ * Only platform specific info is populated here. Rest of information
+ * is obtained during resource table parsing.The platform specific
+ * information includes;
+ *
+ * -CPU ID
+ * -Shared Memory
+ * -Interrupts
+ * -Channel info.
+ *
+ * Although the channel info is not platform specific information
+ * but it is conveneient to keep it in HIL so that user can easily
+ * provide it without modifying the generic part.
+ *
+ * It is good idea to define hil_proc structure with platform
+ * specific fields populated as this can be easily copied to hil_proc
+ * structure passed as parameter in platform_get_processor_info. The
+ * other option is to populate the required structures individually
+ * and copy them one by one to hil_proc structure in platform_get_processor_info
+ * function. The first option is adopted here.
+ *
+ *
+ * 1) First node in the array is intended for the remote contexts and it
+ * defines Master CPU ID, shared memory, interrupts info, number of channels
+ * and there names. This node defines only one channel
+ * "rpmsg-openamp-demo-channel".
+ *
+ * 2)Second node is required by the master and it defines remote CPU ID,
+ * shared memory and interrupts info. In general no channel info is required by the
+ * Master node, however in baremetal master and linux remote case the linux
+ * rpmsg bus driver behaves as master so the rpmsg driver on linux side still needs
+ * channel info. This information is not required by the masters for baremetal
+ * remotes.
+ *
+ */
+
+struct hil_proc proc_table []=
+{
+
+ /* CPU node for remote context */
+ {
+ /* CPU ID of master */
+ MASTER_CPU_ID,
+
+ /* Shared memory info - Last field is not used currently */
+ {
+ SHM_ADDR, SHM_SIZE, 0x00
+ },
+
+ /* VirtIO device info */
+ {
+ /* Leave these three fields empty as these are obtained from rsc
+ * table.
+ */
+ 0, 0, 0,
+
+ /* Vring info */
+ {
+
+ {
+ /* Provide only vring interrupts info here. Other fields are
+ * obtained from the resource table so leave them empty.
+ */
+ NULL, NULL, 0, 0,
+ {
+ VRING0_IPI_VECT,0x1006,1,(void *)(&vring0_ipi_info),
+ }
+ },
+ {
+ NULL, NULL, 0, 0,
+ {
+ VRING1_IPI_VECT,0x1006,1,(void *)(&vring1_ipi_info),
+ }
+ }
+ }
+ },
+
+ /* Number of RPMSG channels */
+ 1,
+
+ /* RPMSG channel info - Only channel name is expected currently */
+ {
+ {"rpmsg-openamp-demo-channel"}
+ },
+
+ /* HIL platform ops table. */
+ &proc_ops,
+
+ /* Next three fields are for future use only */
+ 0,
+ 0,
+ NULL
+ },
+
+ /* CPU node for remote context */
+ {
+ /* CPU ID of remote */
+ REMOTE_CPU_ID,
+
+ /* Shared memory info - Last field is not used currently */
+ {
+ SHM_ADDR, SHM_SIZE, 0x00
+ },
+
+ /* VirtIO device info */
+ {
+ 0, 0, 0,
+ {
+ {
+ /* Provide vring interrupts info here. Other fields are obtained
+ * from the rsc table so leave them empty.
+ */
+ NULL, NULL, 0, 0,
+ {
+ VRING0_IPI_VECT,0x1006,1
+ }
+ },
+ {
+ NULL, NULL, 0, 0,
+ {
+ VRING1_IPI_VECT,0x1006,1
+ }
+ }
+ }
+ },
+
+ /* Number of RPMSG channels */
+ 1,
+
+ /* RPMSG channel info - Only channel name is expected currently */
+ {
+ {"rpmsg-openamp-demo-channel"}
+ },
+
+ /* HIL platform ops table. */
+ &proc_ops,
+
+ /* Next three fields are for future use only */
+ 0,
+ 0,
+ NULL
+ }
+};
+
+/**
+ * platform_get_processor_info
+ *
+ * Copies the target info from the user defined data structures to
+ * HIL proc data structure.In case of remote contexts this function
+ * is called with the reserved CPU ID HIL_RSVD_CPU_ID, because for
+ * remotes there is only one master.
+ *
+ * @param proc - HIL proc to populate
+ * @param cpu_id - CPU ID
+ *
+ * return - status of execution
+ */
+int platform_get_processor_info(struct hil_proc *proc , int cpu_id) {
+ int idx;
+ for(idx = 0; idx < sizeof(proc_table)/sizeof(struct hil_proc); idx++) {
+ if((cpu_id == HIL_RSVD_CPU_ID) || (proc_table[idx].cpu_id == cpu_id) ) {
+ env_memcpy(proc,&proc_table[idx], sizeof(struct hil_proc));
+ return 0;
+ }
+ }
+ return -1;
+}
+
+int platform_get_processor_for_fw(char *fw_name) {
+
+ return 1;
+}