From 5a321c0625da019c85d086541349c9539a69e04f Mon Sep 17 00:00:00 2001 From: Wendy Liang Date: Tue, 24 Jan 2017 10:57:48 -0800 Subject: [PATCH] apps: generic: zynqmp_r5: sync linker script with latest xsdk Update the zynqmp_r5 generic linker script to match with the latest xsdk. Signed-off-by: Wendy Liang --- .../machine/zynqmp_r5/linker_remote.ld | 122 ++++++++++-------- 1 file changed, 68 insertions(+), 54 deletions(-) diff --git a/apps/system/generic/machine/zynqmp_r5/linker_remote.ld b/apps/system/generic/machine/zynqmp_r5/linker_remote.ld index 605e0f8..6459b7d 100644 --- a/apps/system/generic/machine/zynqmp_r5/linker_remote.ld +++ b/apps/system/generic/machine/zynqmp_r5/linker_remote.ld @@ -1,14 +1,34 @@ -/*******************************************************************/ -/* */ -/* This file is automatically generated by linker script generator.*/ -/* */ -/* Version: */ -/* */ -/* Copyright (c) 2010 Xilinx, Inc. All rights reserved. */ -/* */ -/* Description : Cortex-R5 Linker Script */ -/* */ -/*******************************************************************/ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ _STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000; _HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x4000; @@ -23,8 +43,10 @@ _UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024; MEMORY { - ps8_r5_tcm_ram_0_S_AXI_BASEADDR : ORIGIN = 0x00000000, LENGTH = 0x00010000 - ps8_r5_tcm_ram_1_S_AXI_BASEADDR : ORIGIN = 0x00020000, LENGTH = 0x00020000 + psu_ddr_S_AXI_BASEADDR : ORIGIN = 0x3ED00000, LENGTH = 0x00020000 + psu_ocm_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x00010000 + psu_r5_tcm_ram_0_S_AXI_BASEADDR : ORIGIN = 0x00000000, LENGTH = 0x00010000 + psu_r5_tcm_ram_1_S_AXI_BASEADDR : ORIGIN = 0x00020000, LENGTH = 0x00020000 } /* Specify the default entry point to the program */ @@ -37,20 +59,12 @@ ENTRY(_vector_table) SECTIONS { - .vectors : { KEEP (*(.vectors)) -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR - - -_binary_firmware1_start = 0; -_binary_firmware1_end = 0; -_binary_firmware2_start = 0; -_binary_firmware2_end = 0; + *(.boot) +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR .text : { - /* *(.vectors) */ - *(.boot) *(.text) *(.text.*) *(.gnu.linkonce.t.*) @@ -62,23 +76,23 @@ _binary_firmware2_end = 0; *(.vfp11_veneer) *(.ARM.extab) *(.gnu.linkonce.armextab.*) -} > ps8_r5_tcm_ram_1_S_AXI_BASEADDR +} > psu_r5_tcm_ram_1_S_AXI_BASEADDR .init : { KEEP (*(.init)) -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR .fini : { KEEP (*(.fini)) -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR .interp : { KEEP (*(.interp)) -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR .note-ABI-tag : { KEEP (*(.note-ABI-tag)) -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR .rodata : { __rodata_start = .; @@ -86,14 +100,14 @@ _binary_firmware2_end = 0; *(.rodata.*) *(.gnu.linkonce.r.*) __rodata_end = .; -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR .rodata1 : { __rodata1_start = .; *(.rodata1) *(.rodata1.*) __rodata1_end = .; -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR .sdata2 : { __sdata2_start = .; @@ -101,7 +115,7 @@ _binary_firmware2_end = 0; *(.sdata2.*) *(.gnu.linkonce.s2.*) __sdata2_end = .; -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR .sbss2 : { __sbss2_start = .; @@ -109,7 +123,7 @@ _binary_firmware2_end = 0; *(.sbss2.*) *(.gnu.linkonce.sb2.*) __sbss2_end = .; -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR .data : { __data_start = .; @@ -120,18 +134,18 @@ _binary_firmware2_end = 0; *(.got) *(.got.plt) __data_end = .; -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR .data1 : { __data1_start = .; *(.data1) *(.data1.*) __data1_end = .; -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR .got : { *(.got) -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR .ctors : { __CTOR_LIST__ = .; @@ -142,7 +156,7 @@ _binary_firmware2_end = 0; KEEP (*(.ctors)) __CTOR_END__ = .; ___CTORS_END___ = .; -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR .dtors : { __DTOR_LIST__ = .; @@ -153,67 +167,67 @@ _binary_firmware2_end = 0; KEEP (*(.dtors)) __DTOR_END__ = .; ___DTORS_END___ = .; -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR .fixup : { __fixup_start = .; *(.fixup) __fixup_end = .; -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR .eh_frame : { *(.eh_frame) -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR .eh_framehdr : { __eh_framehdr_start = .; *(.eh_framehdr) __eh_framehdr_end = .; -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR .gcc_except_table : { *(.gcc_except_table) -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR .mmu_tbl (ALIGN(16384)) : { __mmu_tbl_start = .; *(.mmu_tbl) __mmu_tbl_end = .; -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR .ARM.exidx : { __exidx_start = .; *(.ARM.exidx*) *(.gnu.linkonce.armexidix.*.*) __exidx_end = .; -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR .preinit_array : { __preinit_array_start = .; KEEP (*(SORT(.preinit_array.*))) KEEP (*(.preinit_array)) __preinit_array_end = .; -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR .init_array : { __init_array_start = .; KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array)) __init_array_end = .; -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR .fini_array : { __fini_array_start = .; KEEP (*(SORT(.fini_array.*))) KEEP (*(.fini_array)) __fini_array_end = .; -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR .ARM.attributes : { __ARM.attributes_start = .; *(.ARM.attributes) __ARM.attributes_end = .; -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR .sdata : { __sdata_start = .; @@ -221,7 +235,7 @@ _binary_firmware2_end = 0; *(.sdata.*) *(.gnu.linkonce.s.*) __sdata_end = .; -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR .sbss (NOLOAD) : { __sbss_start = .; @@ -229,7 +243,7 @@ _binary_firmware2_end = 0; *(.sbss.*) *(.gnu.linkonce.sb.*) __sbss_end = .; -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR .tdata : { __tdata_start = .; @@ -237,7 +251,7 @@ _binary_firmware2_end = 0; *(.tdata.*) *(.gnu.linkonce.td.*) __tdata_end = .; -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR .tbss : { __tbss_start = .; @@ -245,7 +259,7 @@ _binary_firmware2_end = 0; *(.tbss.*) *(.gnu.linkonce.tb.*) __tbss_end = .; -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR .bss (NOLOAD) : { . = ALIGN(4); @@ -256,7 +270,7 @@ _binary_firmware2_end = 0; *(COMMON) . = ALIGN(4); __bss_end__ = .; -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR _SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 ); @@ -272,7 +286,7 @@ _SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 ); . += _HEAP_SIZE; _heap_end = .; HeapLimit = .; -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR .stack (NOLOAD) : { . = ALIGN(16); @@ -300,7 +314,7 @@ _SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 ); . += _UNDEF_STACK_SIZE; . = ALIGN(16); __undef_stack = .; -} > ps8_r5_tcm_ram_0_S_AXI_BASEADDR +} > psu_r5_tcm_ram_0_S_AXI_BASEADDR _end = .; } -- 2.39.2