[PDK-14015] Fix Boot App OSPI issue - Inside the Udma_eventIsrFxn function, we invalidate the cache for gTxCompRingMem. And Note that gTxCompRingMem is an 8-byte memory region - The minimum size that cache can be invlidated is 32 bytes. During the cache invalidation for gTxCompRingMem, an additional 16 bytes were inadvertently invalidated, without performing a cache write-back - Regrettably, the memory allocated for fp_readData and fp_seek resides immediately after gTxCompRingMem. Consequently, the data within fp_readData and fp_seek suffered invalidation due to the cache operation - Increased the gTxCompRingMem size to 32 Bytes, so that while invalidating gTxCompRingMem, nothing else gets effected Signed-off-by: Sai Ramakurthi <s-ramakurthi@ti.com>
Fix OSPI U-boot from SBL - Linux tag 09.02.00.005 has some dma related issues which causes hang in u-boot while booting from OSPI - Updated U-boot binaries with 09.02.00.006 linux tag Signed-off-by: Sai Ramakurthi <s-ramakurthi@ti.com>
[PDK-13980] Fix Boot App OSPI - Boot App OSPI uses sbl libraries - Upon enabling DMA in the SBL, the SBL starts linking to the spi_dma library instead of spi library. However, the boot app continues to link to the standard spi library, resulting in a data mismatch when reading from OSPI flash memory. - Modified the code to link the spi_dma library instead of spi library - Updated the fp_readData() function pointer to use Board_flashRead() instead of memcpy because DMA is now enabled Signed-off-by: Sai Ramakurthi <s-ramakurthi@ti.com>
[PDK-13979][J721E] Fix lockstep boot test - For J721E, Hardware does not support combining TCMs of the both the cores while booting in lockstep mode - Hardware support to combine TCMs of both the cores is added from J7200 onwards - SBL_getAtcmSize and SBL_getBtcmSize return TCM memory sizes for split mode. - Made the changes in code to use this API to get the memory for J721e while calling it twice and summing it for other SOCs Signed-off-by: Sai Ramakurthi <s-ramakurthi@ti.com>
Fix Boot App failure on HS devices - When the ‘shareable’ attribute in the MPU configuration is set to false for DDR (Double Data Rate) memory, it effectively makes the DDR memory cacheable. - Since DDR memory is cacheable, it is essential to perform cache write-back operations before proceeding with the authentication step Signed-off-by: Sai Ramakurthi <s-ramakurthi@ti.com>
Enable Secure HSM Boot on HS-FS devices - Since now SBL_loadAndAuthHsmBinary() is part of normal boot flow, hsm.bin shouldn't present in boot media while booting GP device - If hsm.bin is present in boot media while booting on GP device, tifs tries to authenticate hsm.bin which leads to boot hang Signed-off-by: Sai Ramakurthi <s-ramakurthi@ti.com>
Fix Boot Performance Test - Since PHY tuning time is included in boot performance test, Total Boot time increased by "PHY Tuning Time" - Increased the expected CAN response time by average "PHY Tuning Time" i.e 8ms Signed-off-by: Sai Ramakurthi <s-ramakurthi@ti.com>
[SYSFW-6825] Update hsm.bin file - With the existing hsm.bin file, able to boot from hs-se devices and not from hs-fs devices - Received an updated hsm.bin file from the System Firmware (SysFW) team, which now enables booting from both HS-SE and HS-FS devices. Signed-off-by: Sai Ramakurthi <s-ramakurthi@ti.com>
[PDK-13744] Add performance test for SBL OSPI nand - Added PHY tuning time to the SBL performance numbers Signed-off-by: Sai Ramakurthi <s-ramakurthi@ti.com>
[PDK-13745][PDK-13535][SBL] Enable PHY tuning, DMA for OSPI NOR and OSPI NAND - Enabled DMA for OSPI SBL targets - Instead of defining configurations explicitly in SBL, default configurations were used for OSPI - Added comments for profiling points Signed-off-by: Sai Ramakurthi <s-ramakurthi@ti.com>
[PDK-11514] Add test case to ensure cores are switched off if no application image Signed-off-by: Sai Ramakurthi <s-ramakurthi@ti.com>
Update linux binaries with 09.02.00.005 tag after manually updating device tree Signed-off-by: Sai Ramakurthi <s-ramakurthi@ti.com>
Update Linux Binaries with 09.02.00.005 Signed-off-by: Sai Ramakurthi <s-ramakurthi@ti.com>
Fixes "Boot performance test reports high numbers" - Sciclient_pmSetModuleClkParent API is returning failure if sciclient is initializes with DEVGRP_00. - Skip the step of change parent clock of the input muxed clock to A72 core in Boot Perf SBL target. Since this is needed only for Linux boot - This commit can be reverted after fixing PDK-13497 Signed-off-by: Sai Ramakurthi <s-ramakurthi@ti.com>
[BOOT] bool and unsigned macros implementation previously we have used TRUE/FALSE macros both as boolean and unsigned int Now BTRUE/BFALSE macros gets used for boolean implementation and UTRUE/UFALSE macros for the unsigned int implementation Signed-off-by: Asha <x1101668@ti.com>
[PDK-13747] Fix BootApp boot issue in lockstep - Since Boot core (mcu1_0) does not provide the TCM sizes of other R5 cores, used CSL macros to find them - When the core boots in lockstep mode, the TCM size is the total of the TCM sizes of each core Signed-off-by: Sai Ramakurthi <s-ramakurthi@ti.com>
[PDK-13563] Fix Linux boot issue from SBL and BootApp with latest device tree - The input muxed clock DEV_MAIN_PLL8_SEL_EXTWAVE_VD_CLK, which feeds the A72 core, is set by default to use the parent clock DEV_MAIN_PLL8_SEL_EXTWAVE_VD_CLK_PARENT_PLLFRACF_SSMOD_16FFT_MAIN_8_FOUTVCOP_CLK - The A72 core frequency cannot be changed at run time when the parent clock is DEV_MAIN_PLL8_SEL_EXTWAVE_VD_CLK_PARENT_PLLFRACF_SSMOD_16FFT_MAIN_8_FOUTVCOP_CLK, which has no dividers. This causes Linux boot to hang - The input muxed clock DEV_MAIN_PLL8_SEL_EXTWAVE_VD_CLK, which is connected to the A72 core, needs the parent clock DEV_MAIN_PLL8_SEL_EXTWAVE_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_8_HSDIVOUT0_CLK to change the A72 core frequency at run time - This change is needed for both SBL target and SBL HLOS target, since linux boots from SBL HLOS target and SBL target (in case of BootApp) Signed-off-by: Sai Ramakurthi <s-ramakurthi@ti.com>