1 /*----------------------------------------------------------------------------*/
2 /* r5f_linker.cmd */
3 /* */
4 /* (c) Texas Instruments 2020, All rights reserved. */
5 /* */
7 /* USER CODE BEGIN (0) */
8 /* USER CODE END */
9 --retain="*(.intvecs)"
10 --retain="*(.intc_text)"
11 --retain="*(.rstvectors)"
12 --retain="*(.irqStack)"
13 --retain="*(.fiqStack)"
14 --retain="*(.abortStack)"
15 --retain="*(.undStack)"
16 --retain="*(.svcStack)"
17 -stack 0x2000 /* SOFTWARE STACK SIZE */
18 -heap 0x2000 /* HEAP AREA SIZE */
21 /* Stack Sizes for various modes */
22 __IRQ_STACK_SIZE = 0x1000;
23 __FIQ_STACK_SIZE = 0x1000;
24 __ABORT_STACK_SIZE = 0x1000;
25 __UND_STACK_SIZE = 0x1000;
26 __SVC_STACK_SIZE = 0x1000;
28 /*----------------------------------------------------------------------------*/
29 /* Linker Settings */
30 --retain="*(.intvecs)"
32 /*----------------------------------------------------------------------------*/
33 /* Memory Map */
34 MEMORY{
35 PAGE 0:
36 /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
37 RESET_VECTORS (X) : origin=0x00000000 length=0x100
38 /* RESET_VECTORS (X) : origin=0x00020000 length=0x100 */
39 TCMA_RAM (RX) : origin=0x00000100 length=0x00007F00
40 TCMB_RAM (RW) : origin=0x00080000 length=0x00008000
41 SBL_RESERVED_L2_RAM (RW) : origin=0x10200000 length=0x00060000
42 CPPI_DESC (RW): origin=0x10260000 length=0x00001000
43 L2_RAM (RW) : origin=0x10261000 length=(0x00090000 - 0x00001000)
44 L3_RAM (RW) : origin=0x88000000 length=0x00300000
45 L3_RAM_Ping (RW) : origin=0x88300000 length=0x0040000
46 L3_RAM_Pong (RW) : origin=0x88340000 length=0x0040000
47 HWA_RAM (RW) : origin=0x82000000 length=0x00020000
49 PAGE 1:
50 L3_RAM (RW) : origin=0x88000000 length=0x00390000
51 }
53 /*----------------------------------------------------------------------------*/
54 /* Section Configuration */
55 SECTIONS{
56 .rstvectors : {} palign(8) > RESET_VECTORS
57 .bootCode : {} palign(8) > TCMA_RAM
58 .startupCode : {} palign(8) > TCMA_RAM
59 .startupData : {} palign(8) > TCMB_RAM, type = NOINIT
61 /* The linker notation "X >> Y | Z" indicates section X is first allocated in Y
62 and allowed to overflow into Z and can be split from Y to Z.
63 The linker notation "X > Y | Z" indicates section X is first allocated in Y
64 and allowed to overflow into Z and cannot be split from Y to Z. Some sections
65 like bss are not allowed to be split so > notation is used for them
66 */
67 .l2ram : {} > L2_RAM
68 .l3ram : {} > L3_RAM
69 .hwaram : {} > HWA_RAM
70 .text : {} >> TCMA_RAM | L2_RAM
72 .const : {} > L2_RAM
73 .switch : {} > L2_RAM
74 .cio: : {} > SBL_RESERVED_L2_RAM | L2_RAM
75 .data: : {} > L2_RAM
77 .cinit : {} > L2_RAM
78 .pinit : {} > L2_RAM
79 .bss : {} > SBL_RESERVED_L2_RAM | L2_RAM
80 .stack : {} > TCMB_RAM | SBL_RESERVED_L2_RAM | L2_RAM
81 .sysmem : {} > SBL_RESERVED_L2_RAM | L2_RAM
82 uartbuffer : {} palign(8) > L3_RAM
84 .bss:ENET_CPPI_DESC (NOLOAD) {} ALIGN (128) > CPPI_DESC
85 /* For Ethernet packet memory*/
86 .bss:ENET_DMA_DESC_MEMPOOL (NOLOAD) {} ALIGN (128) > L3_RAM
87 .bss:ENET_DMA_RING_MEMPOOL (NOLOAD) {} ALIGN (128) > L3_RAM
88 .bss:ENET_DMA_PKT_MEMPOOL (NOLOAD) {} ALIGN (128) > L3_RAM
89 .bss:ENET_DMA_OBJ_MEM (NOLOAD) {} ALIGN (128) > L3_RAM
91 .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > L2_RAM (HIGH)
92 RUN_START(__IRQ_STACK_START)
93 RUN_END(__IRQ_STACK_END)
94 .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > L2_RAM (HIGH)
95 RUN_START(__FIQ_STACK_START)
96 RUN_END(__FIQ_STACK_END)
97 .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4)> L2_RAM (HIGH)
98 RUN_START(__ABORT_STACK_START)
99 RUN_END(__ABORT_STACK_END)
100 .undStack : {. = . + __UND_STACK_SIZE;} align(4) > L2_RAM (HIGH)
101 RUN_START(__UND_STACK_START)
102 RUN_END(__UND_STACK_END)
103 .svcStack : {. = . + __SVC_STACK_SIZE;} align(4) > L2_RAM (HIGH)
104 RUN_START(__SVC_STACK_START)
105 RUN_END(__SVC_STACK_END)
106 }
107 /*----------------------------------------------------------------------------*/