1 /*
2 * Copyright (c) Texas Instruments Incorporated 2021
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
33 /*!
34 * \file enet_test.h
35 *
36 * \brief This file contains the type definitions and helper macros for ICSSG
37 * TimeSync.
38 */
40 /* ========================================================================== */
41 /* Include Files */
42 /* ========================================================================== */
44 #include <stdint.h>
45 #include <string.h>
46 #include <assert.h>
48 #include <ti/csl/soc.h>
49 #include <ti/drv/uart/UART.h>
50 #include <ti/drv/uart/UART_stdio.h>
51 #include <ti/board/board.h>
52 #include <ti/drv/udma/udma.h>
53 #include <ti/osal/SemaphoreP.h>
54 #include "diag_common_cfg.h"
55 #include "board_cfg.h"
57 #if defined(am65xx_evm)
58 #include <ti/board/src/am65xx_evm/include/board_ethernet_config.h>
59 #else
60 #include <ti/board/src/am65xx_idk/include/board_ethernet_config.h>
61 #endif
63 /* ENET Driver Header Files */
64 #include <ti/drv/enet/enet.h>
65 #include <ti/drv/enet/enet_cfg.h>
66 #include <ti/drv/enet/include/core/enet_dma.h>
67 #include <ti/drv/enet/include/per/icssg.h>
69 /* ENET Util Files */
70 #include <ti/drv/enet/examples/utils/include/enet_apputils.h>
71 #include <ti/drv/enet/examples/utils/include/enet_apputils_baremetal.h>
72 #include <ti/drv/enet/examples/utils/include/enet_appmemutils.h>
73 #include <ti/drv/enet/examples/utils/include/enet_appmemutils_cfg.h>
74 #include <ti/drv/enet/examples/utils/include/enet_appboardutils.h>
75 #include <ti/drv/enet/examples/utils/include/enet_board_am65xevm.h>
77 /* ========================================================================== */
78 /* Macros & Typedefs */
79 /* ========================================================================== */
81 /* Max number of ports supported per context */
82 #define ENETIG_PORT_MAX (2U)
84 /* Max number of ports that can be tested with this app */
85 #define ENETIG_ICSSG_INSTANCE_MAX (2U)
86 #define ENETIG_ICSSG_MAX_PORTS (6U)
88 /* Loopback test Number of packets count */
89 #define BOARD_DIAG_ENETLPBK_TEST_PKT_NUM (100U)
90 /* Loopback Tx/Rx Timeout */
91 #define BOARD_DIAG_ENETLPBK_TIMEOUT (500U)
92 /* Loopback test packet length */
93 #define BOARD_DIAG_ENETLPBK_TEST_PKT_LEN (100U)
94 /* Link Up Timeout */
95 #define BOARD_DIAG_ICSSG_LINKUP_TIMEOUT (100000U)
97 /* ========================================================================== */
98 /* Structure Declarations */
99 /* ========================================================================== */
100 /* Test parameters for each port in the multiport test */
101 typedef struct EnetIg_TestParams_s
102 {
103 /* Peripheral type */
104 Enet_Type enetType;
106 /* Peripheral instance */
107 uint32_t instId;
109 /* Peripheral's MAC ports to use */
110 Enet_MacPort macPort[ENETIG_PORT_MAX];
112 /* Number of MAC ports in macPorts array */
113 uint32_t macPortNum;
115 /* Name of this port to be used for logging */
116 char *name;
118 }EnetIg_TestParams;
120 /* Context of a peripheral/port */
121 typedef struct EnetIg_PerCtxt_s
122 {
123 /* Peripheral type */
124 Enet_Type enetType;
126 /* Peripheral instance */
127 uint32_t instId;
129 /* Peripheral's MAC ports to use */
130 Enet_MacPort macPort[ENETIG_PORT_MAX];
132 /* Number of MAC ports in macPorts array */
133 uint32_t macPortNum;
135 /* Name of this port to be used for logging */
136 char *name;
138 /* Enet driver handle for this peripheral type/instance */
139 Enet_Handle hEnet;
141 /* ICSSG configuration */
142 Icssg_Cfg icssgCfg;
144 /* MAC address. It's port's MAC address in Dual-MAC or
145 * host port's MAC addres in Switch */
146 uint8_t macAddr[ENET_MAC_ADDR_LEN];
148 /* UDMA driver configuration */
149 EnetUdma_Cfg dmaCfg;
151 /* TX channel number */
152 uint32_t txChNum;
154 /* TX channel handle */
155 EnetDma_TxChHandle hTxCh;
157 /* Start flow index */
158 uint32_t rxStartFlowIdx;
160 /* Flow index */
161 uint32_t rxFlowIdx;
163 /* RX channel handle */
164 EnetDma_RxChHandle hRxCh;
166 /* Semaphore posted from RX callback when packets have arrived */
167 SemaphoreP_Handle hRxSem;
169 /* Semaphore posted from TX callback when packets are transmitted */
170 SemaphoreP_Handle hTxSem;
172 /* Flag updated from event callback upon asynchronous IOCTL completion */
173 bool hAsyncIoctlSem;
175 /* Timestamp of the last received packets */
176 uint64_t rxTs[ENET_MEM_NUM_RX_PKTS];
178 /* Timestamp of the last transmitted packets */
179 uint64_t txTs[ENET_MEM_NUM_RX_PKTS];
181 /* Sequence number used as cookie for timestamp events. This value is passed
182 * to the DMA packet when submitting a packet for transmission. Driver will
183 * pass this same value when timestamp for that packet is ready. */
184 uint32_t txTsSeqId;
186 /* Flag updated from event callback upon tx timestamp completion */
187 bool hTxTsSem;
189 } EnetIg_PerCtxt;
191 typedef struct EnetIg_Obj_s
192 {
193 /* This core's id */
194 uint32_t coreId;
196 /* Core key returned by Enet RM after attaching this core */
197 uint32_t coreKey;
199 /* Main UDMA driver handle */
200 Udma_DrvHandle hMainUdmaDrv;
202 /* MCU UDMA driver handle */
203 Udma_DrvHandle hMcuUdmaDrv;
205 /* Queue of free TX packets */
206 EnetDma_PktQ txFreePktInfoQ;
208 /* Array of all peripheral/port contexts used in the test */
209 EnetIg_PerCtxt perCtxt[ENETIG_ICSSG_INSTANCE_MAX];
211 EthFrame *txFrame;
212 EthFrame *rxFrame;
214 /* Number of active contexts being used */
215 uint32_t numPerCtxts;
217 uint32_t totalTxCnt;
219 uint32_t totalRxCnt;
221 uint32_t loopCnt;
223 uint32_t passIterations;
225 uint32_t failIterations;
227 } EnetIg_Obj;