1 /**\r
2 * Note: This file was auto-generated by TI PinMux on 11/19/2020 at 8:18:21 PM.\r
3 *\r
4 * \file AM64x_pinmux_data.c\r
5 *\r
6 * \brief This file contains the pin mux configurations for the boards.\r
7 * These are prepared based on how the peripherals are extended on\r
8 * the boards.\r
9 *\r
10 * \copyright Copyright (CU) 2020 Texas Instruments Incorporated -\r
11 * http://www.ti.com/\r
12 */\r
13 \r
14 /* ========================================================================== */\r
15 /* Include Files */\r
16 /* ========================================================================== */\r
17 \r
18 #include "AM64x_pinmux.h"\r
19 \r
20 /** Peripheral Pin Configurations */\r
21 \r
22 static pinmuxPerCfg_t gAdc0PinCfg[] =\r
23 {\r
24 /* MyADC1 -> ADC0_AIN0 -> G20 */\r
25 {\r
26 PIN_ADC0_AIN0, PIN_MODE(0) | \\r
27 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
28 },\r
29 /* MyADC1 -> ADC0_AIN1 -> F20 */\r
30 {\r
31 PIN_ADC0_AIN1, PIN_MODE(0) | \\r
32 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
33 },\r
34 /* MyADC1 -> ADC0_AIN2 -> E21 */\r
35 {\r
36 PIN_ADC0_AIN2, PIN_MODE(0) | \\r
37 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
38 },\r
39 /* MyADC1 -> ADC0_AIN3 -> D20 */\r
40 {\r
41 PIN_ADC0_AIN3, PIN_MODE(0) | \\r
42 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
43 },\r
44 /* MyADC1 -> ADC0_AIN4 -> G21 */\r
45 {\r
46 PIN_ADC0_AIN4, PIN_MODE(0) | \\r
47 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
48 },\r
49 /* MyADC1 -> ADC0_AIN5 -> F21 */\r
50 {\r
51 PIN_ADC0_AIN5, PIN_MODE(0) | \\r
52 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
53 },\r
54 /* MyADC1 -> ADC0_AIN6 -> F19 */\r
55 {\r
56 PIN_ADC0_AIN6, PIN_MODE(0) | \\r
57 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
58 },\r
59 /* MyADC1 -> ADC0_AIN7 -> E20 */\r
60 {\r
61 PIN_ADC0_AIN7, PIN_MODE(0) | \\r
62 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
63 },\r
64 {PINMUX_END}\r
65 };\r
66 \r
67 static pinmuxModuleCfg_t gAdcPinCfg[] =\r
68 {\r
69 {0, TRUE, gAdc0PinCfg},\r
70 {PINMUX_END}\r
71 };\r
72 \r
73 \r
74 static pinmuxPerCfg_t gFsi_rx0PinCfg[] =\r
75 {\r
76 /* MyFSI_RX1 -> FSI_RX0_CLK -> V19 */\r
77 {\r
78 PIN_GPMC0_AD8, PIN_MODE(1) | \\r
79 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
80 },\r
81 /* MyFSI_RX1 -> FSI_RX0_D0 -> T17 */\r
82 {\r
83 PIN_GPMC0_AD9, PIN_MODE(1) | \\r
84 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
85 },\r
86 /* MyFSI_RX1 -> FSI_RX0_D1 -> R16 */\r
87 {\r
88 PIN_GPMC0_AD10, PIN_MODE(1) | \\r
89 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
90 },\r
91 {PINMUX_END}\r
92 };\r
93 \r
94 static pinmuxModuleCfg_t gFsi_rxPinCfg[] =\r
95 {\r
96 {0, TRUE, gFsi_rx0PinCfg},\r
97 {PINMUX_END}\r
98 };\r
99 \r
100 \r
101 static pinmuxPerCfg_t gFsi_tx0PinCfg[] =\r
102 {\r
103 /* MyFSI_TX1 -> FSI_TX0_CLK -> T19 */\r
104 {\r
105 PIN_GPMC0_BE1N, PIN_MODE(1) | \\r
106 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
107 },\r
108 /* MyFSI_TX1 -> FSI_TX0_D0 -> Y21 */\r
109 {\r
110 PIN_GPMC0_AD14, PIN_MODE(1) | \\r
111 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
112 },\r
113 /* MyFSI_TX1 -> FSI_TX0_D1 -> Y20 */\r
114 {\r
115 PIN_GPMC0_AD15, PIN_MODE(1) | \\r
116 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
117 },\r
118 {PINMUX_END}\r
119 };\r
120 \r
121 static pinmuxModuleCfg_t gFsi_txPinCfg[] =\r
122 {\r
123 {0, TRUE, gFsi_tx0PinCfg},\r
124 {PINMUX_END}\r
125 };\r
126 \r
127 \r
128 static pinmuxPerCfg_t gGpio0PinCfg[] =\r
129 {\r
130 /* MyGPIO1 -> GPIO0_12 -> L18 */\r
131 {\r
132 PIN_OSPI0_CSN1, PIN_MODE(7) | \\r
133 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
134 },\r
135 /* MyGPIO1 -> GPIO0_13 -> K17 */\r
136 {\r
137 PIN_OSPI0_CSN2, PIN_MODE(7) | \\r
138 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
139 },\r
140 /* MyGPIO1 -> GPIO0_14 -> L17 */\r
141 {\r
142 PIN_OSPI0_CSN3, PIN_MODE(7) | \\r
143 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
144 },\r
145 {PINMUX_END}\r
146 };\r
147 \r
148 static pinmuxPerCfg_t gGpio1PinCfg[] =\r
149 {\r
150 /* MyGPIO2 -> GPIO1_43 -> C13 */\r
151 {\r
152 PIN_SPI0_CS1, PIN_MODE(7) | \\r
153 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
154 },\r
155 /* MyGPIO2 -> GPIO1_70 -> C19 */\r
156 {\r
157 PIN_EXTINTN, PIN_MODE(7) | \\r
158 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
159 },\r
160 /* MyGPIO2 -> GPIO1_78 -> C20 */\r
161 {\r
162 PIN_MMC1_SDWP, PIN_MODE(7) | \\r
163 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
164 },\r
165 {PINMUX_END}\r
166 };\r
167 \r
168 static pinmuxModuleCfg_t gGpioPinCfg[] =\r
169 {\r
170 {0, TRUE, gGpio0PinCfg},\r
171 {1, TRUE, gGpio1PinCfg},\r
172 {PINMUX_END}\r
173 };\r
174 \r
175 \r
176 static pinmuxPerCfg_t gI2c0PinCfg[] =\r
177 {\r
178 /* MyI2C1 -> I2C0_SCL -> A18 */\r
179 {\r
180 PIN_I2C0_SCL, PIN_MODE(0) | \\r
181 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
182 },\r
183 /* MyI2C1 -> I2C0_SDA -> B18 */\r
184 {\r
185 PIN_I2C0_SDA, PIN_MODE(0) | \\r
186 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
187 },\r
188 {PINMUX_END}\r
189 };\r
190 \r
191 static pinmuxPerCfg_t gI2c1PinCfg[] =\r
192 {\r
193 /* MyI2C2 -> I2C1_SCL -> C18 */\r
194 {\r
195 PIN_I2C1_SCL, PIN_MODE(0) | \\r
196 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
197 },\r
198 /* MyI2C2 -> I2C1_SDA -> B19 */\r
199 {\r
200 PIN_I2C1_SDA, PIN_MODE(0) | \\r
201 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
202 },\r
203 {PINMUX_END}\r
204 };\r
205 \r
206 static pinmuxModuleCfg_t gI2cPinCfg[] =\r
207 {\r
208 {0, TRUE, gI2c0PinCfg},\r
209 {1, TRUE, gI2c1PinCfg},\r
210 {PINMUX_END}\r
211 };\r
212 \r
213 \r
214 static pinmuxPerCfg_t gMcan0PinCfg[] =\r
215 {\r
216 /* MyMCAN1 -> MCAN0_RX -> B17 */\r
217 {\r
218 PIN_MCAN0_RX, PIN_MODE(0) | \\r
219 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
220 },\r
221 /* MyMCAN1 -> MCAN0_TX -> A17 */\r
222 {\r
223 PIN_MCAN0_TX, PIN_MODE(0) | \\r
224 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
225 },\r
226 {PINMUX_END}\r
227 };\r
228 \r
229 static pinmuxPerCfg_t gMcan1PinCfg[] =\r
230 {\r
231 /* MyMCAN2 -> MCAN1_RX -> D17 */\r
232 {\r
233 PIN_MCAN1_RX, PIN_MODE(0) | \\r
234 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
235 },\r
236 /* MyMCAN2 -> MCAN1_TX -> C17 */\r
237 {\r
238 PIN_MCAN1_TX, PIN_MODE(0) | \\r
239 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
240 },\r
241 {PINMUX_END}\r
242 };\r
243 \r
244 static pinmuxModuleCfg_t gMcanPinCfg[] =\r
245 {\r
246 {0, TRUE, gMcan0PinCfg},\r
247 {1, TRUE, gMcan1PinCfg},\r
248 {PINMUX_END}\r
249 };\r
250 \r
251 \r
252 static pinmuxPerCfg_t gMcu_gpio0PinCfg[] =\r
253 {\r
254 /* MyMCU_GPIO1 -> MCU_GPIO0_5 -> A7 */\r
255 {\r
256 PIN_MCU_SPI1_CS0, PIN_MODE(7) | \\r
257 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
258 },\r
259 {PINMUX_END}\r
260 };\r
261 \r
262 static pinmuxModuleCfg_t gMcu_gpioPinCfg[] =\r
263 {\r
264 {0, TRUE, gMcu_gpio0PinCfg},\r
265 {PINMUX_END}\r
266 };\r
267 \r
268 \r
269 static pinmuxPerCfg_t gMcu_i2c0PinCfg[] =\r
270 {\r
271 /* MyMCU_I2C1 -> MCU_I2C0_SCL -> E9 */\r
272 {\r
273 PIN_MCU_I2C0_SCL, PIN_MODE(0) | \\r
274 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
275 },\r
276 /* MyMCU_I2C1 -> MCU_I2C0_SDA -> A10 */\r
277 {\r
278 PIN_MCU_I2C0_SDA, PIN_MODE(0) | \\r
279 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
280 },\r
281 {PINMUX_END}\r
282 };\r
283 \r
284 static pinmuxPerCfg_t gMcu_i2c1PinCfg[] =\r
285 {\r
286 /* MyMCU_I2C2 -> MCU_I2C1_SCL -> A11 */\r
287 {\r
288 PIN_MCU_I2C1_SCL, PIN_MODE(0) | \\r
289 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
290 },\r
291 /* MyMCU_I2C2 -> MCU_I2C1_SDA -> B10 */\r
292 {\r
293 PIN_MCU_I2C1_SDA, PIN_MODE(0) | \\r
294 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
295 },\r
296 {PINMUX_END}\r
297 };\r
298 \r
299 static pinmuxModuleCfg_t gMcu_i2cPinCfg[] =\r
300 {\r
301 {0, TRUE, gMcu_i2c0PinCfg},\r
302 {1, TRUE, gMcu_i2c1PinCfg},\r
303 {PINMUX_END}\r
304 };\r
305 \r
306 \r
307 static pinmuxPerCfg_t gMcu_system0PinCfg[] =\r
308 {\r
309 /* MyMCU_SYSTEM1 -> MCU_PORz -> B21 */\r
310 {\r
311 PIN_MCU_PORZ, PIN_MODE(0) | \\r
312 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
313 },\r
314 /* MyMCU_SYSTEM1 -> MCU_RESETSTATz -> B13 */\r
315 {\r
316 PIN_MCU_RESETSTATZ, PIN_MODE(0) | \\r
317 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
318 },\r
319 /* MyMCU_SYSTEM1 -> MCU_RESETz -> B12 */\r
320 {\r
321 PIN_MCU_RESETZ, PIN_MODE(0) | \\r
322 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
323 },\r
324 /* MyMCU_SYSTEM1 -> MCU_SAFETY_ERRORn -> A20 */\r
325 {\r
326 PIN_MCU_SAFETY_ERRORN, PIN_MODE(0) | \\r
327 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
328 },\r
329 {PINMUX_END}\r
330 };\r
331 \r
332 static pinmuxModuleCfg_t gMcu_systemPinCfg[] =\r
333 {\r
334 {0, TRUE, gMcu_system0PinCfg},\r
335 {PINMUX_END}\r
336 };\r
337 \r
338 \r
339 static pinmuxPerCfg_t gMcu_uart0PinCfg[] =\r
340 {\r
341 /* MyMCU_UART1 -> MCU_UART0_CTSn -> D8 */\r
342 {\r
343 PIN_MCU_UART0_CTSN, PIN_MODE(0) | \\r
344 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
345 },\r
346 /* MyMCU_UART1 -> MCU_UART0_RTSn -> E8 */\r
347 {\r
348 PIN_MCU_UART0_RTSN, PIN_MODE(0) | \\r
349 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
350 },\r
351 /* MyMCU_UART1 -> MCU_UART0_RXD -> A9 */\r
352 {\r
353 PIN_MCU_UART0_RXD, PIN_MODE(0) | \\r
354 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
355 },\r
356 /* MyMCU_UART1 -> MCU_UART0_TXD -> A8 */\r
357 {\r
358 PIN_MCU_UART0_TXD, PIN_MODE(0) | \\r
359 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
360 },\r
361 {PINMUX_END}\r
362 };\r
363 \r
364 static pinmuxPerCfg_t gMcu_uart1PinCfg[] =\r
365 {\r
366 /* MyMCU_UART2 -> MCU_UART1_CTSn -> B8 */\r
367 {\r
368 PIN_MCU_UART1_CTSN, PIN_MODE(0) | \\r
369 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
370 },\r
371 /* MyMCU_UART2 -> MCU_UART1_RTSn -> B9 */\r
372 {\r
373 PIN_MCU_UART1_RTSN, PIN_MODE(0) | \\r
374 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
375 },\r
376 /* MyMCU_UART2 -> MCU_UART1_RXD -> C9 */\r
377 {\r
378 PIN_MCU_UART1_RXD, PIN_MODE(0) | \\r
379 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
380 },\r
381 /* MyMCU_UART2 -> MCU_UART1_TXD -> D9 */\r
382 {\r
383 PIN_MCU_UART1_TXD, PIN_MODE(0) | \\r
384 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
385 },\r
386 {PINMUX_END}\r
387 };\r
388 \r
389 static pinmuxModuleCfg_t gMcu_uartPinCfg[] =\r
390 {\r
391 {0, TRUE, gMcu_uart0PinCfg},\r
392 {1, TRUE, gMcu_uart1PinCfg},\r
393 {PINMUX_END}\r
394 };\r
395 \r
396 \r
397 static pinmuxPerCfg_t gMdio0PinCfg[] =\r
398 {\r
399 /* MyMDIO1 -> MDIO0_MDC -> R2 */\r
400 {\r
401 PIN_PRG0_PRU1_GPO19, PIN_MODE(4) | \\r
402 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
403 },\r
404 /* MyMDIO1 -> MDIO0_MDIO -> P5 */\r
405 {\r
406 PIN_PRG0_PRU1_GPO18, PIN_MODE(4) | \\r
407 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
408 },\r
409 {PINMUX_END}\r
410 };\r
411 \r
412 static pinmuxModuleCfg_t gMdioPinCfg[] =\r
413 {\r
414 {0, TRUE, gMdio0PinCfg},\r
415 {PINMUX_END}\r
416 };\r
417 \r
418 \r
419 static pinmuxPerCfg_t gMmc11PinCfg[] =\r
420 {\r
421 /* MyMMC11 -> MMC1_CMD -> J19 */\r
422 {\r
423 PIN_MMC1_CMD, PIN_MODE(0) | \\r
424 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
425 },\r
426 /* MyMMC11 -> MMC1_CLK -> L20 */\r
427 {\r
428 PIN_MMC1_CLK, PIN_MODE(0) | \\r
429 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
430 },\r
431 /* MyMMC11 -> MMC1_CLKLB */\r
432 {\r
433 PIN_MMC1_CLKLB, PIN_MODE(0) | \\r
434 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
435 },\r
436 /* MyMMC11 -> MMC1_DAT0 -> K21 */\r
437 {\r
438 PIN_MMC1_DAT0, PIN_MODE(0) | \\r
439 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
440 },\r
441 /* MyMMC11 -> MMC1_DAT1 -> L21 */\r
442 {\r
443 PIN_MMC1_DAT1, PIN_MODE(0) | \\r
444 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
445 },\r
446 /* MyMMC11 -> MMC1_DAT2 -> K19 */\r
447 {\r
448 PIN_MMC1_DAT2, PIN_MODE(0) | \\r
449 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
450 },\r
451 /* MyMMC11 -> MMC1_DAT3 -> K18 */\r
452 {\r
453 PIN_MMC1_DAT3, PIN_MODE(0) | \\r
454 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
455 },\r
456 /* MyMMC11 -> MMC1_SDCD -> D19 */\r
457 {\r
458 PIN_MMC1_SDCD, PIN_MODE(0) | \\r
459 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))\r
460 },\r
461 {PINMUX_END}\r
462 };\r
463 \r
464 static pinmuxModuleCfg_t gMmc1PinCfg[] =\r
465 {\r
466 {1, TRUE, gMmc11PinCfg},\r
467 {PINMUX_END}\r
468 };\r
469 \r
470 \r
471 static pinmuxPerCfg_t gOspi0PinCfg[] =\r
472 {\r
473 /* MyOSPI1 -> OSPI0_CLK -> N20 */\r
474 {\r
475 PIN_OSPI0_CLK, PIN_MODE(0) | \\r
476 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
477 },\r
478 /* MyOSPI1 -> OSPI0_CSn0 -> L19 */\r
479 {\r
480 PIN_OSPI0_CSN0, PIN_MODE(0) | \\r
481 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
482 },\r
483 /* MyOSPI1 -> OSPI0_D0 -> M19 */\r
484 {\r
485 PIN_OSPI0_D0, PIN_MODE(0) | \\r
486 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
487 },\r
488 /* MyOSPI1 -> OSPI0_D1 -> M18 */\r
489 {\r
490 PIN_OSPI0_D1, PIN_MODE(0) | \\r
491 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
492 },\r
493 /* MyOSPI1 -> OSPI0_D2 -> M20 */\r
494 {\r
495 PIN_OSPI0_D2, PIN_MODE(0) | \\r
496 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
497 },\r
498 /* MyOSPI1 -> OSPI0_D3 -> M21 */\r
499 {\r
500 PIN_OSPI0_D3, PIN_MODE(0) | \\r
501 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
502 },\r
503 /* MyOSPI1 -> OSPI0_D4 -> P21 */\r
504 {\r
505 PIN_OSPI0_D4, PIN_MODE(0) | \\r
506 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
507 },\r
508 /* MyOSPI1 -> OSPI0_D5 -> P20 */\r
509 {\r
510 PIN_OSPI0_D5, PIN_MODE(0) | \\r
511 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
512 },\r
513 /* MyOSPI1 -> OSPI0_D6 -> N18 */\r
514 {\r
515 PIN_OSPI0_D6, PIN_MODE(0) | \\r
516 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
517 },\r
518 /* MyOSPI1 -> OSPI0_D7 -> M17 */\r
519 {\r
520 PIN_OSPI0_D7, PIN_MODE(0) | \\r
521 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
522 },\r
523 /* MyOSPI1 -> OSPI0_DQS -> N19 */\r
524 {\r
525 PIN_OSPI0_DQS, PIN_MODE(0) | \\r
526 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
527 },\r
528 {PINMUX_END}\r
529 };\r
530 \r
531 static pinmuxModuleCfg_t gOspiPinCfg[] =\r
532 {\r
533 {0, TRUE, gOspi0PinCfg},\r
534 {PINMUX_END}\r
535 };\r
536 \r
537 \r
538 static pinmuxPerCfg_t gPru_icssg0_mdio0PinCfg[] =\r
539 {\r
540 /* MyPRU_ICSSG0_MDIO1 -> PRG0_MDIO0_MDC -> P3 */\r
541 {\r
542 PIN_PRG0_MDIO0_MDC, PIN_MODE(0) | \\r
543 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
544 },\r
545 /* MyPRU_ICSSG0_MDIO1 -> PRG0_MDIO0_MDIO -> P2 */\r
546 {\r
547 PIN_PRG0_MDIO0_MDIO, PIN_MODE(0) | \\r
548 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
549 },\r
550 {PINMUX_END}\r
551 };\r
552 \r
553 static pinmuxModuleCfg_t gPru_icssg0_mdioPinCfg[] =\r
554 {\r
555 {0, TRUE, gPru_icssg0_mdio0PinCfg},\r
556 {PINMUX_END}\r
557 };\r
558 \r
559 \r
560 static pinmuxPerCfg_t gPru_icssg0_pru0PinCfg[] =\r
561 {\r
562 /* MyPRU_ICSSG0_PRU1 -> PRG0_PRU0_GPO8 -> T2 */\r
563 {\r
564 PIN_PRG0_PRU0_GPO8, PIN_MODE(0) | \\r
565 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
566 },\r
567 {PINMUX_END}\r
568 };\r
569 \r
570 static pinmuxPerCfg_t gPru_icssg0_pru1PinCfg[] =\r
571 {\r
572 /* MyPRU_ICSSG0_PRU2 -> PRG0_PRU1_GPO8 -> R1 */\r
573 {\r
574 PIN_PRG0_PRU1_GPO8, PIN_MODE(0) | \\r
575 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
576 },\r
577 {PINMUX_END}\r
578 };\r
579 \r
580 static pinmuxModuleCfg_t gPru_icssg0_pruPinCfg[] =\r
581 {\r
582 {0, TRUE, gPru_icssg0_pru0PinCfg},\r
583 {1, TRUE, gPru_icssg0_pru1PinCfg},\r
584 {PINMUX_END}\r
585 };\r
586 \r
587 \r
588 static pinmuxPerCfg_t gPru_icssg1_mdio0PinCfg[] =\r
589 {\r
590 /* MyPRU_ICSSG1_MDIO1 -> PRG1_MDIO0_MDC -> Y6 */\r
591 {\r
592 PIN_PRG1_MDIO0_MDC, PIN_MODE(0) | \\r
593 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
594 },\r
595 /* MyPRU_ICSSG1_MDIO1 -> PRG1_MDIO0_MDIO -> AA6 */\r
596 {\r
597 PIN_PRG1_MDIO0_MDIO, PIN_MODE(0) | \\r
598 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
599 },\r
600 {PINMUX_END}\r
601 };\r
602 \r
603 static pinmuxModuleCfg_t gPru_icssg1_mdioPinCfg[] =\r
604 {\r
605 {0, TRUE, gPru_icssg1_mdio0PinCfg},\r
606 {PINMUX_END}\r
607 };\r
608 \r
609 \r
610 static pinmuxPerCfg_t gPru_icssg1_rgmii1PinCfg[] =\r
611 {\r
612 /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_RD0 -> Y7 */\r
613 {\r
614 PIN_PRG1_PRU0_GPO0, PIN_MODE(2) | \\r
615 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
616 },\r
617 /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_RD1 -> U8 */\r
618 {\r
619 PIN_PRG1_PRU0_GPO1, PIN_MODE(2) | \\r
620 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
621 },\r
622 /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_RD2 -> W8 */\r
623 {\r
624 PIN_PRG1_PRU0_GPO2, PIN_MODE(2) | \\r
625 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
626 },\r
627 /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_RD3 -> V8 */\r
628 {\r
629 PIN_PRG1_PRU0_GPO3, PIN_MODE(2) | \\r
630 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
631 },\r
632 /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_RXC -> AA7 */\r
633 {\r
634 PIN_PRG1_PRU0_GPO6, PIN_MODE(2) | \\r
635 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
636 },\r
637 /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_RX_CTL -> Y8 */\r
638 {\r
639 PIN_PRG1_PRU0_GPO4, PIN_MODE(2) | \\r
640 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
641 },\r
642 /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_TD0 -> AA8 */\r
643 {\r
644 PIN_PRG1_PRU0_GPO11, PIN_MODE(2) | \\r
645 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
646 },\r
647 /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_TD1 -> U9 */\r
648 {\r
649 PIN_PRG1_PRU0_GPO12, PIN_MODE(2) | \\r
650 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
651 },\r
652 /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_TD2 -> W9 */\r
653 {\r
654 PIN_PRG1_PRU0_GPO13, PIN_MODE(2) | \\r
655 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
656 },\r
657 /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_TD3 -> AA9 */\r
658 {\r
659 PIN_PRG1_PRU0_GPO14, PIN_MODE(2) | \\r
660 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
661 },\r
662 /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_TXC -> V9 */\r
663 {\r
664 PIN_PRG1_PRU0_GPO16, PIN_MODE(2) | \\r
665 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
666 },\r
667 /* MyPRU_ICSSG1_RGMII1 -> PRG1_RGMII1_TX_CTL -> Y9 */\r
668 {\r
669 PIN_PRG1_PRU0_GPO15, PIN_MODE(2) | \\r
670 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
671 },\r
672 {PINMUX_END}\r
673 };\r
674 \r
675 static pinmuxPerCfg_t gPru_icssg1_rgmii2PinCfg[] =\r
676 {\r
677 /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_RD0 -> W11 */\r
678 {\r
679 PIN_PRG1_PRU1_GPO0, PIN_MODE(2) | \\r
680 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
681 },\r
682 /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_RD1 -> V11 */\r
683 {\r
684 PIN_PRG1_PRU1_GPO1, PIN_MODE(2) | \\r
685 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
686 },\r
687 /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_RD2 -> AA12 */\r
688 {\r
689 PIN_PRG1_PRU1_GPO2, PIN_MODE(2) | \\r
690 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
691 },\r
692 /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_RD3 -> Y12 */\r
693 {\r
694 PIN_PRG1_PRU1_GPO3, PIN_MODE(2) | \\r
695 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
696 },\r
697 /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_RXC -> U11 */\r
698 {\r
699 PIN_PRG1_PRU1_GPO6, PIN_MODE(2) | \\r
700 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
701 },\r
702 /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_RX_CTL -> W12 */\r
703 {\r
704 PIN_PRG1_PRU1_GPO4, PIN_MODE(2) | \\r
705 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
706 },\r
707 /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_TD0 -> AA10 */\r
708 {\r
709 PIN_PRG1_PRU1_GPO11, PIN_MODE(2) | \\r
710 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
711 },\r
712 /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_TD1 -> V10 */\r
713 {\r
714 PIN_PRG1_PRU1_GPO12, PIN_MODE(2) | \\r
715 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
716 },\r
717 /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_TD2 -> U10 */\r
718 {\r
719 PIN_PRG1_PRU1_GPO13, PIN_MODE(2) | \\r
720 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
721 },\r
722 /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_TD3 -> AA11 */\r
723 {\r
724 PIN_PRG1_PRU1_GPO14, PIN_MODE(2) | \\r
725 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
726 },\r
727 /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_TXC -> Y10 */\r
728 {\r
729 PIN_PRG1_PRU1_GPO16, PIN_MODE(2) | \\r
730 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
731 },\r
732 /* MyPRU_ICSSG1_RGMII2 -> PRG1_RGMII2_TX_CTL -> Y11 */\r
733 {\r
734 PIN_PRG1_PRU1_GPO15, PIN_MODE(2) | \\r
735 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
736 },\r
737 {PINMUX_END}\r
738 };\r
739 \r
740 static pinmuxModuleCfg_t gPru_icssg1_rgmiiPinCfg[] =\r
741 {\r
742 {1, TRUE, gPru_icssg1_rgmii1PinCfg},\r
743 {2, TRUE, gPru_icssg1_rgmii2PinCfg},\r
744 {PINMUX_END}\r
745 };\r
746 \r
747 \r
748 static pinmuxPerCfg_t gRgmii1PinCfg[] =\r
749 {\r
750 /* MyRGMII1 -> RGMII1_RD0 -> W5 */\r
751 {\r
752 PIN_PRG0_PRU1_GPO7, PIN_MODE(4) | \\r
753 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
754 },\r
755 /* MyRGMII1 -> RGMII1_RD1 -> Y5 */\r
756 {\r
757 PIN_PRG0_PRU1_GPO9, PIN_MODE(4) | \\r
758 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
759 },\r
760 /* MyRGMII1 -> RGMII1_RD2 -> V6 */\r
761 {\r
762 PIN_PRG0_PRU1_GPO10, PIN_MODE(4) | \\r
763 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
764 },\r
765 /* MyRGMII1 -> RGMII1_RD3 -> V5 */\r
766 {\r
767 PIN_PRG0_PRU1_GPO17, PIN_MODE(4) | \\r
768 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
769 },\r
770 /* MyRGMII1 -> RGMII1_RXC -> AA5 */\r
771 {\r
772 PIN_PRG0_PRU0_GPO10, PIN_MODE(4) | \\r
773 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
774 },\r
775 /* MyRGMII1 -> RGMII1_RX_CTL -> W6 */\r
776 {\r
777 PIN_PRG0_PRU0_GPO9, PIN_MODE(4) | \\r
778 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
779 },\r
780 /* MyRGMII1 -> RGMII1_TD0 -> V15 */\r
781 {\r
782 PIN_PRG1_PRU1_GPO7, PIN_MODE(4) | \\r
783 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
784 },\r
785 /* MyRGMII1 -> RGMII1_TD1 -> V14 */\r
786 {\r
787 PIN_PRG1_PRU1_GPO9, PIN_MODE(4) | \\r
788 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
789 },\r
790 /* MyRGMII1 -> RGMII1_TD2 -> W14 */\r
791 {\r
792 PIN_PRG1_PRU1_GPO10, PIN_MODE(4) | \\r
793 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
794 },\r
795 /* MyRGMII1 -> RGMII1_TD3 -> AA14 */\r
796 {\r
797 PIN_PRG1_PRU1_GPO17, PIN_MODE(4) | \\r
798 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
799 },\r
800 /* MyRGMII1 -> RGMII1_TXC -> U14 */\r
801 {\r
802 PIN_PRG1_PRU0_GPO10, PIN_MODE(4) | \\r
803 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
804 },\r
805 /* MyRGMII1 -> RGMII1_TX_CTL -> U15 */\r
806 {\r
807 PIN_PRG1_PRU0_GPO9, PIN_MODE(4) | \\r
808 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
809 },\r
810 {PINMUX_END}\r
811 };\r
812 \r
813 static pinmuxModuleCfg_t gRgmiiPinCfg[] =\r
814 {\r
815 {1, TRUE, gRgmii1PinCfg},\r
816 {PINMUX_END}\r
817 };\r
818 \r
819 \r
820 static pinmuxPerCfg_t gSpi0PinCfg[] =\r
821 {\r
822 /* MySPI1 -> SPI0_CLK -> D13 */\r
823 {\r
824 PIN_SPI0_CLK, PIN_MODE(0) | \\r
825 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
826 },\r
827 /* MySPI1 -> SPI0_CS0 -> D12 */\r
828 {\r
829 PIN_SPI0_CS0, PIN_MODE(0) | \\r
830 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
831 },\r
832 /* MySPI1 -> SPI0_D0 -> A13 */\r
833 {\r
834 PIN_SPI0_D0, PIN_MODE(0) | \\r
835 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
836 },\r
837 /* MySPI1 -> SPI0_D1 -> A14 */\r
838 {\r
839 PIN_SPI0_D1, PIN_MODE(0) | \\r
840 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
841 },\r
842 {PINMUX_END}\r
843 };\r
844 \r
845 static pinmuxModuleCfg_t gSpiPinCfg[] =\r
846 {\r
847 {0, TRUE, gSpi0PinCfg},\r
848 {PINMUX_END}\r
849 };\r
850 \r
851 \r
852 static pinmuxPerCfg_t gSystem0PinCfg[] =\r
853 {\r
854 /* MySYSTEM1 -> EXT_REFCLK1 -> A19 */\r
855 {\r
856 PIN_EXT_REFCLK1, PIN_MODE(0) | \\r
857 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
858 },\r
859 /* MySYSTEM1 -> GPMC0_FCLK_MUX -> R17 */\r
860 {\r
861 PIN_GPMC0_CLK, PIN_MODE(4) | \\r
862 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
863 },\r
864 /* MySYSTEM1 -> PORz_OUT -> E17 */\r
865 {\r
866 PIN_PORZ_OUT, PIN_MODE(0) | \\r
867 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
868 },\r
869 /* MySYSTEM1 -> RESETSTATz -> F16 */\r
870 {\r
871 PIN_RESETSTATZ, PIN_MODE(0) | \\r
872 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
873 },\r
874 /* MySYSTEM1 -> SYNC0_OUT -> D18 */\r
875 {\r
876 PIN_ECAP0_IN_APWM_OUT, PIN_MODE(1) | \\r
877 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
878 },\r
879 {PINMUX_END}\r
880 };\r
881 \r
882 static pinmuxModuleCfg_t gSystemPinCfg[] =\r
883 {\r
884 {0, TRUE, gSystem0PinCfg},\r
885 {PINMUX_END}\r
886 };\r
887 \r
888 \r
889 static pinmuxPerCfg_t gUart0PinCfg[] =\r
890 {\r
891 /* MyUART1 -> UART0_CTSn -> B16 */\r
892 {\r
893 PIN_UART0_CTSN, PIN_MODE(0) | \\r
894 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
895 },\r
896 /* MyUART1 -> UART0_RTSn -> A16 */\r
897 {\r
898 PIN_UART0_RTSN, PIN_MODE(0) | \\r
899 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
900 },\r
901 /* MyUART1 -> UART0_RXD -> D15 */\r
902 {\r
903 PIN_UART0_RXD, PIN_MODE(0) | \\r
904 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
905 },\r
906 /* MyUART1 -> UART0_TXD -> C16 */\r
907 {\r
908 PIN_UART0_TXD, PIN_MODE(0) | \\r
909 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
910 },\r
911 {PINMUX_END}\r
912 };\r
913 \r
914 static pinmuxPerCfg_t gUart1PinCfg[] =\r
915 {\r
916 /* MyUART2 -> UART1_RXD -> E15 */\r
917 {\r
918 PIN_UART1_RXD, PIN_MODE(0) | \\r
919 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
920 },\r
921 /* MyUART2 -> UART1_TXD -> E14 */\r
922 {\r
923 PIN_UART1_TXD, PIN_MODE(0) | \\r
924 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
925 },\r
926 {PINMUX_END}\r
927 };\r
928 \r
929 static pinmuxPerCfg_t gUart3PinCfg[] =\r
930 {\r
931 /* MyUART3 -> UART3_RXD -> D16 */\r
932 {\r
933 PIN_UART1_CTSN, PIN_MODE(4) | \\r
934 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
935 },\r
936 /* MyUART3 -> UART3_TXD -> E16 */\r
937 {\r
938 PIN_UART1_RTSN, PIN_MODE(4) | \\r
939 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
940 },\r
941 {PINMUX_END}\r
942 };\r
943 \r
944 static pinmuxModuleCfg_t gUartPinCfg[] =\r
945 {\r
946 {0, TRUE, gUart0PinCfg},\r
947 {1, TRUE, gUart1PinCfg},\r
948 {3, TRUE, gUart3PinCfg},\r
949 {PINMUX_END}\r
950 };\r
951 \r
952 \r
953 pinmuxBoardCfg_t gAM64x_MainPinmuxData[] =\r
954 {\r
955 {0, gAdcPinCfg},\r
956 {1, gFsi_rxPinCfg},\r
957 {2, gFsi_txPinCfg},\r
958 {3, gGpioPinCfg},\r
959 {4, gI2cPinCfg},\r
960 {5, gMcanPinCfg},\r
961 {6, gMdioPinCfg},\r
962 {7, gMmc1PinCfg},\r
963 {8, gOspiPinCfg},\r
964 {9, gPru_icssg0_mdioPinCfg},\r
965 {10, gPru_icssg0_pruPinCfg},\r
966 {11, gPru_icssg1_mdioPinCfg},\r
967 {12, gPru_icssg1_rgmiiPinCfg},\r
968 {13, gRgmiiPinCfg},\r
969 {14, gSpiPinCfg},\r
970 {15, gSystemPinCfg},\r
971 {16, gUartPinCfg},\r
972 {PINMUX_END}\r
973 };\r
974 \r
975 pinmuxBoardCfg_t gAM64x_WkupPinmuxData[] =\r
976 {\r
977 {0, gMcu_gpioPinCfg},\r
978 {1, gMcu_i2cPinCfg},\r
979 {2, gMcu_systemPinCfg},\r
980 {3, gMcu_uartPinCfg},\r
981 {PINMUX_END}\r
982 };\r