1 /******************************************************************************\r
2 * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com\r
3 *\r
4 * Redistribution and use in source and binary forms, with or without\r
5 * modification, are permitted provided that the following conditions\r
6 * are met:\r
7 *\r
8 * Redistributions of source code must retain the above copyright\r
9 * notice, this list of conditions and the following disclaimer.\r
10 *\r
11 * Redistributions in binary form must reproduce the above copyright\r
12 * notice, this list of conditions and the following disclaimer in the\r
13 * documentation and/or other materials provided with the\r
14 * distribution.\r
15 *\r
16 * Neither the name of Texas Instruments Incorporated nor the names of\r
17 * its contributors may be used to endorse or promote products derived\r
18 * from this software without specific prior written permission.\r
19 *\r
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
31 *\r
32 *****************************************************************************/\r
33 /**\r
34 * \file board_mmr.c\r
35 *\r
36 * \brief MMR configuration file\r
37 *\r
38 * This file contains the function to unlock the MMR registers\r
39 *\r
40 */\r
41 \r
42 #include <ti/csl/soc/am64x/src/cslr_main_ctrl_mmr.h>\r
43 #include <ti/csl/soc/am64x/src/cslr_mcu_ctrl_mmr.h>\r
44 #include <ti/csl/soc/am64x/src/cslr_main_pll_mmr.h>\r
45 #include <ti/csl/soc/am64x/src/cslr_mcu_pll_mmr.h>\r
46 #include "board_internal.h"\r
47 \r
48 #define BOARD_MMR_PASS (1U)\r
49 #define BOARD_MMR_FAIL (0U)\r
50 \r
51 static const uint32_t main_ctrl_mmr_kick_offsets[]= { CSL_MAIN_CTRL_MMR_CFG0_LOCK0_KICK0,\r
52 CSL_MAIN_CTRL_MMR_CFG0_LOCK1_KICK0,\r
53 CSL_MAIN_CTRL_MMR_CFG0_LOCK2_KICK0,\r
54 CSL_MAIN_CTRL_MMR_CFG0_LOCK3_KICK0,\r
55 CSL_MAIN_CTRL_MMR_CFG0_LOCK4_KICK0,\r
56 CSL_MAIN_CTRL_MMR_CFG0_LOCK5_KICK0,\r
57 //CSL_MAIN_CTRL_MMR_CFG0_LOCK6_KICK0,\r
58 //CSL_MAIN_CTRL_MMR_CFG0_LOCK7_KICK0,\r
59 };\r
60 static const uint32_t main_ctrl_mmr_kick_num = sizeof(main_ctrl_mmr_kick_offsets)/sizeof(uint32_t);\r
61 \r
62 static const uint32_t mcu_ctrl_mmr_kick_offsets[]= { CSL_MCU_CTRL_MMR_CFG0_LOCK0_KICK0,\r
63 CSL_MCU_CTRL_MMR_CFG0_LOCK1_KICK0,\r
64 CSL_MCU_CTRL_MMR_CFG0_LOCK2_KICK0,\r
65 CSL_MCU_CTRL_MMR_CFG0_LOCK3_KICK0,\r
66 CSL_MCU_CTRL_MMR_CFG0_LOCK4_KICK0,\r
67 //CSL_MCU_CTRL_MMR_CFG0_LOCK5_KICK0,\r
68 CSL_MCU_CTRL_MMR_CFG0_LOCK6_KICK0,\r
69 //CSL_MCU_CTRL_MMR_CFG0_LOCK7_KICK0,\r
70 };\r
71 static const uint32_t mcu_ctrl_mmr_kick_num = sizeof(mcu_ctrl_mmr_kick_offsets)/sizeof(uint32_t);\r
72 \r
73 \r
74 \r
75 static const uint32_t main_pll_mmr_kick_offsets[]= { CSL_MAIN_PLL_MMR_CFG_PLL0_LOCKKEY0,\r
76 CSL_MAIN_PLL_MMR_CFG_PLL1_LOCKKEY0,\r
77 CSL_MAIN_PLL_MMR_CFG_PLL2_LOCKKEY0,\r
78 //CSL_MAIN_PLL_MMR_CFG_PLL3_LOCKKEY0,\r
79 //CSL_MAIN_PLL_MMR_CFG_PLL4_LOCKKEY0,\r
80 //CSL_MAIN_PLL_MMR_CFG_PLL5_LOCKKEY0,\r
81 //CSL_MAIN_PLL_MMR_CFG_PLL6_LOCKKEY0,\r
82 //CSL_MAIN_PLL_MMR_CFG_PLL7_LOCKKEY0,\r
83 CSL_MAIN_PLL_MMR_CFG_PLL8_LOCKKEY0,\r
84 //CSL_MAIN_PLL_MMR_CFG_PLL9_LOCKKEY0,\r
85 //CSL_MAIN_PLL_MMR_CFG_PLL10_LOCKKEY0,\r
86 //CSL_MAIN_PLL_MMR_CFG_PLL11_LOCKKEY0,\r
87 CSL_MAIN_PLL_MMR_CFG_PLL12_LOCKKEY0,\r
88 };\r
89 static const uint32_t main_pll_mmr_kick_num = sizeof(main_pll_mmr_kick_offsets)/sizeof(uint32_t);\r
90 \r
91 static const uint32_t mcu_pll_mmr_kick_offsets[]= { CSL_MCU_PLL_MMR_CFG_PLL0_LOCKKEY0,\r
92 //CSL_MCU_PLL_MMR_CFG_PLL1_LOCKKEY0,\r
93 //CSL_MCU_PLL_MMR_CFG_PLL2_LOCKKEY0,\r
94 //CSL_MCU_PLL_MMR_CFG_PLL3_LOCKKEY0,\r
95 //CSL_MCU_PLL_MMR_CFG_PLL4_LOCKKEY0,\r
96 //CSL_MCU_PLL_MMR_CFG_PLL5_LOCKKEY0,\r
97 //CSL_MCU_PLL_MMR_CFG_PLL6_LOCKKEY0,\r
98 //CSL_MCU_PLL_MMR_CFG_PLL7_LOCKKEY0,\r
99 //CSL_MCU_PLL_MMR_CFG_PLL8_LOCKKEY0,\r
100 //CSL_MCU_PLL_MMR_CFG_PLL9_LOCKKEY0,\r
101 //CSL_MCU_PLL_MMR_CFG_PLL10_LOCKKEY0,\r
102 //CSL_MCU_PLL_MMR_CFG_PLL11_LOCKKEY0,\r
103 //CSL_MCU_PLL_MMR_CFG_PLL12_LOCKKEY0,\r
104 };\r
105 static const uint32_t mcu_pll_mmr_kick_num = sizeof(mcu_pll_mmr_kick_offsets)/sizeof(uint32_t);\r
106 \r
107 \r
108 #define TEMP_REPLACE_WITH_CSL_MAIN_PADCONFIG_LOCK0_KICK0_OFFSET (0x1008)\r
109 #define TEMP_REPLACE_WITH_CSL_MAIN_PADCONFIG_LOCK1_KICK0_OFFSET (0x5008)\r
110 \r
111 #define TEMP_REPLACE_WITH_CSL_MCU_PADCONFIG_LOCK0_KICK0_OFFSET (0x1008)\r
112 #define TEMP_REPLACE_WITH_CSL_MCU_PADCONFIG_LOCK1_KICK0_OFFSET (0x5008)\r
113 \r
114 static const uint32_t main_padcfg_mmr_kick_offsets[]= { TEMP_REPLACE_WITH_CSL_MAIN_PADCONFIG_LOCK0_KICK0_OFFSET,\r
115 TEMP_REPLACE_WITH_CSL_MAIN_PADCONFIG_LOCK1_KICK0_OFFSET,\r
116 };\r
117 static const uint32_t main_padcfg_mmr_kick_num = sizeof(main_padcfg_mmr_kick_offsets)/sizeof(uint32_t);\r
118 \r
119 static const uint32_t mcu_padcfg_mmr_kick_offsets[]= { TEMP_REPLACE_WITH_CSL_MCU_PADCONFIG_LOCK0_KICK0_OFFSET,\r
120 TEMP_REPLACE_WITH_CSL_MCU_PADCONFIG_LOCK1_KICK0_OFFSET,\r
121 };\r
122 static const uint32_t mcu_padcfg_mmr_kick_num = sizeof(mcu_padcfg_mmr_kick_offsets)/sizeof(uint32_t);\r
123 \r
124 \r
125 \r
126 typedef enum {\r
127 MMR_UNLOCK= 1,\r
128 MMR_LOCK=0\r
129 } mmr_lock_actions_t;\r
130 \r
131 /* define the unlock and lock values */\r
132 #define KICK_LOCK_VAL 0x00000000\r
133 \r
134 #define MAIN_MMR_BASE_ADDRESS CSL_CTRL_MMR0_CFG0_BASE\r
135 #define MCU_MMR_BASE_ADDRESS CSL_MCU_CTRL_MMR0_CFG0_BASE\r
136 \r
137 #define MAIN_PLL_MMR_BASE_ADDRESS CSL_PLL0_CFG_BASE\r
138 #define MCU_PLL_MMR_BASE_ADDRESS CSL_MCU_PLL0_CFG_BASE\r
139 \r
140 #ifdef BUILD_M4F\r
141 #define MAIN_PADCONFIG_MMR_BASE_ADDRESS CSL_PADCFG_CTRL0_CFG0_BASE + 0x60000000\r
142 #define MCU_PADCONFIG_MMR_BASE_ADDRESS CSL_MCU_PADCFG_CTRL0_CFG0_BASE + 0x60000000\r
143 #else\r
144 #define MAIN_PADCONFIG_MMR_BASE_ADDRESS CSL_PADCFG_CTRL0_CFG0_BASE\r
145 #define MCU_PADCONFIG_MMR_BASE_ADDRESS CSL_MCU_PADCFG_CTRL0_CFG0_BASE\r
146 #endif\r
147 \r
148 uint32_t MMR_change_lock(mmr_lock_actions_t target_state, volatile uint32_t * kick0);\r
149 uint32_t generic_mmr_change_all_locks(mmr_lock_actions_t target_state, uint32_t base_addr, const uint32_t * offset_array, uint32_t array_size);\r
150 \r
151 uint32_t MAIN_PADCONFIG_MMR_unlock_all();\r
152 uint32_t MAIN_PADCONFIG_MMR_lock_all();\r
153 uint32_t MAIN_PADCONFIG_MMR_change_all_locks(mmr_lock_actions_t target_state);\r
154 \r
155 uint32_t MCU_PADCONFIG_MMR_unlock_all();\r
156 uint32_t MCU_PADCONFIG_MMR_lock_all();\r
157 uint32_t MCU_PADCONFIG_MMR_change_all_locks(mmr_lock_actions_t target_state);\r
158 \r
159 uint32_t MAIN_CTRL_MMR_unlock_all();\r
160 uint32_t MAIN_CTRL_MMR_lock_all();\r
161 uint32_t MAIN_CTRL_MMR_change_all_locks(mmr_lock_actions_t target_state);\r
162 \r
163 uint32_t MCU_CTRL_MMR_unlock_all();\r
164 uint32_t MCU_CTRL_MMR_lock_all();\r
165 uint32_t MCU_CTRL_MMR_change_all_locks(mmr_lock_actions_t target_state);\r
166 \r
167 uint32_t MAIN_PLL_MMR_unlock_all();\r
168 uint32_t MAIN_PLL_MMR_lock_all();\r
169 uint32_t MAIN_PLL_MMR_change_all_locks(mmr_lock_actions_t target_state);\r
170 \r
171 uint32_t MCU_PLL_MMR_unlock_all();\r
172 uint32_t MCU_PLL_MMR_lock_all();\r
173 uint32_t MCU_PLL_MMR_change_all_locks(mmr_lock_actions_t target_state);\r
174 \r
175 \r
176 uint32_t MMR_change_lock(mmr_lock_actions_t target_state, volatile uint32_t * kick0) {\r
177 volatile uint32_t * kick1 = kick0 + 1;\r
178 uint32_t lock_state = (*kick0 & 0x1); //status is 1 if unlocked, 0 if locked\r
179 \r
180 //If lock state is not what we want, change it\r
181 if (lock_state != (uint32_t) target_state ) {\r
182 switch(target_state) {\r
183 case MMR_LOCK:\r
184 // lock the partition by writing the lock values to the kick lock registers\r
185 *kick0 = KICK_LOCK_VAL;\r
186 *kick1 = KICK_LOCK_VAL;\r
187 break;\r
188 case MMR_UNLOCK:\r
189 // unlock the partition by writing the unlock values to the kick lock registers\r
190 *kick0 = KICK0_UNLOCK_VAL;\r
191 *kick1 = KICK1_UNLOCK_VAL;\r
192 break;\r
193 }\r
194 \r
195 lock_state = (*kick0 & 0x1);\r
196 //Error out if the change did not take effect\r
197 if(lock_state!= (uint32_t) target_state ){\r
198 //Could insert debug statement here\r
199 //printf("SAVV_DEBUG: Error in changing MMR lock state at address %llx", kick0 );\r
200 return BOARD_MMR_FAIL;\r
201 }\r
202 }\r
203 //Return pass if lock is already what we want or if changing lock succeeds\r
204 return BOARD_MMR_PASS;\r
205 }\r
206 uint32_t generic_mmr_change_all_locks(mmr_lock_actions_t target_state, uint32_t base_addr, const uint32_t * offset_array, uint32_t array_size) {\r
207 uint32_t errors=0;\r
208 uint32_t i=0;\r
209 volatile uint32_t * kick0_ptr;\r
210 for(i=0;i<array_size;i++) {\r
211 kick0_ptr = (volatile uint32_t *) (base_addr + offset_array[i]);\r
212 if(MMR_change_lock(target_state, kick0_ptr) == BOARD_MMR_FAIL){\r
213 errors++;\r
214 }\r
215 }\r
216 return errors;\r
217 }\r
218 //MAIN_CTRL_MMR\r
219 uint32_t MAIN_CTRL_MMR_unlock_all() {\r
220 return MAIN_CTRL_MMR_change_all_locks(MMR_UNLOCK);\r
221 }\r
222 uint32_t MAIN_CTRL_MMR_lock_all() {\r
223 return MAIN_CTRL_MMR_change_all_locks(MMR_LOCK);\r
224 }\r
225 uint32_t MAIN_CTRL_MMR_change_all_locks(mmr_lock_actions_t target_state) {\r
226 uint32_t errors=generic_mmr_change_all_locks(target_state, (uint32_t) MAIN_MMR_BASE_ADDRESS, main_ctrl_mmr_kick_offsets, main_ctrl_mmr_kick_num);\r
227 if(errors==0) { return BOARD_MMR_PASS; }\r
228 else { return BOARD_MMR_FAIL; }\r
229 }\r
230 //MCU_CTRL_MMR\r
231 uint32_t MCU_CTRL_MMR_unlock_all() {\r
232 return MCU_CTRL_MMR_change_all_locks(MMR_UNLOCK);\r
233 }\r
234 uint32_t MCU_CTRL_MMR_lock_all() {\r
235 return MCU_CTRL_MMR_change_all_locks(MMR_LOCK);\r
236 }\r
237 uint32_t MCU_CTRL_MMR_change_all_locks(mmr_lock_actions_t target_state) {\r
238 uint32_t errors=generic_mmr_change_all_locks(target_state, (uint32_t) MCU_MMR_BASE_ADDRESS, mcu_ctrl_mmr_kick_offsets, mcu_ctrl_mmr_kick_num);\r
239 if(errors==0) { return BOARD_MMR_PASS; }\r
240 else { return BOARD_MMR_FAIL; }\r
241 }\r
242 //MAIN_PLL_MMR\r
243 uint32_t MAIN_PLL_MMR_unlock_all() {\r
244 return MAIN_PLL_MMR_change_all_locks(MMR_UNLOCK);\r
245 }\r
246 uint32_t MAIN_PLL_MMR_lock_all() {\r
247 return MAIN_PLL_MMR_change_all_locks(MMR_LOCK);\r
248 }\r
249 uint32_t MAIN_PLL_MMR_change_all_locks(mmr_lock_actions_t target_state) {\r
250 uint32_t errors=generic_mmr_change_all_locks(target_state, (uint32_t) MAIN_PLL_MMR_BASE_ADDRESS, main_pll_mmr_kick_offsets, main_pll_mmr_kick_num);\r
251 if(errors==0) { return BOARD_MMR_PASS; }\r
252 else { return BOARD_MMR_FAIL; }\r
253 }\r
254 //MCU_PLL_MMR\r
255 uint32_t MCU_PLL_MMR_unlock_all() {\r
256 return MCU_PLL_MMR_change_all_locks(MMR_UNLOCK);\r
257 }\r
258 uint32_t MCU_PLL_MMR_lock_all() {\r
259 return MCU_PLL_MMR_change_all_locks(MMR_LOCK);\r
260 }\r
261 uint32_t MCU_PLL_MMR_change_all_locks(mmr_lock_actions_t target_state) {\r
262 uint32_t errors=generic_mmr_change_all_locks(target_state, (uint32_t) MCU_PLL_MMR_BASE_ADDRESS, mcu_pll_mmr_kick_offsets, mcu_pll_mmr_kick_num);\r
263 if(errors==0) { return BOARD_MMR_PASS; }\r
264 else { return BOARD_MMR_FAIL; }\r
265 }\r
266 //MAIN_PADCONFIG_MMR\r
267 uint32_t MAIN_PADCONFIG_MMR_unlock_all() {\r
268 return MAIN_PADCONFIG_MMR_change_all_locks(MMR_UNLOCK);\r
269 }\r
270 uint32_t MAIN_PADCONFIG_MMR_lock_all() {\r
271 return MAIN_PADCONFIG_MMR_change_all_locks(MMR_LOCK);\r
272 }\r
273 uint32_t MAIN_PADCONFIG_MMR_change_all_locks(mmr_lock_actions_t target_state) {\r
274 uint32_t errors=generic_mmr_change_all_locks(target_state, (uint32_t) MAIN_PADCONFIG_MMR_BASE_ADDRESS, main_padcfg_mmr_kick_offsets, main_padcfg_mmr_kick_num);\r
275 if(errors==0) { return BOARD_MMR_PASS; }\r
276 else { return BOARD_MMR_FAIL; }\r
277 }\r
278 //MCU_PADCONFIG_MMR\r
279 uint32_t MCU_PADCONFIG_MMR_unlock_all() {\r
280 return MCU_PADCONFIG_MMR_change_all_locks(MMR_UNLOCK);\r
281 }\r
282 uint32_t MCU_PADCONFIG_MMR_lock_all() {\r
283 return MCU_PADCONFIG_MMR_change_all_locks(MMR_LOCK);\r
284 }\r
285 uint32_t MCU_PADCONFIG_MMR_change_all_locks(mmr_lock_actions_t target_state) {\r
286 uint32_t errors=generic_mmr_change_all_locks(target_state, (uint32_t) MCU_PADCONFIG_MMR_BASE_ADDRESS, mcu_padcfg_mmr_kick_offsets, mcu_padcfg_mmr_kick_num);\r
287 if(errors==0) { return BOARD_MMR_PASS; }\r
288 else { return BOARD_MMR_FAIL; }\r
289 }\r
290 \r
291 /**\r
292 * \brief Unlocks MMR registers\r
293 *\r
294 * \return Board_STATUS\r
295 */\r
296 Board_STATUS Board_unlockMMR(void)\r
297 {\r
298 MAIN_PADCONFIG_MMR_unlock_all();\r
299 MCU_PADCONFIG_MMR_unlock_all();\r
300 return BOARD_SOK;\r
301 }\r
302 \r
303 /**\r
304 * \brief Locks MMR registers\r
305 *\r
306 * \return Board_STATUS\r
307 */\r
308 Board_STATUS Board_lockMMR(void)\r
309 {\r
310 MAIN_PADCONFIG_MMR_lock_all();\r
311 MCU_PADCONFIG_MMR_lock_all();\r
312 return BOARD_SOK;\r
313 }\r
314 \r