4efd4cc031812a07af5d1f6573c0f7f415413abb
1 /**
2 * Redistribution and use in source and binary forms, with or without
3 * modification, are permitted provided that the following conditions
4 * are met:
5 *
6 * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 *
9 * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the
12 * distribution.
13 *
14 * Neither the name of Texas Instruments Incorporated nor the names of
15 * its contributors may be used to endorse or promote products derived
16 * from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 */
32 /**
33 * \file AM65xx_pinmux_data.c
34 *
35 * \brief This file contains the pin mux configurations for the boards.
36 * These are prepared based on how the peripherals are extended on
37 * the boards.
38 *
39 */
41 /* ========================================================================== */
42 /* Include Files */
43 /* ========================================================================== */
45 #include "AM65xx_pinmux.h"
47 /** Peripheral Pin Configurations */
50 static pinmuxPerCfg_t gCal0PinCfg[] =
51 {
52 {PINMUX_END}
53 };
55 static pinmuxModuleCfg_t gCalPinCfg[] =
56 {
57 {0, TRUE, gCal0PinCfg},
58 {PINMUX_END}
59 };
62 static pinmuxPerCfg_t gDdr0PinCfg[] =
63 {
64 {PINMUX_END}
65 };
67 static pinmuxModuleCfg_t gDdrPinCfg[] =
68 {
69 {0, TRUE, gDdr0PinCfg},
70 {PINMUX_END}
71 };
74 static pinmuxPerCfg_t gDebugss0PinCfg[] =
75 {
76 /* DEBUGSS -> TMS -> A21 */
77 {
78 PIN_TMS, PIN_MODE(0) | \
79 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
80 },
81 /* DEBUGSS -> TDI -> C20 */
82 {
83 PIN_TDI, PIN_MODE(0) | \
84 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
85 },
86 /* DEBUGSS -> TDO -> A20 */
87 {
88 PIN_TDO, PIN_MODE(0) | \
89 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
90 },
91 {PINMUX_END}
92 };
94 static pinmuxModuleCfg_t gDebugssPinCfg[] =
95 {
96 {0, TRUE, gDebugss0PinCfg},
97 {PINMUX_END}
98 };
101 static pinmuxPerCfg_t gEcap0PinCfg[] =
102 {
103 /* ECAP0 -> ECAP0_IN_APWM_OUT -> D21 */
104 {
105 PIN_ECAP0_IN_APWM_OUT, PIN_MODE(0) | \
106 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
107 },
108 {PINMUX_END}
109 };
111 static pinmuxModuleCfg_t gEcapPinCfg[] =
112 {
113 {0, TRUE, gEcap0PinCfg},
114 {PINMUX_END}
115 };
118 static pinmuxPerCfg_t gGpio0PinCfg[] =
119 {
120 /* GPIO0 -> GPIO0_61 -> AF27 */
121 {
122 PIN_PRG1_PRU0_GPO5, PIN_MODE(7) | \
123 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
124 },
125 /* GPIO0 -> GPIO0_64 -> AF28 */
126 {
127 PIN_PRG1_PRU0_GPO8, PIN_MODE(7) | \
128 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
129 },
130 /* GPIO0 -> GPIO0_81 -> AC22 */
131 {
132 PIN_PRG1_PRU1_GPO5, PIN_MODE(7) | \
133 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
134 },
135 /* GPIO0 -> GPIO0_84 -> AE24 */
136 {
137 PIN_PRG1_PRU1_GPO8, PIN_MODE(7) | \
138 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
139 },
140 {PINMUX_END}
141 };
142 static pinmuxPerCfg_t gGpio1PinCfg[] =
143 {
144 #if !(defined(AM65XX_BETA_BOARD))
145 /* GPIO1 -> GPIO1_14 -> B23 */
146 {
147 PIN_MMC0_SDWP, PIN_MODE(7) | \
148 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
149 },
150 #endif
151 /* GPIO1 -> GPIO1_34 -> V28 */
152 {
153 PIN_PRG0_PRU0_GPO5, PIN_MODE(7) | \
154 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
155 },
156 /* GPIO1 -> GPIO1_37 -> V27 */
157 {
158 PIN_PRG0_PRU0_GPO8, PIN_MODE(7) | \
159 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
160 },
161 /* GPIO1 -> GPIO1_39 -> U25 */
162 {
163 PIN_PRG0_PRU0_GPO10, PIN_MODE(7) | \
164 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
165 },
166 /* GPIO1 -> GPIO1_57 -> W27 */
167 {
168 PIN_PRG0_PRU1_GPO8, PIN_MODE(7) | \
169 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
170 },
171 /* GPIO1 -> GPIO1_81 -> F18 */
172 {
173 PIN_NMIN, PIN_MODE(7) | \
174 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
175 },
176 {PINMUX_END}
177 };
179 static pinmuxModuleCfg_t gGpioPinCfg[] =
180 {
181 {0, TRUE, gGpio0PinCfg},
182 {1, TRUE, gGpio1PinCfg},
183 {PINMUX_END}
184 };
187 static pinmuxPerCfg_t gI2c0PinCfg[] =
188 {
189 /* I2C0 -> I2C0_SCL -> D20 */
190 {
191 PIN_I2C0_SCL, PIN_MODE(0) | \
192 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
193 },
194 /* I2C0 -> I2C0_SDA -> C21 */
195 {
196 PIN_I2C0_SDA, PIN_MODE(0) | \
197 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
198 },
199 {PINMUX_END}
200 };
201 static pinmuxPerCfg_t gI2c1PinCfg[] =
202 {
203 /* I2C1 -> I2C1_SCL -> B21 */
204 {
205 PIN_I2C1_SCL, PIN_MODE(0) | \
206 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
207 },
208 /* I2C1 -> I2C1_SDA -> E21 */
209 {
210 PIN_I2C1_SDA, PIN_MODE(0) | \
211 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
212 },
213 {PINMUX_END}
214 };
215 static pinmuxPerCfg_t gI2c2PinCfg[] =
216 {
217 /* I2C2 -> I2C2_SCL -> T27 */
218 {
219 PIN_GPMC0_CSN3, PIN_MODE(5) | \
220 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
221 },
222 /* I2C2 -> I2C2_SDA -> R25 */
223 {
224 PIN_GPMC0_CSN2, PIN_MODE(5) | \
225 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
226 },
227 {PINMUX_END}
228 };
230 static pinmuxModuleCfg_t gI2cPinCfg[] =
231 {
232 {0, TRUE, gI2c0PinCfg},
233 {1, TRUE, gI2c1PinCfg},
234 {2, TRUE, gI2c2PinCfg},
235 {PINMUX_END}
236 };
239 static pinmuxPerCfg_t gMcu_adc0PinCfg[] =
240 {
241 {PINMUX_END}
242 };
243 static pinmuxPerCfg_t gMcu_adc1PinCfg[] =
244 {
245 {PINMUX_END}
246 };
248 static pinmuxModuleCfg_t gMcu_adcPinCfg[] =
249 {
250 {0, TRUE, gMcu_adc0PinCfg},
251 {1, TRUE, gMcu_adc1PinCfg},
252 {PINMUX_END}
253 };
256 static pinmuxPerCfg_t gMcu_cpsw0PinCfg[] =
257 {
258 /* MCU_CPSW -> MCU_RGMII1_TX_CTL -> N4 */
259 {
260 PIN_MCU_RGMII1_TX_CTL, PIN_MODE(0) | \
261 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
262 },
263 /* MCU_CPSW -> MCU_RGMII1_RX_CTL -> N5 */
264 {
265 PIN_MCU_RGMII1_RX_CTL, PIN_MODE(0) | \
266 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
267 },
268 /* MCU_CPSW -> MCU_RGMII1_TD3 -> M2 */
269 {
270 PIN_MCU_RGMII1_TD3, PIN_MODE(0) | \
271 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
272 },
273 /* MCU_CPSW -> MCU_RGMII1_TD2 -> M3 */
274 {
275 PIN_MCU_RGMII1_TD2, PIN_MODE(0) | \
276 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
277 },
278 /* MCU_CPSW -> MCU_RGMII1_TD1 -> M4 */
279 {
280 PIN_MCU_RGMII1_TD1, PIN_MODE(0) | \
281 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
282 },
283 /* MCU_CPSW -> MCU_RGMII1_TD0 -> M5 */
284 {
285 PIN_MCU_RGMII1_TD0, PIN_MODE(0) | \
286 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
287 },
288 /* MCU_CPSW -> MCU_RGMII1_RD3 -> L2 */
289 {
290 PIN_MCU_RGMII1_RD3, PIN_MODE(0) | \
291 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
292 },
293 /* MCU_CPSW -> MCU_RGMII1_RD2 -> L5 */
294 {
295 PIN_MCU_RGMII1_RD2, PIN_MODE(0) | \
296 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
297 },
298 /* MCU_CPSW -> MCU_RGMII1_RD1 -> M6 */
299 {
300 PIN_MCU_RGMII1_RD1, PIN_MODE(0) | \
301 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
302 },
303 /* MCU_CPSW -> MCU_RGMII1_RD0 -> L6 */
304 {
305 PIN_MCU_RGMII1_RD0, PIN_MODE(0) | \
306 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
307 },
308 /* MCU_CPSW -> MCU_RGMII1_TXC -> N1 */
309 {
310 PIN_MCU_RGMII1_TXC, PIN_MODE(0) | \
311 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
312 },
313 /* MCU_CPSW -> MCU_RGMII1_RXC -> M1 */
314 {
315 PIN_MCU_RGMII1_RXC, PIN_MODE(0) | \
316 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
317 },
318 {PINMUX_END}
319 };
321 static pinmuxModuleCfg_t gMcu_cpswPinCfg[] =
322 {
323 {0, TRUE, gMcu_cpsw0PinCfg},
324 {PINMUX_END}
325 };
328 static pinmuxPerCfg_t gMcu_fss0_ospi0PinCfg[] =
329 {
330 /* MCU_OSPI0 -> MCU_OSPI0_CLK -> V1 */
331 {
332 PIN_MCU_OSPI0_CLK, PIN_MODE(0) | \
333 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
334 },
335 /* MCU_OSPI0 -> MCU_OSPI0_CSn0 -> R4 */
336 {
337 PIN_MCU_OSPI0_CSN0, PIN_MODE(0) | \
338 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
339 },
340 /* MCU_OSPI0 -> MCU_OSPI0_D0 -> U4 */
341 {
342 PIN_MCU_OSPI0_D0, PIN_MODE(0) | \
343 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
344 },
345 /* MCU_OSPI0 -> MCU_OSPI0_D1 -> U5 */
346 {
347 PIN_MCU_OSPI0_D1, PIN_MODE(0) | \
348 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
349 },
350 /* MCU_OSPI0 -> MCU_OSPI0_D2 -> T2 */
351 {
352 PIN_MCU_OSPI0_D2, PIN_MODE(0) | \
353 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
354 },
355 /* MCU_OSPI0 -> MCU_OSPI0_D3 -> T3 */
356 {
357 PIN_MCU_OSPI0_D3, PIN_MODE(0) | \
358 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
359 },
360 /* MCU_OSPI0 -> MCU_OSPI0_D4 -> T4 */
361 {
362 PIN_MCU_OSPI0_D4, PIN_MODE(0) | \
363 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
364 },
365 /* MCU_OSPI0 -> MCU_OSPI0_D5 -> T5 */
366 {
367 PIN_MCU_OSPI0_D5, PIN_MODE(0) | \
368 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
369 },
370 /* MCU_OSPI0 -> MCU_OSPI0_D6 -> R2 */
371 {
372 PIN_MCU_OSPI0_D6, PIN_MODE(0) | \
373 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
374 },
375 /* MCU_OSPI0 -> MCU_OSPI0_D7 -> R3 */
376 {
377 PIN_MCU_OSPI0_D7, PIN_MODE(0) | \
378 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
379 },
380 /* MCU_OSPI0 -> MCU_OSPI0_DQS -> U2 */
381 {
382 PIN_MCU_OSPI0_DQS, PIN_MODE(0) | \
383 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
384 },
385 {PINMUX_END}
386 };
388 static pinmuxModuleCfg_t gMcu_fss0_ospiPinCfg[] =
389 {
390 {0, TRUE, gMcu_fss0_ospi0PinCfg},
391 {PINMUX_END}
392 };
395 static pinmuxPerCfg_t gMcu_i2c0PinCfg[] =
396 {
397 /* MCU_I2C0 -> MCU_I2C0_SCL -> AD8 */
398 {
399 PIN_MCU_I2C0_SCL, PIN_MODE(0) | \
400 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
401 },
402 /* MCU_I2C0 -> MCU_I2C0_SDA -> AD7 */
403 {
404 PIN_MCU_I2C0_SDA, PIN_MODE(0) | \
405 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
406 },
407 {PINMUX_END}
408 };
410 static pinmuxModuleCfg_t gMcu_i2cPinCfg[] =
411 {
412 {0, TRUE, gMcu_i2c0PinCfg},
413 {PINMUX_END}
414 };
417 static pinmuxPerCfg_t gMcu_mdio0PinCfg[] =
418 {
419 /* MCU_MDIO0 -> MCU_MDIO0_MDC -> L1 */
420 {
421 PIN_MCU_MDIO0_MDC, PIN_MODE(0) | \
422 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
423 },
424 /* MCU_MDIO0 -> MCU_MDIO0_MDIO -> L4 */
425 {
426 PIN_MCU_MDIO0_MDIO, PIN_MODE(0) | \
427 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
428 },
429 {PINMUX_END}
430 };
432 static pinmuxModuleCfg_t gMcu_mdioPinCfg[] =
433 {
434 {0, TRUE, gMcu_mdio0PinCfg},
435 {PINMUX_END}
436 };
439 static pinmuxPerCfg_t gMcu_spi0PinCfg[] =
440 {
441 /* MCU_SPI -> MCU_SPI0_CLK -> Y1 */
442 {
443 PIN_MCU_SPI0_CLK, PIN_MODE(0) | \
444 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
445 },
446 /* MCU_SPI -> MCU_SPI0_CS0 -> Y4 */
447 {
448 PIN_MCU_SPI0_CS0, PIN_MODE(0) | \
449 ((~PIN_PULL_DISABLE) & (PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
450 },
451 /* MCU_SPI -> MCU_SPI0_D0 -> Y3 */
452 {
453 PIN_MCU_SPI0_D0, PIN_MODE(0) | \
454 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
455 },
456 {PINMUX_END}
457 };
459 static pinmuxModuleCfg_t gMcu_spiPinCfg[] =
460 {
461 {0, TRUE, gMcu_spi0PinCfg},
462 {PINMUX_END}
463 };
466 static pinmuxPerCfg_t gMcu_uart0PinCfg[] =
467 {
468 /* MCU_UART0 -> MCU_UART0_RXD -> P4 */
469 {
470 PIN_MCU_OSPI1_D1, PIN_MODE(4) | \
471 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
472 },
473 /* MCU_UART0 -> MCU_UART0_TXD -> P5 */
474 {
475 PIN_MCU_OSPI1_D2, PIN_MODE(4) | \
476 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
477 },
478 /* MCU_UART0 -> MCU_UART0_CTS -> P1 */
479 {
480 PIN_MCU_OSPI1_D3, PIN_MODE(4) | \
481 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
482 },
483 /* MCU_UART0 -> MCU_UART0_RTS -> P4 */
484 {
485 PIN_MCU_OSPI1_CSN1, PIN_MODE(4) | \
486 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
487 },
488 {PINMUX_END}
489 };
491 static pinmuxModuleCfg_t gMcu_uartPinCfg[] =
492 {
493 {0, TRUE, gMcu_uart0PinCfg},
494 {PINMUX_END}
495 };
498 static pinmuxPerCfg_t gMmc0PinCfg[] =
499 {
500 /* MMC0 -> MMC0_CLK -> B25 */
501 {
502 PIN_MMC0_CLK, PIN_MODE(0) | \
503 ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
504 },
505 /* MMC0 -> MMC0_CMD -> B27 */
506 {
507 PIN_MMC0_CMD, PIN_MODE(0) | \
508 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
509 },
510 /* MMC0 -> MMC0_DAT0 -> A26 */
511 {
512 PIN_MMC0_DAT0, PIN_MODE(0) | \
513 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
514 },
515 /* MMC0 -> MMC0_DAT1 -> E25 */
516 {
517 PIN_MMC0_DAT1, PIN_MODE(0) | \
518 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
519 },
520 /* MMC0 -> MMC0_DAT2 -> C26 */
521 {
522 PIN_MMC0_DAT2, PIN_MODE(0) | \
523 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
524 },
525 /* MMC0 -> MMC0_DAT3 -> A25 */
526 {
527 PIN_MMC0_DAT3, PIN_MODE(0) | \
528 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
529 },
530 /* MMC0 -> MMC0_DAT4 -> E24 */
531 {
532 PIN_MMC0_DAT4, PIN_MODE(0) | \
533 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
534 },
535 /* MMC0 -> MMC0_DAT5 -> A24 */
536 {
537 PIN_MMC0_DAT5, PIN_MODE(0) | \
538 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
539 },
540 /* MMC0 -> MMC0_DAT6 -> B26 */
541 {
542 PIN_MMC0_DAT6, PIN_MODE(0) | \
543 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
544 },
545 /* MMC0 -> MMC0_DAT7 -> D25 */
546 {
547 PIN_MMC0_DAT7, PIN_MODE(0) | \
548 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
549 },
550 /* MMC0 -> MMC0_DS -> C25 */
551 {
552 PIN_MMC0_DS, PIN_MODE(0) | \
553 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
554 },
555 /* MMC0 -> MMC0_SDCD -> A23 */
556 {
557 PIN_MMC0_SDCD, PIN_MODE(0) | \
558 ((PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION | ~PIN_PULL_DISABLE))
559 },
560 #if defined(AM65XX_BETA_BOARD)
561 /* MMC0 -> MMC0_SDWP -> B23 */
562 {
563 PIN_MMC0_SDWP, PIN_MODE(0) | \
564 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
565 },
566 #endif
567 {PINMUX_END}
568 };
569 static pinmuxPerCfg_t gMmc1PinCfg[] =
570 {
571 /* MMC1 -> MMC1_CLK -> C27 */
572 {
573 PIN_MMC1_CLK, PIN_MODE(0) | \
574 ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
575 },
576 /* MMC1 -> MMC1_CMD -> C28 */
577 {
578 PIN_MMC1_CMD, PIN_MODE(0) | \
579 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
580 },
581 /* MMC1 -> MMC1_DAT0 -> D28 */
582 {
583 PIN_MMC1_DAT0, PIN_MODE(0) | \
584 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
585 },
586 /* MMC1 -> MMC1_DAT1 -> E27 */
587 {
588 PIN_MMC1_DAT1, PIN_MODE(0) | \
589 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
590 },
591 /* MMC1 -> MMC1_DAT2 -> D26 */
592 {
593 PIN_MMC1_DAT2, PIN_MODE(0) | \
594 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
595 },
596 /* MMC1 -> MMC1_DAT3 -> D27 */
597 {
598 PIN_MMC1_DAT3, PIN_MODE(0) | \
599 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
600 },
601 /* MMC1 -> MMC1_SDCD -> B24 */
602 {
603 PIN_MMC1_SDCD, PIN_MODE(0) | \
604 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
605 },
606 {PINMUX_END}
607 };
609 static pinmuxModuleCfg_t gMmcPinCfg[] =
610 {
611 {0, TRUE, gMmc0PinCfg},
612 {1, TRUE, gMmc1PinCfg},
613 {PINMUX_END}
614 };
617 static pinmuxPerCfg_t gOldi0PinCfg[] =
618 {
619 {PINMUX_END}
620 };
622 static pinmuxModuleCfg_t gOldiPinCfg[] =
623 {
624 {0, TRUE, gOldi0PinCfg},
625 {PINMUX_END}
626 };
629 static pinmuxPerCfg_t gOsc00PinCfg[] =
630 {
631 {PINMUX_END}
632 };
634 static pinmuxModuleCfg_t gOsc0PinCfg[] =
635 {
636 {0, TRUE, gOsc00PinCfg},
637 {PINMUX_END}
638 };
641 static pinmuxPerCfg_t gPru_icssg2_mdio0PinCfg[] =
642 {
643 /* PRU_ICSSG2_MDIO -> PRG2_MDIO0_MDIO -> AC19 */
644 {
645 PIN_PRG2_PRU0_GPO7, PIN_MODE(2) | \
646 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
647 },
648 /* PRU_ICSSG2_MDIO -> PRG2_MDIO0_MDC -> AE15 */
649 {
650 PIN_PRG2_PRU1_GPO7, PIN_MODE(2) | \
651 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
652 },
653 {PINMUX_END}
654 };
656 static pinmuxModuleCfg_t gPru_icssg2_mdioPinCfg[] =
657 {
658 {0, TRUE, gPru_icssg2_mdio0PinCfg},
659 {PINMUX_END}
660 };
663 static pinmuxPerCfg_t gPru_icssg2_rgmii1PinCfg[] =
664 {
665 /* PRU_ICSSG2_RGMII1 -> PRG2_RGMII1_RD0 -> AF18 */
666 {
667 PIN_PRG2_PRU0_GPO0, PIN_MODE(2) | \
668 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
669 },
670 /* PRU_ICSSG2_RGMII1 -> PRG2_RGMII1_RD1 -> AE18 */
671 {
672 PIN_PRG2_PRU0_GPO1, PIN_MODE(2) | \
673 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
674 },
675 /* PRU_ICSSG2_RGMII1 -> PRG2_RGMII1_RD2 -> AH17 */
676 {
677 PIN_PRG2_PRU0_GPO2, PIN_MODE(2) | \
678 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
679 },
680 /* PRU_ICSSG2_RGMII1 -> PRG2_RGMII1_RD3 -> AG18 */
681 {
682 PIN_PRG2_PRU0_GPO3, PIN_MODE(2) | \
683 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
684 },
685 /* PRU_ICSSG2_RGMII1 -> PRG2_RGMII1_TD0 -> AH16 */
686 {
687 PIN_PRG2_PRU0_GPO8, PIN_MODE(2) | \
688 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
689 },
690 /* PRU_ICSSG2_RGMII1 -> PRG2_RGMII1_TD1 -> AG16 */
691 {
692 PIN_PRG2_PRU0_GPO9, PIN_MODE(2) | \
693 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
694 },
695 /* PRU_ICSSG2_RGMII1 -> PRG2_RGMII1_TD2 -> AF16 */
696 {
697 PIN_PRG2_PRU0_GPO10, PIN_MODE(2) | \
698 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
699 },
700 /* PRU_ICSSG2_RGMII1 -> PRG2_RGMII1_TD3 -> AE16 */
701 {
702 PIN_PRG2_PRU0_GPO11, PIN_MODE(2) | \
703 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
704 },
705 /* PRU_ICSSG2_RGMII1 -> PRG2_RGMII1_TXC -> AD16 */
706 {
707 PIN_PRG2_PRU0_GPO16, PIN_MODE(2) | \
708 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
709 },
710 /* PRU_ICSSG2_RGMII1 -> PRG2_RGMII1_TX_CTL -> AE17 */
711 {
712 PIN_PRG2_PRU0_GPO6, PIN_MODE(2) | \
713 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
714 },
715 /* PRU_ICSSG2_RGMII1 -> PRG2_RGMII1_RXC -> AF17 */
716 {
717 PIN_PRG2_PRU0_GPO5, PIN_MODE(2) | \
718 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
719 },
720 /* PRU_ICSSG2_RGMII1 -> PRG2_RGMII1_RX_CTL -> AG17 */
721 {
722 PIN_PRG2_PRU0_GPO4, PIN_MODE(2) | \
723 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
724 },
725 {PINMUX_END}
726 };
727 static pinmuxPerCfg_t gPru_icssg2_rgmii2PinCfg[] =
728 {
729 /* PRU_ICSSG2_RGMII2 -> PRG2_RGMII2_RD0 -> AH15 */
730 {
731 PIN_PRG2_PRU1_GPO0, PIN_MODE(2) | \
732 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
733 },
734 /* PRU_ICSSG2_RGMII2 -> PRG2_RGMII2_RD1 -> AC16 */
735 {
736 PIN_PRG2_PRU1_GPO1, PIN_MODE(2) | \
737 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
738 },
739 /* PRU_ICSSG2_RGMII2 -> PRG2_RGMII2_RD2 -> AD17 */
740 {
741 PIN_PRG2_PRU1_GPO2, PIN_MODE(2) | \
742 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
743 },
744 /* PRU_ICSSG2_RGMII2 -> PRG2_RGMII2_RD3 -> AH14 */
745 {
746 PIN_PRG2_PRU1_GPO3, PIN_MODE(2) | \
747 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
748 },
749 /* PRU_ICSSG2_RGMII2 -> PRG2_RGMII2_TD0 -> AD15 */
750 {
751 PIN_PRG2_PRU1_GPO8, PIN_MODE(2) | \
752 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
753 },
754 /* PRU_ICSSG2_RGMII2 -> PRG2_RGMII2_TD1 -> AF14 */
755 {
756 PIN_PRG2_PRU1_GPO9, PIN_MODE(2) | \
757 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
758 },
759 /* PRU_ICSSG2_RGMII2 -> PRG2_RGMII2_TD2 -> AC15 */
760 {
761 PIN_PRG2_PRU1_GPO10, PIN_MODE(2) | \
762 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
763 },
764 /* PRU_ICSSG2_RGMII2 -> PRG2_RGMII2_TD3 -> AD14 */
765 {
766 PIN_PRG2_PRU1_GPO11, PIN_MODE(2) | \
767 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
768 },
769 /* PRU_ICSSG2_RGMII2 -> PRG2_RGMII2_TXC -> AE14 */
770 {
771 PIN_PRG2_PRU1_GPO16, PIN_MODE(2) | \
772 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
773 },
774 /* PRU_ICSSG2_RGMII2 -> PRG2_RGMII2_TX_CTL -> AC17 */
775 {
776 PIN_PRG2_PRU1_GPO6, PIN_MODE(2) | \
777 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
778 },
779 /* PRU_ICSSG2_RGMII2 -> PRG2_RGMII2_RXC -> AG15 */
780 {
781 PIN_PRG2_PRU1_GPO5, PIN_MODE(2) | \
782 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
783 },
784 /* PRU_ICSSG2_RGMII2 -> PRG2_RGMII2_RX_CTL -> AG14 */
785 {
786 PIN_PRG2_PRU1_GPO4, PIN_MODE(2) | \
787 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
788 },
789 {PINMUX_END}
790 };
792 static pinmuxModuleCfg_t gPru_icssg2_rgmiiPinCfg[] =
793 {
794 {1, TRUE, gPru_icssg2_rgmii1PinCfg},
795 {2, TRUE, gPru_icssg2_rgmii2PinCfg},
796 {PINMUX_END}
797 };
800 static pinmuxPerCfg_t gSerdes0PinCfg[] =
801 {
802 {PINMUX_END}
803 };
804 static pinmuxPerCfg_t gSerdes1PinCfg[] =
805 {
806 {PINMUX_END}
807 };
809 static pinmuxModuleCfg_t gSerdesPinCfg[] =
810 {
811 {0, TRUE, gSerdes0PinCfg},
812 {1, TRUE, gSerdes1PinCfg},
813 {PINMUX_END}
814 };
816 static pinmuxPerCfg_t gSpi0PinCfg[] =
817 {
818 /* SPI0 -> SPI0_CLK -> AH13 */
819 {
820 PIN_SPI0_CLK, PIN_MODE(0) | \
821 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
822 },
823 /* SPI0 -> SPI0_D0 -> AE13 */
824 {
825 PIN_SPI0_D0, PIN_MODE(0) | \
826 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
827 },
828 /* SPI0 -> SPI0_D1 -> AD13 */
829 {
830 PIN_SPI0_D1, PIN_MODE(0) | \
831 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
832 },
833 /* SPI0 -> SPI0_CS0 -> AG13 */
834 {
835 PIN_SPI0_CS0, PIN_MODE(0) | \
836 ((~PIN_PULL_DISABLE) & (PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
837 },
838 /* SPI0 -> SPI0_CS1 -> AF13 */
839 {
840 PIN_SPI0_CS1, PIN_MODE(0) | \
841 ((~PIN_PULL_DISABLE) & (PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
842 },
843 {PINMUX_END}
844 };
846 static pinmuxPerCfg_t gSpi1PinCfg[] =
847 {
848 /* SPI1 -> SPI1_CLK -> AH12 */
849 {
850 PIN_SPI1_CLK, PIN_MODE(0) | \
851 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
852 },
853 /* SPI1 -> SPI1_D0 -> AE12 */
854 {
855 PIN_SPI1_D0, PIN_MODE(0) | \
856 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
857 },
858 /* SPI1 -> SPI1_D1 -> AF12 */
859 {
860 PIN_SPI1_D1, PIN_MODE(0) | \
861 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
862 },
863 /* SPI1 -> SPI1_CS0 -> AD12 */
864 {
865 PIN_SPI1_CS0, PIN_MODE(0) | \
866 ((~PIN_PULL_DISABLE) & (PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
867 },
868 /* SPI1 -> SPI1_CS1 -> AG12 */
869 {
870 PIN_SPI1_CS1, PIN_MODE(0) | \
871 ((~PIN_PULL_DISABLE) & (PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
872 },
873 {PINMUX_END}
874 };
876 static pinmuxModuleCfg_t gSpiPinCfg[] =
877 {
878 {0, TRUE, gSpi0PinCfg},
879 {1, TRUE, gSpi1PinCfg},
880 {PINMUX_END}
881 };
884 pinmuxPerCfg_t gSystem0PinCfgPG1[] =
885 {
886 /* SYSTEM -> RESETz -> F17 */
887 {
888 PIN_RESETZ, PIN_MODE(0) | \
889 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
890 },
891 /* SYSTEM -> PORz -> E19 */
892 {
893 PIN_PORZ, PIN_MODE(0) | \
894 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
895 },
896 /* SYSTEM -> RESETSTATz -> D19 */
897 {
898 PIN_RESETSTATZ, PIN_MODE(0) | \
899 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
900 },
901 /* SYSTEM -> PORz_OUT -> C19 */
902 {
903 PIN_PORZ_OUT, PIN_MODE(0) | \
904 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
905 },
906 /* SYSTEM -> SOC_SAFETY_ERRORn -> E20 */
907 {
908 PIN_SOC_SAFETY_ERRORN, PIN_MODE(0) | \
909 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
910 },
911 {PINMUX_END}
912 };
914 static pinmuxPerCfg_t gSystem0PinCfg[] =
915 {
916 /* SYSTEM -> RESETz -> F17 */
917 {
918 PIN_RESETZ, PIN_MODE(0) | \
919 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
920 },
921 /* SYSTEM -> PORz -> E19 */
922 {
923 PIN_PORZ, PIN_MODE(0) | \
924 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
925 },
926 /* SYSTEM -> RESETSTATz -> D19 */
927 {
928 PIN_RESETSTATZ, PIN_MODE(0) | \
929 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
930 },
931 /* SYSTEM -> PORz_OUT -> C19 */
932 {
933 PIN_PORZ_OUT, PIN_MODE(0) | \
934 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
935 },
936 /* SYSTEM -> SOC_SAFETY_ERRORn -> E20 */
937 {
938 PIN_SOC_SAFETY_ERRORN, PIN_MODE(0) | \
939 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
940 },
941 {PINMUX_END}
942 };
944 pinmuxModuleCfg_t gSystemPinCfg[] =
945 {
946 {0, FALSE, gSystem0PinCfg},
947 {PINMUX_END}
948 };
951 static pinmuxPerCfg_t gTimer0PinCfg[] =
952 {
953 /* TIMER -> TIMER_IO0 -> B22 */
954 {
955 PIN_TIMER_IO0, PIN_MODE(0) | \
956 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
957 },
958 /* TIMER -> TIMER_IO1 -> C23 */
959 {
960 PIN_TIMER_IO1, PIN_MODE(0) | \
961 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
962 },
963 {PINMUX_END}
964 };
966 static pinmuxModuleCfg_t gTimerPinCfg[] =
967 {
968 {0, TRUE, gTimer0PinCfg},
969 {PINMUX_END}
970 };
972 static pinmuxPerCfg_t gUart0PinCfg[] =
973 {
974 /* UART0 -> UART0_RXD -> AF11 */
975 {
976 PIN_UART0_RXD, PIN_MODE(0) | \
977 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
978 },
979 /* UART0 -> UART0_TXD -> AE11 */
980 {
981 PIN_UART0_TXD, PIN_MODE(0) | \
982 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
983 },
984 /* UART0 -> UART0_CTSn -> AG11 */
985 {
986 PIN_UART0_CTSN, PIN_MODE(0) | \
987 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
988 },
989 /* UART0 -> UART0_RTSn -> AD11 */
990 {
991 PIN_UART0_RTSN, PIN_MODE(0) | \
992 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
993 },
994 {PINMUX_END}
995 };
997 static pinmuxPerCfg_t gUart1PinCfg[] =
998 {
999 /* GPIO0 -> GPIO0_83 -> AD23 */
1000 {
1001 PIN_PRG1_PRU1_GPO7, PIN_MODE(6) | \
1002 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1003 },
1005 /* GPIO0 -> GPIO0_93 -> AE23 */
1006 {
1007 PIN_PRG1_PRU1_GPO17, PIN_MODE(6) | \
1008 ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
1009 },
1010 /* GPIO0 -> GPIO0_94 -> AD22 */
1011 {
1012 PIN_PRG1_PRU1_GPO18, PIN_MODE(6) | \
1013 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1014 },
1015 /* GPIO0 -> GPIO0_95 -> AC21 */
1016 {
1017 PIN_PRG1_PRU1_GPO19, PIN_MODE(6) | \
1018 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1019 },
1020 {PINMUX_END}
1021 };
1023 static pinmuxModuleCfg_t gUartPinCfg[] =
1024 {
1025 {0, TRUE, gUart0PinCfg},
1026 {1, TRUE, gUart1PinCfg},
1027 {PINMUX_END}
1028 };
1031 static pinmuxPerCfg_t gUsb0PinCfg[] =
1032 {
1033 /* USB0 -> USB0_DRVVBUS -> AD9 */
1034 {
1035 PIN_USB0_DRVVBUS, PIN_MODE(0) | \
1036 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1037 },
1038 {PINMUX_END}
1039 };
1040 static pinmuxPerCfg_t gUsb1PinCfg[] =
1041 {
1042 /* USB1 -> USB1_DRVVBUS -> AC8 */
1043 {
1044 PIN_USB1_DRVVBUS, PIN_MODE(0) | \
1045 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1046 },
1047 {PINMUX_END}
1048 };
1050 static pinmuxModuleCfg_t gUsbPinCfg[] =
1051 {
1052 {0, TRUE, gUsb0PinCfg},
1053 {1, TRUE, gUsb1PinCfg},
1054 {PINMUX_END}
1055 };
1058 static pinmuxPerCfg_t gVout0PinCfg[] =
1059 {
1060 /* MyVOUT1 -> VOUT1_VSYNC -> T25 */
1061 {
1062 PIN_GPMC0_WPN, PIN_MODE(1) | \
1063 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1064 },
1065 /* MyVOUT1 -> VOUT1_HSYNC -> T24 */
1066 {
1067 PIN_GPMC0_DIR, PIN_MODE(1) | \
1068 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1069 },
1070 /* MyVOUT1 -> VOUT1_PCLK -> R24 */
1071 {
1072 PIN_GPMC0_CSN0, PIN_MODE(1) | \
1073 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1074 },
1075 /* MyVOUT1 -> VOUT1_DE -> T23 */
1076 {
1077 PIN_GPMC0_CSN1, PIN_MODE(1) | \
1078 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1079 },
1080 /* MyVOUT1 -> VOUT1_DATA0 -> M27 */
1081 {
1082 PIN_GPMC0_AD0, PIN_MODE(1) | \
1083 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1084 },
1085 /* MyVOUT1 -> VOUT1_DATA1 -> M23 */
1086 {
1087 PIN_GPMC0_AD1, PIN_MODE(1) | \
1088 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1089 },
1090 /* MyVOUT1 -> VOUT1_DATA2 -> M28 */
1091 {
1092 PIN_GPMC0_AD2, PIN_MODE(1) | \
1093 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1094 },
1095 /* MyVOUT1 -> VOUT1_DATA3 -> M24 */
1096 {
1097 PIN_GPMC0_AD3, PIN_MODE(1) | \
1098 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1099 },
1100 /* MyVOUT1 -> VOUT1_DATA4 -> N24 */
1101 {
1102 PIN_GPMC0_AD4, PIN_MODE(1) | \
1103 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1104 },
1105 /* MyVOUT1 -> VOUT1_DATA5 -> N27 */
1106 {
1107 PIN_GPMC0_AD5, PIN_MODE(1) | \
1108 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1109 },
1110 /* MyVOUT1 -> VOUT1_DATA6 -> N28 */
1111 {
1112 PIN_GPMC0_AD6, PIN_MODE(1) | \
1113 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1114 },
1115 /* MyVOUT1 -> VOUT1_DATA7 -> M25 */
1116 {
1117 PIN_GPMC0_AD7, PIN_MODE(1) | \
1118 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1119 },
1120 /* MyVOUT1 -> VOUT1_DATA8 -> N23 */
1121 {
1122 PIN_GPMC0_AD8, PIN_MODE(1) | \
1123 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1124 },
1125 /* MyVOUT1 -> VOUT1_DATA9 -> M26 */
1126 {
1127 PIN_GPMC0_AD9, PIN_MODE(1) | \
1128 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1129 },
1130 /* MyVOUT1 -> VOUT1_DATA10 -> P28 */
1131 {
1132 PIN_GPMC0_AD10, PIN_MODE(1) | \
1133 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1134 },
1135 /* MyVOUT1 -> VOUT1_DATA11 -> P27 */
1136 {
1137 PIN_GPMC0_AD11, PIN_MODE(1) | \
1138 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1139 },
1140 /* MyVOUT1 -> VOUT1_DATA12 -> N26 */
1141 {
1142 PIN_GPMC0_AD12, PIN_MODE(1) | \
1143 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1144 },
1145 /* MyVOUT1 -> VOUT1_DATA13 -> N25 */
1146 {
1147 PIN_GPMC0_AD13, PIN_MODE(1) | \
1148 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1149 },
1150 /* MyVOUT1 -> VOUT1_DATA14 -> P24 */
1151 {
1152 PIN_GPMC0_AD14, PIN_MODE(1) | \
1153 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1154 },
1155 /* MyVOUT1 -> VOUT1_DATA15 -> R27 */
1156 {
1157 PIN_GPMC0_AD15, PIN_MODE(1) | \
1158 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1159 },
1160 /* MyVOUT1 -> VOUT1_DATA16 -> R28 */
1161 {
1162 PIN_GPMC0_CLK, PIN_MODE(1) | \
1163 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1164 },
1165 /* MyVOUT1 -> VOUT1_DATA17 -> P25 */
1166 {
1167 PIN_GPMC0_ADVN_ALE, PIN_MODE(1) | \
1168 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1169 },
1170 /* MyVOUT1 -> VOUT1_DATA18 -> P26 */
1171 {
1172 PIN_GPMC0_OEN_REN, PIN_MODE(1) | \
1173 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1174 },
1175 /* MyVOUT1 -> VOUT1_DATA19 -> U28 */
1176 {
1177 PIN_GPMC0_WEN, PIN_MODE(1) | \
1178 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1179 },
1180 /* MyVOUT1 -> VOUT1_DATA20 -> T28 */
1181 {
1182 PIN_GPMC0_BE0N_CLE, PIN_MODE(1) | \
1183 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1184 },
1185 /* MyVOUT1 -> VOUT1_DATA21 -> P23 */
1186 {
1187 PIN_GPMC0_BE1N, PIN_MODE(1) | \
1188 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1189 },
1190 /* MyVOUT1 -> VOUT1_DATA22 -> R26 */
1191 {
1192 PIN_GPMC0_WAIT0, PIN_MODE(1) | \
1193 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1194 },
1195 /* MyVOUT1 -> VOUT1_DATA23 -> R23 */
1196 {
1197 PIN_GPMC0_WAIT1, PIN_MODE(1) | \
1198 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1199 },
1200 {PINMUX_END}
1201 };
1203 static pinmuxModuleCfg_t gVoutPinCfg[] =
1204 {
1205 {0, TRUE, gVout0PinCfg},
1206 {PINMUX_END}
1207 };
1210 static pinmuxPerCfg_t gWkup_debugss0PinCfg[] =
1211 {
1212 /* WKUP_DEBUGSS -> TCK -> AA4 */
1213 {
1214 PIN_TCK, PIN_MODE(0) | \
1215 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1216 },
1217 /* WKUP_DEBUGSS -> TRSTn -> AA3 */
1218 {
1219 PIN_TRSTN, PIN_MODE(0) | \
1220 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1221 },
1222 /* WKUP_DEBUGSS -> EMU0 -> AA2 */
1223 {
1224 PIN_EMU0, PIN_MODE(0) | \
1225 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1226 },
1227 /* WKUP_DEBUGSS -> EMU1 -> AA1 */
1228 {
1229 PIN_EMU1, PIN_MODE(0) | \
1230 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1231 },
1232 {PINMUX_END}
1233 };
1235 static pinmuxModuleCfg_t gWkup_debugssPinCfg[] =
1236 {
1237 {0, TRUE, gWkup_debugss0PinCfg},
1238 {PINMUX_END}
1239 };
1242 static pinmuxPerCfg_t gWkup_gpio0PinCfg[] =
1243 {
1244 /* WKUP_GPIO0 -> WKUP_GPIO0_0 -> AF4 */
1245 {
1246 PIN_WKUP_GPIO0_0, PIN_MODE(0) | \
1247 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1248 },
1249 /* WKUP_GPIO0 -> WKUP_GPIO0_1 -> AF3 */
1250 {
1251 PIN_WKUP_GPIO0_1, PIN_MODE(0) | \
1252 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1253 },
1254 /* WKUP_GPIO0 -> WKUP_GPIO0_8 -> AC5 */
1255 {
1256 PIN_WKUP_GPIO0_8, PIN_MODE(0) | \
1257 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1258 },
1259 /* WKUP_GPIO0 -> WKUP_GPIO0_13 -> U1 */
1260 {
1261 PIN_MCU_OSPI0_LBCLKO, PIN_MODE(7) | \
1262 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1263 },
1264 /* WKUP_GPIO0 -> WKUP_GPIO0_24 -> R5 */
1265 {
1266 PIN_MCU_OSPI0_CSN1, PIN_MODE(7) | \
1267 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1268 },
1269 /* WKUP_GPIO0 -> WKUP_GPIO0_25 -> T1 */
1270 {
1271 PIN_MCU_OSPI1_CLK, PIN_MODE(7) | \
1272 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1273 },
1274 /* WKUP_GPIO0 -> WKUP_GPIO0_26 -> R1 */
1275 {
1276 PIN_MCU_OSPI1_LBCLKO, PIN_MODE(7) | \
1277 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1278 },
1279 /* WKUP_GPIO0 -> WKUP_GPIO0_27 -> P2 */
1280 {
1281 PIN_MCU_OSPI1_DQS, PIN_MODE(7) | \
1282 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1283 },
1284 /* WKUP_GPIO0 -> WKUP_GPIO0_28 -> P3 */
1285 {
1286 PIN_MCU_OSPI1_D0, PIN_MODE(7) | \
1287 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1288 },
1289 /* WKUP_GPIO0 -> WKUP_GPIO0_32 -> N2 */
1290 {
1291 PIN_MCU_OSPI1_CSN0, PIN_MODE(7) | \
1292 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1293 },
1294 /* WKUP_GPIO0 -> WKUP_GPIO0_50 -> Y2 */
1295 {
1296 PIN_MCU_SPI0_D1, PIN_MODE(7) | \
1297 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1298 },
1299 {PINMUX_END}
1300 };
1302 static pinmuxModuleCfg_t gWkup_gpioPinCfg[] =
1303 {
1304 {0, TRUE, gWkup_gpio0PinCfg},
1305 {PINMUX_END}
1306 };
1309 static pinmuxPerCfg_t gWkup_i2c0PinCfg[] =
1310 {
1311 /* WKUP_I2C0 -> WKUP_I2C0_SCL -> AC7 */
1312 {
1313 PIN_WKUP_I2C0_SCL, PIN_MODE(0) | \
1314 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1315 },
1316 /* WKUP_I2C0 -> WKUP_I2C0_SDA -> AD6 */
1317 {
1318 PIN_WKUP_I2C0_SDA, PIN_MODE(0) | \
1319 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1320 },
1321 {PINMUX_END}
1322 };
1324 static pinmuxModuleCfg_t gWkup_i2cPinCfg[] =
1325 {
1326 {0, TRUE, gWkup_i2c0PinCfg},
1327 {PINMUX_END}
1328 };
1331 static pinmuxPerCfg_t gWkup_osc00PinCfg[] =
1332 {
1333 {PINMUX_END}
1334 };
1336 static pinmuxModuleCfg_t gWkup_osc0PinCfg[] =
1337 {
1338 {0, TRUE, gWkup_osc00PinCfg},
1339 {PINMUX_END}
1340 };
1342 pinmuxPerCfg_t gWkup_system0PinCfgPG1[] =
1343 {
1344 /* WKUP_SYSTEM -> PMIC_POWER_EN0 -> Y5 */
1345 {
1346 PIN_PMIC_POWER_EN0, PIN_MODE(0) | \
1347 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1348 },
1349 /* WKUP_SYSTEM -> PMIC_POWER_EN1 -> AA5 */
1350 {
1351 PIN_PMIC_POWER_EN1, PIN_MODE(0) | \
1352 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1353 },
1354 /* WKUP_SYSTEM -> MCU_SAFETY_ERRORn -> W3 */
1355 {
1356 PIN_MCU_SAFETY_ERRORN, PIN_MODE(0) | \
1357 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1358 },
1359 /* WKUP_SYSTEM -> MCU_RESETz -> W4 */
1360 {
1361 PIN_MCU_RESETZ, PIN_MODE(0) | \
1362 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1363 },
1364 /* WKUP_SYSTEM -> MCU_RESETSTATz -> V3 */
1365 {
1366 PIN_MCU_RESETSTATZ, PIN_MODE(0) | \
1367 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1368 },
1369 /* WKUP_SYSTEM -> MCU_PORz_OUT -> V2 */
1370 {
1371 PIN_MCU_PORZ_OUT, PIN_MODE(0) | \
1372 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1373 },
1374 {PINMUX_END}
1375 };
1377 static pinmuxPerCfg_t gWkup_system0PinCfg[] =
1378 {
1379 /* WKUP_SYSTEM -> PMIC_POWER_EN0 -> Y5 */
1380 {
1381 PIN_PMIC_POWER_EN0, PIN_MODE(0) | \
1382 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1383 },
1384 /* WKUP_SYSTEM -> PMIC_POWER_EN1 -> AA5 */
1385 {
1386 PIN_PMIC_POWER_EN1, PIN_MODE(0) | \
1387 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1388 },
1389 /* WKUP_SYSTEM -> MCU_SAFETY_ERRORn -> W3 */
1390 {
1391 PIN_MCU_SAFETY_ERRORN, PIN_MODE(0) | \
1392 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1393 },
1394 /* WKUP_SYSTEM -> MCU_RESETz -> W4 */
1395 {
1396 PIN_MCU_RESETZ, PIN_MODE(0) | \
1397 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1398 },
1399 /* WKUP_SYSTEM -> MCU_RESETSTATz -> V3 */
1400 {
1401 PIN_MCU_RESETSTATZ, PIN_MODE(0) | \
1402 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1403 },
1404 /* WKUP_SYSTEM -> MCU_PORz_OUT -> V2 */
1405 {
1406 PIN_MCU_PORZ_OUT, PIN_MODE(0) | \
1407 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1408 },
1409 {PINMUX_END}
1410 };
1412 pinmuxModuleCfg_t gWkup_systemPinCfg[] =
1413 {
1414 {0, TRUE, gWkup_system0PinCfg},
1415 {PINMUX_END}
1416 };
1419 static pinmuxPerCfg_t gWkup_uart0PinCfg[] =
1420 {
1421 /* WKUP_UART0 -> WKUP_UART0_RXD -> AB1 */
1422 {
1423 PIN_WKUP_UART0_RXD, PIN_MODE(0) | \
1424 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1425 },
1426 /* WKUP_UART0 -> WKUP_UART0_TXD -> AB5 */
1427 {
1428 PIN_WKUP_UART0_TXD, PIN_MODE(0) | \
1429 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1430 },
1431 /* WKUP_UART0 -> WKUP_UART0_CTSn -> AC2 */
1432 {
1433 PIN_WKUP_GPIO0_6, PIN_MODE(1) | \
1434 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1435 },
1436 /* WKUP_UART0 -> WKUP_UART0_RTSn -> AC1 */
1437 {
1438 PIN_WKUP_GPIO0_7, PIN_MODE(1) | \
1439 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
1440 },
1441 {PINMUX_END}
1442 };
1444 static pinmuxModuleCfg_t gWkup_uartPinCfg[] =
1445 {
1446 {0, TRUE, gWkup_uart0PinCfg},
1447 {PINMUX_END}
1448 };
1451 static pinmuxPerCfg_t gPru0PinCfg[] =
1452 {
1453 /* PRU0 -> PRG1_PRU0GPO0 -> AE22 */
1454 {
1455 PIN_PRG1_PRU0_GPO0, PIN_MODE(0) | \
1456 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1457 },
1458 /* PRU0 -> PRG1_PRU0GPO1 -> AG24 */
1459 {
1460 PIN_PRG1_PRU0_GPO1, PIN_MODE(0) | \
1461 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1462 },
1463 /* PRU0 -> PRG1_PRU0GPO2 -> AF23 */
1464 {
1465 PIN_PRG1_PRU0_GPO2, PIN_MODE(0) | \
1466 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1467 },
1468 /* PRU0 -> PRG1_PRU0GPO3 -> AD21 */
1469 {
1470 PIN_PRG1_PRU0_GPO3, PIN_MODE(0) | \
1471 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1472 },
1473 /* PRU0 -> PRG1_PRU0GPO4 -> AG23 */
1474 {
1475 PIN_PRG1_PRU0_GPO4, PIN_MODE(0) | \
1476 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1477 },
1478 /* PRU0 -> PRG1_PRU0GPO5 -> AF27 */
1479 {
1480 PIN_PRG1_PRU0_GPO5, PIN_MODE(0) | \
1481 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1482 },
1483 /* PRU0 -> PRG1_PRU0GPO6 -> AF22 */
1484 {
1485 PIN_PRG1_PRU0_GPO6, PIN_MODE(0) | \
1486 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1487 },
1488 /* PRU0 -> PRG1_PRU0GPO7 -> AG27 */
1489 {
1490 PIN_PRG1_PRU0_GPO7, PIN_MODE(0) | \
1491 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1492 },
1493 /* PRU0 -> PRG1_PRU0GPO9 -> AF26 */
1494 {
1495 PIN_PRG1_PRU0_GPO9, PIN_MODE(0) | \
1496 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1497 },
1498 /* PRU0 -> PRG1_PRU0GPO10 -> AH25 */
1499 {
1500 PIN_PRG1_PRU0_GPO10, PIN_MODE(0) | \
1501 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1502 },
1503 /* PRU0 -> PRG1_PRU0GPO11 -> AF21 */
1504 {
1505 PIN_PRG1_PRU0_GPO11, PIN_MODE(0) | \
1506 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1507 },
1508 /* PRU0 -> PRG1_PRU0GPO12 -> AH20 */
1509 {
1510 PIN_PRG1_PRU0_GPO12, PIN_MODE(0) | \
1511 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1512 },
1513 /* PRU0 -> PRG1_PRU0GPO13 -> AH21 */
1514 {
1515 PIN_PRG1_PRU0_GPO13, PIN_MODE(0) | \
1516 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1517 },
1518 /* PRU0 -> PRG1_PRU0GPO14 -> AG20 */
1519 {
1520 PIN_PRG1_PRU0_GPO14, PIN_MODE(0) | \
1521 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1522 },
1523 {PINMUX_END}
1524 };
1526 static pinmuxPerCfg_t gPru1PinCfg[] =
1527 {
1528 /* PRU1 -> PRG1_PRU1GPO0 -> AH24 */
1529 {
1530 PIN_PRG1_PRU1_GPO0, PIN_MODE(0) | \
1531 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1532 },
1533 /* PRU1 -> PRG1_PRU1GPO1 -> AH23 */
1534 {
1535 PIN_PRG1_PRU1_GPO1, PIN_MODE(0) | \
1536 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1537 },
1538 /* PRU1 -> PRG1_PRU1GPO2 -> AG21 */
1539 {
1540 PIN_PRG1_PRU1_GPO2, PIN_MODE(0) | \
1541 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1542 },
1543 /* PRU1 -> PRG1_PRU1GPO3 -> AH22 */
1544 {
1545 PIN_PRG1_PRU1_GPO3, PIN_MODE(0) | \
1546 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1547 },
1548 /* PRU1 -> PRG1_PRU1GPO4 -> AE21 */
1549 {
1550 PIN_PRG1_PRU1_GPO4, PIN_MODE(0) | \
1551 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1552 },
1553 /* PRU1 -> PRG1_PRU1GPO5 -> AC22 */
1554 {
1555 PIN_PRG1_PRU1_GPO5, PIN_MODE(0) | \
1556 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1557 },
1558 /* PRU1 -> PRG1_PRU1GPO6 -> AG22 */
1559 {
1560 PIN_PRG1_PRU1_GPO6, PIN_MODE(0) | \
1561 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1562 },
1563 /* PRU1 -> PRG1_PRU1GPO9 -> AF25 */
1564 {
1565 PIN_PRG1_PRU1_GPO9, PIN_MODE(0) | \
1566 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1567 },
1568 /* PRU1 -> PRG1_PRU1GPO10 -> AF24 */
1569 {
1570 PIN_PRG1_PRU1_GPO10, PIN_MODE(0) | \
1571 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1572 },
1573 /* PRU1 -> PRG1_PRU1GPO11 -> AC20 */
1574 {
1575 PIN_PRG1_PRU1_GPO11, PIN_MODE(0) | \
1576 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1577 },
1578 /* PRU1 -> PRG1_PRU1GPO12 -> AE20 */
1579 {
1580 PIN_PRG1_PRU1_GPO12, PIN_MODE(0) | \
1581 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1582 },
1583 /* PRU1 -> PRG1_PRU1GPO13 -> AF19 */
1584 {
1585 PIN_PRG1_PRU1_GPO13, PIN_MODE(0) | \
1586 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1587 },
1588 /* PRU1 -> PRG1_PRU1GPO14 -> AH19 */
1589 {
1590 PIN_PRG1_PRU1_GPO14, PIN_MODE(0) | \
1591 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1592 },
1593 /* PRU0 -> PRG0_PRU1GPO0 -> AB28 */
1594 {
1595 PIN_PRG0_PRU1_GPO0, PIN_MODE(0) | \
1596 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1597 },
1598 /* PRU0 -> PRG0_PRU1GPO1 -> AC28 */
1599 {
1600 PIN_PRG0_PRU1_GPO1, PIN_MODE(0) | \
1601 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1602 },
1603 /* PRU0 -> PRG0_PRU1GPO2 -> AC27 */
1604 {
1605 PIN_PRG0_PRU1_GPO2, PIN_MODE(0) | \
1606 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1607 },
1608 /* PRU0 -> PRG0_PRU1GPO3 -> AB26 */
1609 {
1610 PIN_PRG0_PRU1_GPO3, PIN_MODE(0) | \
1611 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1612 },
1613 /* PRU0 -> PRG0_PRU1GPO4 -> AA25 */
1614 {
1615 PIN_PRG0_PRU1_GPO4, PIN_MODE(0) | \
1616 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1617 },
1618 /* PRU0 -> PRG0_PRU1GPO5 -> U23 */
1619 {
1620 PIN_PRG0_PRU1_GPO5, PIN_MODE(0) | \
1621 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1622 },
1623 /* PRU0 -> PRG0_PRU1GPO6 -> AB27 */
1624 {
1625 PIN_PRG0_PRU1_GPO6, PIN_MODE(0) | \
1626 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1627 },
1628 /* PRU0 -> PRG0_PRU1GPO7 -> W28 */
1629 {
1630 PIN_PRG0_PRU1_GPO7, PIN_MODE(0) | \
1631 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1632 },
1633 /* PRU0 -> PRG0_PRU1GPO8 -> W27 */
1634 {
1635 PIN_PRG0_PRU1_GPO8, PIN_MODE(0) | \
1636 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1637 },
1638 /* PRU0 -> PRG0_PRU1GPO9 -> Y28 */
1639 {
1640 PIN_PRG0_PRU1_GPO9, PIN_MODE(0) | \
1641 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1642 },
1643 /* PRU0 -> PRG0_PRU1GPO10 -> AA28 */
1644 {
1645 PIN_PRG0_PRU1_GPO10, PIN_MODE(0) | \
1646 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1647 },
1648 /* PRU0 -> PRG0_PRU1GPO11 -> AB24 */
1649 {
1650 PIN_PRG0_PRU1_GPO11, PIN_MODE(0) | \
1651 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1652 },
1653 /* PRU0 -> PRG0_PRU1GPO12 -> AC25 */
1654 {
1655 PIN_PRG0_PRU1_GPO12, PIN_MODE(0) | \
1656 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1657 },
1658 /* PRU0 -> PRG0_PRU1GPO13 -> AD25 */
1659 {
1660 PIN_PRG0_PRU1_GPO13, PIN_MODE(0) | \
1661 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1662 },
1663 /* PRU0 -> PRG0_PRU1GPO14 -> AD24 */
1664 {
1665 PIN_PRG0_PRU1_GPO14, PIN_MODE(0) | \
1666 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1667 },
1668 /* PRU0 -> PRG0_PRU1GPO15 -> AE27 */
1669 {
1670 PIN_PRG0_PRU1_GPO15, PIN_MODE(0) | \
1671 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1672 },
1674 {PINMUX_END}
1675 };
1677 static pinmuxModuleCfg_t gPruPinCfg[] =
1678 {
1679 {0, TRUE, gPru0PinCfg},
1680 {1, TRUE, gPru1PinCfg},
1681 {PINMUX_END}
1682 };
1685 static pinmuxPerCfg_t gMcasp0PinCfg[] =
1686 {
1687 /* MCASP0 -> PRG0_PRU0GPO0 -> V24 */
1688 {
1689 PIN_PRG0_PRU0_GPO0, PIN_MODE(5) | \
1690 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1691 },
1692 /* MCASP0 -> PRG0_PRU0GPO1 -> W25 */
1693 {
1694 PIN_PRG0_PRU0_GPO1, PIN_MODE(5) | \
1695 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1696 },
1697 /* MCASP0 -> PRG0_PRU0GPO4 -> Y24 */
1698 {
1699 PIN_PRG0_PRU0_GPO4, PIN_MODE(5) | \
1700 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1701 },
1702 /* MCASP0 -> PRG0_PRU0GPO5 -> V28 */
1703 {
1704 PIN_PRG0_PRU0_GPO5, PIN_MODE(5) | \
1705 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1706 },
1707 /* MCASP0 -> GPIO0_71 -> AD19 */
1708 {
1709 PIN_PRG0_PRU0_GPO15, PIN_MODE(7) | \
1710 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
1711 },
1712 {PINMUX_END}
1713 };
1715 static pinmuxModuleCfg_t gMcaspPinCfg[] =
1716 {
1717 {0, TRUE, gMcasp0PinCfg},
1718 {PINMUX_END}
1719 };
1722 pinmuxBoardCfg_t gAM65xxMainPinmuxData[] =
1723 {
1724 {0, gCalPinCfg},
1725 {1, gDdrPinCfg},
1726 {2, gDebugssPinCfg},
1727 {3, gEcapPinCfg},
1728 {4, gGpioPinCfg},
1729 {5, gI2cPinCfg},
1730 {6, gMmcPinCfg},
1731 {7, gOldiPinCfg},
1732 {8, gOsc0PinCfg},
1733 {9, gPru_icssg2_mdioPinCfg},
1734 {10, gPru_icssg2_rgmiiPinCfg},
1735 {11, gSerdesPinCfg},
1736 {12, gSpiPinCfg},
1737 {13, gSystemPinCfg},
1738 {14, gTimerPinCfg},
1739 {15, gUartPinCfg},
1740 {16, gUsbPinCfg},
1741 {17, gVoutPinCfg},
1742 {18, gMcaspPinCfg},
1743 {19, gPruPinCfg},
1744 {PINMUX_END}
1745 };
1747 pinmuxBoardCfg_t gAM65xxWkupPinmuxData[] =
1748 {
1749 {0, gMcu_adcPinCfg},
1750 {1, gMcu_cpswPinCfg},
1751 {2, gMcu_fss0_ospiPinCfg},
1752 {3, gMcu_i2cPinCfg},
1753 {4, gMcu_mdioPinCfg},
1754 {5, gMcu_spiPinCfg},
1755 {6, gMcu_uartPinCfg},
1756 {7, gWkup_debugssPinCfg},
1757 {8, gWkup_gpioPinCfg},
1758 {9, gWkup_i2cPinCfg},
1759 {10, gWkup_osc0PinCfg},
1760 {11, gWkup_systemPinCfg},
1761 {12, gWkup_uartPinCfg},
1762 {PINMUX_END}
1763 };