3853009e4a672f026c4f4a859d115808dd4b432b
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34 /** \file am65xx_evm_clock.c
35 *
36 * \brief This file contains initialization of wakeup and main PSC
37 * configuration structures and function definitions to get the number
38 * of wakeup and main PSC config exists.
39 */
41 /**
42 * \brief wkup PSC configuration parameters
43 *
44 * This structure provides the device-level view with module association to
45 * the clock, power, and voltage domains.
46 *
47 * The PSC provides the user with an interface to control several important
48 * power and clock operations. The device has two PSC - WKUP_PSC0 and PSC0
49 * in WKUPSS and MAIN SoC, respectively.
50 *
51 * PSC: The Power Sleep Controller is the device has several power domains
52 * that can be turned ON for operation or OFF to minimize power dissipation,
53 * which includes a Global Power Sleep Controller(GPSC) and Local Power
54 * Sleep Controller(LPSC).
55 *
56 * GPSC: Global Power Sleep Controller, is used to control the power gating
57 * of various power domains.
58 *
59 * LPSC: Local Power Sleep Controller, manages the clock gating for to each
60 * logic block. For modules with a dedicated clock or multiple clocks, the
61 * LPSC communicates with the PLL controller to enable and disable that
62 * module's clock(s) at the source. For modules that share a clock with
63 * other modules, the LPSC controls the clock gating logic for each module.
64 */
66 #include "board_clock.h"
67 #include <ti/drv/sciclient/sciclient.h>
69 #ifdef DISABLE_SCI_CLK_CONFIG
70 const pscConfig wkupPscConfigs[] =
71 {
72 {CSL_PSC_PD_WKUP, CSL_PSC_LPSC_WKUP_COMMON},
73 /* {CSL_PSC_PD_WKUP, CSL_PSC_LPSC_DMSC}, */
74 {CSL_PSC_PD_WKUP, CSL_PSC_LPSC_WKUP2MCU},
75 {CSL_PSC_PD_WKUP, CSL_PSC_LPSC_WKUP2MAIN_INFRA},
76 {CSL_PSC_PD_WKUP, CSL_PSC_LPSC_DEBUG2DMSC},
77 {CSL_PSC_PD_WKUP, CSL_PSC_LPSC_WKUP_GPIO},
78 {CSL_PSC_PD_MCU, CSL_PSC_LPSC_MCU2MAIN_INFRA},
79 {CSL_PSC_PD_MCU, CSL_PSC_LPSC_MCU2MAIN},
80 {CSL_PSC_PD_MCU, CSL_PSC_LPSC_MCU2WKUP},
81 {CSL_PSC_PD_MCU, CSL_PSC_LPSC_MAIN2MCU},
82 {CSL_PSC_PD_MCU, CSL_PSC_LPSC_MCU_COMMON},
83 {CSL_PSC_PD_MCU, CSL_PSC_LPSC_MCU_TEST},
84 {CSL_PSC_PD_MCU, CSL_PSC_LPSC_MCU_MCAN_0},
85 {CSL_PSC_PD_MCU, CSL_PSC_LPSC_MCU_MCAN_1},
86 {CSL_PSC_PD_MCU, CSL_PSC_LPSC_MCU_OSPI_0},
87 {CSL_PSC_PD_MCU, CSL_PSC_LPSC_MCU_OSPI_1},
88 {CSL_PSC_PD_MCU, CSL_PSC_LPSC_MCU_HYPERBUS},
89 {CSL_PSC_PD_MCU, CSL_PSC_LPSC_MCU_DEBUG}
90 /* {CSL_PSC_PD_MCU_PULSAR, CSL_PSC_LPSC_MCU_R5_0}, */
91 /* {CSL_PSC_PD_MCU_PULSAR, CSL_PSC_LPSC_MCU_R5_1} */
92 };
94 /**
95 * \brief main PSC configuration parameters
96 *
97 * This structure provides the device-level view with module association to
98 * the clock, power, and voltage domains.
99 *
100 * The PSC provides the user with an interface to control several important
101 * power and clock operations. The device has two PSC - WKUP_PSC0 and PSC0
102 * in WKUPSS and MAIN SoC, respectively.
103 *
104 * PSC: The Power Sleep Controller is the device has several power domains
105 * that can be turned ON for operation or OFF to minimize power dissipation,
106 * which includes a Global Power Sleep Controller(GPSC) and Local Power
107 * Sleep Controller(LPSC).
108 *
109 * GPSC: Global Power Sleep Controller, is used to control the power gating
110 * of various power domains.
111 *
112 * LPSC: Local Power Sleep Controller, manages the clock gating for to each
113 * logic block. For modules with a dedicated clock or multiple clocks, the
114 * LPSC communicates with the PLL controller to enable and disable that
115 * module's clock(s) at the source. For modules that share a clock with
116 * other modules, the LPSC controls the clock gating logic for each module.
117 */
118 const pscConfig mainPscConfigs[] =
119 {
120 {CSL_PSC_GP_CORE_CTL, CSL_PSC_LPSC_MAIN_INFRA},
121 {CSL_PSC_GP_CORE_CTL, CSL_PSC_LPSC_MAIN_TEST},
122 /* {CSL_PSC_GP_CORE_CTL, CSL_PSC_LPSC_MAIN_PBIST}, */
123 {CSL_PSC_PD_CC_TOP, CSL_PSC_LPSC_CC_TOP},
124 /* {CSL_PSC_PD_CC_TOP, CSL_PSC_LPSC_CC_TOP_PBIST}, */
125 {CSL_PSC_PD_A53_CLUSTER_0, CSL_PSC_LPSC_A53_CLUSTER_0},
126 /* {CSL_PSC_PD_A53_0, CSL_PSC_LPSC_A53_0}, */
127 /* {CSL_PSC_PD_A53_1, CSL_PSC_LPSC_A53_1}, */
128 {CSL_PSC_PD_A53_CLUSTER_1, CSL_PSC_LPSC_A53_CLUSTER_1},
129 /* {CSL_PSC_PD_A53_2, CSL_PSC_LPSC_A53_2}, */
130 /* {CSL_PSC_PD_A53_3, CSL_PSC_LPSC_A53_3}, */
131 /* {CSL_PSC_PD_A53_CLUSTER_0, CSL_PSC_LPSC_A53_CLUSTER_0_PBIST}, */
132 /* {CSL_PSC_PD_A53_CLUSTER_1, CSL_PSC_LPSC_A53_CLUSTER_1_PBIST}, */
133 {CSL_PSC_PD_DEBUG, CSL_PSC_LPSC_MAIN_DEBUG},
134 {CSL_PSC_PD_PER, CSL_PSC_LPSC_DSS},
135 {CSL_PSC_PD_PER, CSL_PSC_LPSC_MMC},
136 {CSL_PSC_PD_PER, CSL_PSC_LPSC_CAL},
137 {CSL_PSC_PD_PER, CSL_PSC_LPSC_PCIE_0},
138 {CSL_PSC_PD_PER, CSL_PSC_LPSC_PCIE_1},
139 {CSL_PSC_PD_PER, CSL_PSC_LPSC_USB_0},
140 {CSL_PSC_PD_PER, CSL_PSC_LPSC_USB_1},
141 {CSL_PSC_PD_PER, CSL_PSC_LPSC_SAUL},
142 {CSL_PSC_PD_PER, CSL_PSC_LPSC_PER_COMMON},
143 {CSL_PSC_PD_PER, CSL_PSC_LPSC_NB},
144 {CSL_PSC_PD_SERDES, CSL_PSC_LPSC_SERDES_0},
145 {CSL_PSC_PD_SERDES, CSL_PSC_LPSC_SERDES_1},
146 {CSL_PSC_PD_ICSSG, CSL_PSC_LPSC_ICSSG_0},
147 {CSL_PSC_PD_ICSSG, CSL_PSC_LPSC_ICSSG_1},
148 {CSL_PSC_PD_ICSSG, CSL_PSC_LPSC_ICSSG_2},
149 {CSL_PSC_PD_GPU, CSL_PSC_LPSC_GPU},
150 /* {CSL_PSC_PD_GPU, CSL_PSC_LPSC_GPU_PBIST}, */
151 {CSL_PSC_PD_EMIF, CSL_PSC_LPSC_EMIF_DATA},
152 {CSL_PSC_PD_EMIF, CSL_PSC_LPSC_EMIF_CFG}
153 };
155 /**
156 * \brief This function is used to get the number of \
157 * wkup PSC configs exists.
158 *
159 * \return
160 * \n uint32_t - Number of wkup PSC configs.
161 */
162 uint32_t Board_getNumWkupPscCconfigs(void)
163 {
164 return (sizeof(wkupPscConfigs) / sizeof(pscConfig));
165 }
167 /**
168 * \brief This function is used to get the number of \
169 * main PSC configs exists.
170 *
171 * \return
172 * \n uint32_t - Number of main PSC configs.
173 */
174 uint32_t Board_getNumMainPscCconfigs(void)
175 {
176 return (sizeof(mainPscConfigs) / sizeof(pscConfig));
177 }
179 #else /* #ifdef DISABLE_SCI_CLK_CONFIG */
180 uint32_t gBoardClkModuleID[] = {
181 TISCI_DEV_MCU_ADC0,
182 TISCI_DEV_MCU_ADC1,
183 TISCI_DEV_CAL0,
184 TISCI_DEV_CMPEVENT_INTRTR0,
185 TISCI_DEV_MCU_CPSW0,
186 TISCI_DEV_CPT2_AGGR0,
187 TISCI_DEV_MCU_CPT2_AGGR0,
188 TISCI_DEV_STM0,
189 TISCI_DEV_DCC0,
190 TISCI_DEV_DCC1,
191 TISCI_DEV_DCC2,
192 TISCI_DEV_DCC3,
193 TISCI_DEV_DCC4,
194 TISCI_DEV_DCC5,
195 TISCI_DEV_DCC6,
196 TISCI_DEV_DCC7,
197 TISCI_DEV_MCU_DCC0,
198 TISCI_DEV_MCU_DCC1,
199 TISCI_DEV_MCU_DCC2,
200 TISCI_DEV_DDRSS0,
201 TISCI_DEV_DEBUGSS_WRAP0,
202 TISCI_DEV_WKUP_DMSC0,
203 TISCI_DEV_TIMER0,
204 TISCI_DEV_TIMER1,
205 TISCI_DEV_TIMER10,
206 TISCI_DEV_TIMER11,
207 TISCI_DEV_TIMER2,
208 TISCI_DEV_TIMER3,
209 TISCI_DEV_TIMER4,
210 TISCI_DEV_TIMER5,
211 TISCI_DEV_TIMER6,
212 TISCI_DEV_TIMER7,
213 TISCI_DEV_TIMER8,
214 TISCI_DEV_TIMER9,
215 TISCI_DEV_MCU_TIMER0,
216 TISCI_DEV_MCU_TIMER1,
217 TISCI_DEV_MCU_TIMER2,
218 TISCI_DEV_MCU_TIMER3,
219 TISCI_DEV_ECAP0,
220 TISCI_DEV_EHRPWM0,
221 TISCI_DEV_EHRPWM1,
222 TISCI_DEV_EHRPWM2,
223 TISCI_DEV_EHRPWM3,
224 TISCI_DEV_EHRPWM4,
225 TISCI_DEV_EHRPWM5,
226 TISCI_DEV_ELM0,
227 TISCI_DEV_MMCSD0,
228 TISCI_DEV_MMCSD1,
229 TISCI_DEV_EQEP0,
230 TISCI_DEV_EQEP1,
231 TISCI_DEV_EQEP2,
232 TISCI_DEV_ESM0,
233 TISCI_DEV_MCU_ESM0,
234 TISCI_DEV_WKUP_ESM0,
235 TISCI_DEV_MCU_FSS0_FSAS_0,
236 TISCI_DEV_MCU_FSS0_HYPERBUS0,
237 TISCI_DEV_MCU_FSS0_OSPI_0,
238 TISCI_DEV_MCU_FSS0_OSPI_1,
239 TISCI_DEV_GIC0,
240 TISCI_DEV_GPIO0,
241 TISCI_DEV_GPIO1,
242 TISCI_DEV_WKUP_GPIO0,
243 TISCI_DEV_GPMC0,
244 TISCI_DEV_GTC0,
245 TISCI_DEV_PRU_ICSSG0,
246 TISCI_DEV_PRU_ICSSG1,
247 TISCI_DEV_PRU_ICSSG2,
248 TISCI_DEV_GPU0,
249 TISCI_DEV_CCDEBUGSS0,
250 TISCI_DEV_DSS0,
251 TISCI_DEV_DEBUGSS0,
252 TISCI_DEV_EFUSE0,
253 TISCI_DEV_PSC0,
254 TISCI_DEV_MCU_DEBUGSS0,
255 TISCI_DEV_MCU_EFUSE0,
256 TISCI_DEV_PBIST0,
257 TISCI_DEV_PBIST1,
258 TISCI_DEV_MCU_PBIST0,
259 TISCI_DEV_PLLCTRL0,
260 TISCI_DEV_WKUP_PLLCTRL0,
261 TISCI_DEV_MCU_ROM0,
262 TISCI_DEV_WKUP_PSC0,
263 TISCI_DEV_WKUP_VTM0,
264 TISCI_DEV_DEBUGSUSPENDRTR0,
265 TISCI_DEV_CBASS0,
266 TISCI_DEV_CBASS_DEBUG0,
267 TISCI_DEV_CBASS_FW0,
268 TISCI_DEV_CBASS_INFRA0,
269 TISCI_DEV_ECC_AGGR0,
270 TISCI_DEV_ECC_AGGR1,
271 TISCI_DEV_ECC_AGGR2,
272 TISCI_DEV_MCU_CBASS0,
273 TISCI_DEV_MCU_CBASS_DEBUG0,
274 TISCI_DEV_MCU_CBASS_FW0,
275 TISCI_DEV_MCU_ECC_AGGR0,
276 TISCI_DEV_MCU_ECC_AGGR1,
277 TISCI_DEV_WKUP_CBASS0,
278 TISCI_DEV_WKUP_ECC_AGGR0,
279 TISCI_DEV_WKUP_CBASS_FW0,
280 TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
281 TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
282 TISCI_DEV_CTRL_MMR0,
283 TISCI_DEV_GPIOMUX_INTRTR0,
284 TISCI_DEV_PLL_MMR0,
285 TISCI_DEV_MCU_MCAN0,
286 TISCI_DEV_MCU_MCAN1,
287 TISCI_DEV_MCASP0,
288 TISCI_DEV_MCASP1,
289 TISCI_DEV_MCASP2,
290 TISCI_DEV_MCU_CTRL_MMR0,
291 TISCI_DEV_MCU_PLL_MMR0,
292 TISCI_DEV_MCU_SEC_MMR0,
293 TISCI_DEV_I2C0,
294 TISCI_DEV_I2C1,
295 TISCI_DEV_I2C2,
296 TISCI_DEV_I2C3,
297 TISCI_DEV_MCU_I2C0,
298 TISCI_DEV_WKUP_I2C0,
299 TISCI_DEV_MCU_MSRAM0,
300 TISCI_DEV_DFTSS0,
301 TISCI_DEV_NAVSS0,
302 TISCI_DEV_MCU_NAVSS0,
303 TISCI_DEV_PCIE0,
304 TISCI_DEV_PCIE1,
305 TISCI_DEV_PDMA_DEBUG0,
306 TISCI_DEV_PDMA0,
307 TISCI_DEV_PDMA1,
308 TISCI_DEV_MCU_PDMA0,
309 TISCI_DEV_MCU_PDMA1,
310 TISCI_DEV_MCU_PSRAM0,
311 TISCI_DEV_PSRAMECC0,
312 TISCI_DEV_SA2_UL0,
313 TISCI_DEV_MCSPI0,
314 TISCI_DEV_MCSPI1,
315 TISCI_DEV_MCSPI2,
316 TISCI_DEV_MCSPI3,
317 TISCI_DEV_MCSPI4,
318 TISCI_DEV_MCU_MCSPI0,
319 TISCI_DEV_MCU_MCSPI1,
320 TISCI_DEV_MCU_MCSPI2,
321 TISCI_DEV_TIMESYNC_INTRTR0,
322 TISCI_DEV_UART1,
323 TISCI_DEV_UART2,
324 TISCI_DEV_USB3SS0,
325 TISCI_DEV_USB3SS1,
326 TISCI_DEV_SERDES0,
327 TISCI_DEV_SERDES1,
328 TISCI_DEV_NAVSS0_CPTS0,
329 TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER0,
330 TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER1,
331 TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER2,
332 TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER3,
333 TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER4,
334 TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER5,
335 TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER6,
336 TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER7,
337 TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER8,
338 TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER9,
339 TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER10,
340 TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER11,
341 TISCI_DEV_NAVSS0_MCRC0,
342 TISCI_DEV_NAVSS0_PVU0,
343 TISCI_DEV_NAVSS0_PVU1,
344 TISCI_DEV_NAVSS0_UDMASS_INTA0,
345 TISCI_DEV_NAVSS0_MODSS_INTA0,
346 TISCI_DEV_NAVSS0_MODSS_INTA1,
347 TISCI_DEV_NAVSS0_INTR_ROUTER_0,
348 TISCI_DEV_NAVSS0_TIMER_MGR0,
349 TISCI_DEV_NAVSS0_TIMER_MGR1,
350 TISCI_DEV_NAVSS0_PROXY0,
351 TISCI_DEV_NAVSS0_SEC_PROXY0,
352 TISCI_DEV_NAVSS0_RINGACC0,
353 TISCI_DEV_NAVSS0_UDMAP0,
354 TISCI_DEV_MCU_NAVSS0_INTR_AGGR_0,
355 TISCI_DEV_MCU_NAVSS0_INTR_ROUTER_0,
356 TISCI_DEV_MCU_NAVSS0_PROXY0,
357 TISCI_DEV_MCU_NAVSS0_SEC_PROXY0,
358 TISCI_DEV_MCU_NAVSS0_MCRC0,
359 TISCI_DEV_MCU_NAVSS0_UDMAP0,
360 TISCI_DEV_MCU_NAVSS0_RINGACC0,
361 TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4,
362 TISCI_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3,
363 TISCI_DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0,
364 TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3,
365 TISCI_DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1,
366 TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5,
367 TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6,
368 TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0,
369 TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2,
370 TISCI_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2,
371 TISCI_DEV_OLDI_TX_CORE_MAIN_0,
372 TISCI_DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0,
373 TISCI_DEV_ICEMELTER_WKUP_0,
374 TISCI_DEV_K3_LED_MAIN_0,
375 TISCI_DEV_VDC_DATA_VBUSM_32B_REF_WKUP2MCU,
376 TISCI_DEV_VDC_DATA_VBUSM_32B_REF_MCU2WKUP,
377 TISCI_DEV_VDC_DATA_VBUSM_64B_REF_MAIN2MCU,
378 TISCI_DEV_VDC_DATA_VBUSM_64B_REF_MCU2MAIN,
379 TISCI_DEV_VDC_DMSC_DBG_VBUSP_32B_REF_DBG2DMSC,
380 TISCI_DEV_VDC_INFRA_VBUSP_32B_REF_WKUP2MAIN_INFRA,
381 TISCI_DEV_VDC_INFRA_VBUSP_32B_REF_MCU2MAIN_INFRA,
382 TISCI_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWWKUP2MCU,
383 TISCI_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWMCU2MAIN,
384 TISCI_DEV_VDC_MCU_DBG_VBUSP_32B_REF_DBGMAIN2MCU,
385 TISCI_DEV_VDC_NAV_PSIL_128B_REF_MAIN2MCU,
386 TISCI_DEV_GS80PRG_SOC_WRAP_WKUP_0,
387 TISCI_DEV_GS80PRG_MCU_WRAP_WKUP_0,
388 TISCI_DEV_MX_WAKEUP_RESET_SYNC_WKUP_0,
389 TISCI_DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0,
390 TISCI_DEV_MX_EFUSE_MCU_CHAIN_MCU_0,
391 TISCI_DEV_DUMMY_IP_LPSC_WKUP2MCU_VD,
392 TISCI_DEV_DUMMY_IP_LPSC_WKUP2MAIN_INFRA_VD,
393 TISCI_DEV_DUMMY_IP_LPSC_DEBUG2DMSC_VD,
394 TISCI_DEV_DUMMY_IP_LPSC_DMSC_VD,
395 TISCI_DEV_DUMMY_IP_LPSC_MCU2MAIN_INFRA_VD,
396 TISCI_DEV_DUMMY_IP_LPSC_MCU2MAIN_VD,
397 TISCI_DEV_DUMMY_IP_LPSC_MCU2WKUP_VD,
398 TISCI_DEV_DUMMY_IP_LPSC_MAIN2MCU_VD,
399 TISCI_DEV_DUMMY_IP_LPSC_EMIF_DATA_VD,
400 TISCI_DEV_MCU_ARMSS0_CPU1
401 };
403 /**
404 * \brief Returns number of module clocks
405 *
406 * \return
407 * \n uint32_t - number of module clocks
408 */
409 uint32_t Board_getNumClkConfigs(void)
410 {
411 return (sizeof (gBoardClkModuleID)/sizeof(uint32_t));
412 }
414 #endif /* #ifdef DISABLE_SCI_CLK_CONFIG */