1 /******************************************************************************\r
2 * Copyright (c) 2010-2015 Texas Instruments Incorporated - http://www.ti.com\r
3 *\r
4 * Redistribution and use in source and binary forms, with or without\r
5 * modification, are permitted provided that the following conditions\r
6 * are met:\r
7 *\r
8 * Redistributions of source code must retain the above copyright\r
9 * notice, this list of conditions and the following disclaimer.\r
10 *\r
11 * Redistributions in binary form must reproduce the above copyright\r
12 * notice, this list of conditions and the following disclaimer in the\r
13 * documentation and/or other materials provided with the\r
14 * distribution.\r
15 *\r
16 * Neither the name of Texas Instruments Incorporated nor the names of\r
17 * its contributors may be used to endorse or promote products derived\r
18 * from this software without specific prior written permission.\r
19 *\r
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
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29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
31 *\r
32 *****************************************************************************/\r
33 \r
34 #include "board_cfg.h"\r
35 #include "board_internal.h"\r
36 \r
37 /**\r
38 * \brief This structure defines the various Configuration Parameters for\r
39 * a DPLL.\r
40 */\r
41 typedef struct {\r
42 Uint32 mult;\r
43 /**< Multiplier(m) Value */\r
44 Uint32 div;\r
45 /**< Divider(n) Value */\r
46 Uint32 dccEnable;\r
47 /**< Divider(n) Value */\r
48 Uint32 autoDpllMode;\r
49 /**< Auto DPLL Mode, refer to enum #sbllibAutoDpllMode_t for values */\r
50 Uint32 divM2;\r
51 /**< M2 Divider Value */\r
52 Uint32 divM3;\r
53 /**< M3 Divider Value */\r
54 Uint32 divH11;\r
55 /**< H11 Divider Value */\r
56 Uint32 divH12;\r
57 /**< H12 Divider Value */\r
58 Uint32 divH13;\r
59 /**< H13 Divider Value */\r
60 Uint32 divH14;\r
61 /**< H14 Divider Value */\r
62 Uint32 divH21;\r
63 /**< H21 Divider Value */\r
64 Uint32 divH22;\r
65 /**< H22 Divider Value */\r
66 Uint32 divH23;\r
67 /**< H23 Divider Value */\r
68 Uint32 divH24;\r
69 /**< H24 Divider Value */\r
70 } pllcParam;\r
71 \r
72 /**\r
73 * \brief This structure defines the various Configuration Parameters for\r
74 * a MPU DPLL.\r
75 */\r
76 typedef struct {\r
77 Uint32 mult;\r
78 /**< Multiplier(m) Value */\r
79 Uint32 div;\r
80 /**< Divider(n) Value */\r
81 Uint32 dccEnable;\r
82 /**< Divider(n) Value */\r
83 Uint32 divM2;\r
84 /**< M2 Divider Value */\r
85 } pllcMpuParam;\r
86 \r
87 /**\r
88 * \brief This structure defines the various Configuration Parameters for\r
89 * a peripheral DPLL.\r
90 */\r
91 typedef struct {\r
92 Uint32 mult;\r
93 /**< Multiplier(m) Value */\r
94 Uint32 div;\r
95 /**< Divider(n) Value */\r
96 Uint32 divM2;\r
97 /**< M2 Divider Value */\r
98 Uint32 divM3;\r
99 /**< M3 Divider Value */\r
100 Uint32 divH11;\r
101 /**< H11 Divider Value */\r
102 Uint32 divH12;\r
103 /**< H12 Divider Value */\r
104 Uint32 divH13;\r
105 /**< H13 Divider Value */\r
106 Uint32 divH14;\r
107 /**< H14 Divider Value */\r
108 } pllcPerParam;\r
109 \r
110 /**\r
111 * \brief This structure defines the various Configuration Parameters for\r
112 * a core DPLL.\r
113 */\r
114 typedef struct {\r
115 Uint32 l3ClkSel;\r
116 /**< L3 divider */\r
117 Uint32 l4ClkSel;\r
118 /**< L3 divider */\r
119 Uint32 mult;\r
120 /**< Multiplier(m) Value */\r
121 Uint32 div;\r
122 /**< Divider(n) Value */\r
123 Uint32 divM2;\r
124 /**< M2 Divider Value */\r
125 Uint32 divM3;\r
126 /**< M3 Divider Value */\r
127 Uint32 divH12;\r
128 /**< H12 Divider Value */\r
129 Uint32 divH13;\r
130 /**< H13 Divider Value */\r
131 Uint32 divH14;\r
132 /**< H14 Divider Value */\r
133 Uint32 divH22;\r
134 /**< H22 Divider Value */\r
135 Uint32 divH23;\r
136 /**< H23 Divider Value */\r
137 Uint32 divH24;\r
138 /**< H24 Divider Value */\r
139 } pllcCoreParam;\r
140 \r
141 /**\r
142 * \brief This structure defines the various Configuration Parameters for\r
143 * an ABE DPLL.\r
144 */\r
145 typedef struct {\r
146 Uint32 mult;\r
147 /**< Multiplier(m) Value */\r
148 Uint32 div;\r
149 /**< Divider(n) Value */\r
150 Uint32 divM2;\r
151 /**< M2 Divider Value */\r
152 Uint32 divM3;\r
153 /**< M3 Divider Value */\r
154 } pllcAbeParam;\r
155 \r
156 /**\r
157 * \brief This structure defines the various Configuration Parameters for\r
158 * an IVA DPLL.\r
159 */\r
160 typedef struct {\r
161 Uint32 mult;\r
162 /**< Multiplier(m) Value */\r
163 Uint32 div;\r
164 /**< Divider(n) Value */\r
165 Uint32 divM2;\r
166 /**< M2 Divider Value */\r
167 } pllcIvaParam;\r
168 \r
169 /**\r
170 * \brief This structure defines the various Configuration Parameters for\r
171 * a GMAC DPLL.\r
172 */\r
173 typedef struct {\r
174 Uint32 mult;\r
175 /**< Multiplier(m) Value */\r
176 Uint32 div;\r
177 /**< Divider(n) Value */\r
178 Uint32 divM2;\r
179 /**< M2 Divider Value */\r
180 Uint32 divM3;\r
181 /**< M3 Divider Value */\r
182 Uint32 divH11;\r
183 /**< H11 Divider Value */\r
184 Uint32 divH12;\r
185 /**< H12 Divider Value */\r
186 Uint32 divH13;\r
187 /**< H13 Divider Value */\r
188 } pllcGmacParam;\r
189 \r
190 /**\r
191 * \brief This structure defines the various Configuration Parameters for\r
192 * a PCIE DPLL.\r
193 */\r
194 typedef struct {\r
195 Uint32 mult;\r
196 /**< Multiplier(m) Value */\r
197 Uint32 div;\r
198 /**< Divider(n) Value */\r
199 Uint32 divM2;\r
200 /**< M2 Divider Value */\r
201 } pllcPcieParam;\r
202 \r
203 /**\r
204 * \brief This structure defines the various Configuration Parameters for\r
205 * a DDR DPLL.\r
206 */\r
207 typedef struct {\r
208 Uint32 mult;\r
209 /**< Multiplier(m) Value */\r
210 Uint32 div;\r
211 /**< Divider(n) Value */\r
212 Uint32 divM2;\r
213 /**< M2 Divider Value */\r
214 Uint32 divM3;\r
215 /**< M3 Divider Value */\r
216 Uint32 divH11;\r
217 /**< H11 Divider Value */\r
218 } pllcDdrParam;\r
219 \r
220 /**\r
221 * \brief This structure defines the various Configuration Parameters for\r
222 * a GPU DPLL.\r
223 */\r
224 typedef struct {\r
225 Uint32 mult;\r
226 /**< Multiplier(m) Value */\r
227 Uint32 div;\r
228 /**< Divider(n) Value */\r
229 Uint32 divM2;\r
230 /**< M2 Divider Value */\r
231 } pllcGpuParam;\r
232 \r
233 /**\r
234 * \brief This structure defines the various Configuration Parameters for\r
235 * a DSP DPLL.\r
236 */\r
237 typedef struct {\r
238 Uint32 mult;\r
239 /**< Multiplier(m) Value */\r
240 Uint32 div;\r
241 /**< Divider(n) Value */\r
242 Uint32 divM2;\r
243 /**< M2 Divider Value */\r
244 Uint32 divM3;\r
245 /**< M3 Divider Value */\r
246 } pllcDspParam;\r
247 \r
248 void pllcMpuUnlock(void);\r
249 \r
250 void pllcMpuLock(void);\r
251 \r
252 void pllcMpuConfigure(pllcMpuParam *mpuPllcParam);\r
253 \r
254 void pllcIvaUnlock(void);\r
255 \r
256 void pllcIvaLock(void);\r
257 \r
258 void pllcIvaConfigure(pllcIvaParam *ivaPllcParam);\r
259 \r
260 void pllcCoreUnlock(void);\r
261 \r
262 void pllcCoreLock(void);\r
263 \r
264 void pllcCoreConfigure(pllcCoreParam *corePllcParam);\r
265 \r
266 void pllcAbeUnlock(void);\r
267 \r
268 void pllcAbeLock(void);\r
269 \r
270 void pllcAbeConfigure(pllcAbeParam *abePllcParam);\r
271 \r
272 void pllcDdrUnlock(void);\r
273 \r
274 void pllcDdrLock(void);\r
275 \r
276 void pllcDdrConfigure(pllcDdrParam *ddrPllcParam);\r
277 \r
278 void pllcDspUnlock(void);\r
279 \r
280 void pllcDspLock(void);\r
281 \r
282 void pllcDspConfigure(pllcDspParam *dspPllcParam);\r
283 \r
284 void pllcGmacUnlock(void);\r
285 \r
286 void pllcGmacLock(void);\r
287 \r
288 void pllcGmacConfigure(pllcGmacParam *gmacPllcParam);\r
289 \r
290 void pllcGpuUnlock(void);\r
291 \r
292 void pllcGpuLock(void);\r
293 \r
294 void pllcGpuConfigure(pllcGpuParam *gpuPllcParam);\r
295 \r
296 void pllcPcieUnlock(void);\r
297 \r
298 void pllcPcieLock(void);\r
299 \r
300 void pllcPcieConfigure(pllcPcieParam *pciePllcParam);\r
301 \r
302 void pllcPerUnlock(void);\r
303 \r
304 void pllcPerLock(void);\r
305 \r
306 void pllcPerConfigure(pllcPerParam *perPllcParam);\r
307 \r
308 \r
309 /* Set the desired DDR3 configuration -- assumes 66.67 MHz DDR3 clock input */\r
310 Board_STATUS Board_PLLInit(Uint32 opp)\r
311 {\r
312 pllcMpuParam mpuPllcParam;\r
313 pllcIvaParam ivaPllcParam;\r
314 pllcCoreParam corePllcParam;\r
315 pllcAbeParam abePllcParam;\r
316 pllcDdrParam ddrPllcParam;\r
317 pllcDspParam dspPllcParam;\r
318 pllcGmacParam gmacPllcParam;\r
319 pllcGpuParam gpuPllcParam;\r
320 pllcPcieParam pciePllcParam;\r
321 pllcPerParam perPllcParam;\r
322 CSL_ckgen_prmRegs *hCkgenPrm =\r
323 (CSL_ckgen_prmRegs *) CSL_MPU_CKGEN_PRM_REGS;\r
324 \r
325 if (OPP_HIGH == opp)\r
326 {\r
327 /* 1500MHz at 20MHz sys_clk */\r
328 mpuPllcParam.mult = 600U;\r
329 mpuPllcParam.div = 7U;\r
330 mpuPllcParam.dccEnable = 1U;\r
331 mpuPllcParam.divM2 = 1U;\r
332 }\r
333 else if (OPP_OD == opp)\r
334 {\r
335 /* 1176MHz at 20MHz sys_clk */\r
336 mpuPllcParam.mult = 294U;\r
337 mpuPllcParam.div = 4U;\r
338 mpuPllcParam.dccEnable = 0U;\r
339 mpuPllcParam.divM2 = 1U;\r
340 }\r
341 else \r
342 {\r
343 /* Default to OPP_NOM */\r
344 /* 1000MHz at 20MHz sys_clk */\r
345 mpuPllcParam.mult = 500U;\r
346 mpuPllcParam.div = 9U;\r
347 mpuPllcParam.dccEnable = 0U;\r
348 mpuPllcParam.divM2 = 1U;\r
349 }\r
350 \r
351 pllcMpuUnlock();\r
352 pllcMpuConfigure(&mpuPllcParam);\r
353 pllcMpuLock();\r
354 \r
355 if (OPP_HIGH == opp)\r
356 {\r
357 /* 532MHz at 20MHz sys_clk */\r
358 ivaPllcParam.mult = 266U;\r
359 ivaPllcParam.div = 4U;\r
360 ivaPllcParam.divM2 = 2U;\r
361 }\r
362 else if (OPP_OD == opp)\r
363 {\r
364 /* 430MHz at 20MHz sys_clk */\r
365 ivaPllcParam.mult = 172U;\r
366 ivaPllcParam.div = 3U;\r
367 ivaPllcParam.divM2 = 2U;\r
368 }\r
369 else \r
370 {\r
371 /* Default to OPP_NOM */\r
372 /* 388.3MHz at 20MHz sys_clk */\r
373 ivaPllcParam.mult = 233U;\r
374 ivaPllcParam.div = 3U;\r
375 ivaPllcParam.divM2 = 3U;\r
376 }\r
377 pllcIvaUnlock();\r
378 pllcIvaConfigure(&ivaPllcParam);\r
379 pllcIvaLock();\r
380 \r
381 perPllcParam.mult = 0x60U;\r
382 perPllcParam.div = 4U;\r
383 perPllcParam.divM2 = 4U;\r
384 perPllcParam.divM3 = 1U;\r
385 perPllcParam.divH11 = 3U;\r
386 perPllcParam.divH12 = 4U;\r
387 perPllcParam.divH13 = 4U;\r
388 perPllcParam.divH14 = 2U;\r
389 pllcPerUnlock();\r
390 pllcPerConfigure(&perPllcParam);\r
391 pllcPerLock();\r
392 \r
393 corePllcParam.l3ClkSel = 1U;\r
394 corePllcParam.l4ClkSel = 1U;\r
395 corePllcParam.mult = 0x10AU;\r
396 corePllcParam.div = 0x4U;\r
397 corePllcParam.divM2 = 2U;\r
398 corePllcParam.divM3 = 1U;\r
399 corePllcParam.divH12 = 4U;\r
400 corePllcParam.divH13 = 0x3EU;\r
401 corePllcParam.divH14 = 0x5U;\r
402 corePllcParam.divH22 = 0x5U;\r
403 corePllcParam.divH23 = 0x4U;\r
404 corePllcParam.divH24 = 0x6U;\r
405 pllcCoreUnlock();\r
406 pllcCoreConfigure(&corePllcParam);\r
407 pllcCoreLock();\r
408 \r
409 hCkgenPrm->CM_CLKSEL_ABE_PLL_REF_REG = 0x00000000U;\r
410 \r
411 abePllcParam.mult = 0x13U;\r
412 abePllcParam.div = 0x1U;\r
413 abePllcParam.divM2 = 1U;\r
414 abePllcParam.divM3 = 1U;\r
415 pllcAbeUnlock();\r
416 pllcAbeConfigure(&abePllcParam);\r
417 pllcAbeLock();\r
418 \r
419 gmacPllcParam.mult = 0xFAU;\r
420 gmacPllcParam.div = 0x4U;\r
421 gmacPllcParam.divM2 = 0x4U;\r
422 gmacPllcParam.divM3 = 0xAU;\r
423 gmacPllcParam.divH11 = 0x28U;\r
424 gmacPllcParam.divH12 = 0x8U;\r
425 gmacPllcParam.divH13 = 0xAU;\r
426 pllcGmacUnlock();\r
427 pllcGmacConfigure(&gmacPllcParam);\r
428 pllcGmacLock();\r
429 \r
430 if(OPP_HIGH == opp)\r
431 {\r
432 /* 532MHz at 20MHz sys_clk */\r
433 gpuPllcParam.mult = 266U;\r
434 gpuPllcParam.div = 4U;\r
435 gpuPllcParam.divM2 = 2U;\r
436 }\r
437 else if(OPP_OD == opp)\r
438 {\r
439 /* 500MHz at 20MHz sys_clk */\r
440 gpuPllcParam.mult = 200U;\r
441 gpuPllcParam.div = 3U;\r
442 gpuPllcParam.divM2 = 2U;\r
443 }\r
444 else\r
445 {\r
446 /* Default to OPP_NOM */\r
447 /* 425MHz at 20MHz sys_clk */\r
448 gpuPllcParam.mult = 170U;\r
449 gpuPllcParam.div = 3U;\r
450 gpuPllcParam.divM2 = 2U;\r
451 }\r
452 pllcGpuUnlock();\r
453 pllcGpuConfigure(&gpuPllcParam);\r
454 pllcGpuLock();\r
455 \r
456 if(OPP_HIGH == opp)\r
457 {\r
458 /* 750MHz at 20MHz sys_clk */\r
459 dspPllcParam.mult = 150U;\r
460 dspPllcParam.div = 3U;\r
461 dspPllcParam.divM2 = 1U;\r
462 dspPllcParam.divM3 = 3U;\r
463 }\r
464 else if(OPP_OD == opp)\r
465 {\r
466 /* 500MHz at 20MHz sys_clk */\r
467 dspPllcParam.mult = 130U;\r
468 dspPllcParam.div = 3U;\r
469 dspPllcParam.divM2 = 1U;\r
470 dspPllcParam.divM3 = 3U;\r
471 }\r
472 else\r
473 {\r
474 /* Default to OPP_NOM */\r
475 /* 425MHz at 20MHz sys_clk */\r
476 dspPllcParam.mult = 150U;\r
477 dspPllcParam.div = 4U;\r
478 dspPllcParam.divM2 = 1U;\r
479 dspPllcParam.divM3 = 3U;\r
480 }\r
481 pllcDspUnlock();\r
482 pllcDspConfigure(&dspPllcParam);\r
483 pllcDspLock();\r
484 \r
485 pciePllcParam.mult = 750U;\r
486 pciePllcParam.div = 9U;\r
487 pciePllcParam.divM2 = 15U;\r
488 pllcPcieUnlock();\r
489 pllcPcieConfigure(&pciePllcParam);\r
490 pllcPcieLock();\r
491 \r
492 ddrPllcParam.mult = 0x10AU;\r
493 ddrPllcParam.div = 0x4U;\r
494 ddrPllcParam.divM2 = 0x2U;\r
495 ddrPllcParam.divM3 = 0x1U;\r
496 ddrPllcParam.divH11 = 0x8U;\r
497 pllcDdrUnlock();\r
498 pllcDdrConfigure(&ddrPllcParam);\r
499 pllcDdrLock();\r
500 return BOARD_SOK;\r
501 }\r
502 \r
503 void CtrlLockMMR(void)\r
504 {\r
505 CSL_control_coreRegs *ctrlCoreReg =\r
506 (CSL_control_coreRegs *) CSL_MPU_CTRL_MODULE_CORE_CORE_REGISTERS_REGS;\r
507 \r
508 /* unlock MMR1 space for region 0x0100 to 0x079F */\r
509 ctrlCoreReg->MMR_LOCK_1 = 438075716U;\r
510 /* unlock MMR2 space for region 0x07A0 to 0x0D9F */\r
511 ctrlCoreReg->MMR_LOCK_2 = 4260648240U;\r
512 /* unlock MMR3 space for region 0x0DA0 to 0x0FFF */\r
513 ctrlCoreReg->MMR_LOCK_3 = 451339040U;\r
514 /* unlock MMR4 space for region 0x1000 to 0x13FF */\r
515 ctrlCoreReg->MMR_LOCK_4 = 515838749U;\r
516 /* unlock MMR5 space for region 0x1400 to 0x1FFF */\r
517 ctrlCoreReg->MMR_LOCK_5 = 339706668U;\r
518 }\r
519 \r
520 void pllcMpuUnlock(void)\r
521 {\r
522 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =\r
523 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;\r
524 \r
525 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_MPU_REG,\r
526 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_MPU_REG_DPLL_EN,\r
527 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_MPU_REG_DPLL_EN_DPLL_LP_BYP_MODE);\r
528 }\r
529 \r
530 void pllcMpuLock(void)\r
531 {\r
532 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =\r
533 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;\r
534 \r
535 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_MPU_REG,\r
536 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_MPU_REG_DPLL_EN,\r
537 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_MPU_REG_DPLL_EN_DPLL_LOCK_MODE);\r
538 }\r
539 \r
540 void pllcMpuConfigure(pllcMpuParam *mpuPllcParam)\r
541 {\r
542 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =\r
543 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;\r
544 \r
545 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_MPU_REG,\r
546 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_MPU_REG_DPLL_DIV, mpuPllcParam->div);\r
547 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_MPU_REG,\r
548 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_MPU_REG_DPLL_MULT, mpuPllcParam->mult);\r
549 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_MPU_REG,\r
550 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_MPU_REG_DCC_EN, mpuPllcParam->dccEnable);\r
551 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_M2_DPLL_MPU_REG,\r
552 CKGEN_CM_CORE_AON_CM_DIV_M2_DPLL_MPU_REG_DIVHS, mpuPllcParam->divM2);\r
553 }\r
554 \r
555 void pllcIvaUnlock(void)\r
556 {\r
557 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =\r
558 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;\r
559 \r
560 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_IVA_REG,\r
561 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_IVA_REG_DPLL_EN,\r
562 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_IVA_REG_DPLL_EN_DPLL_LP_BYP_MODE);\r
563 }\r
564 \r
565 void pllcIvaLock(void)\r
566 {\r
567 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =\r
568 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;\r
569 \r
570 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_IVA_REG,\r
571 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_IVA_REG_DPLL_EN,\r
572 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_IVA_REG_DPLL_EN_DPLL_LOCK_MODE);\r
573 }\r
574 \r
575 void pllcIvaConfigure(pllcIvaParam *ivaPllcParam)\r
576 {\r
577 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =\r
578 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;\r
579 \r
580 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_IVA_REG,\r
581 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_IVA_REG_DPLL_DIV, ivaPllcParam->div);\r
582 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_IVA_REG,\r
583 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_IVA_REG_DPLL_MULT, ivaPllcParam->mult);\r
584 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_M2_DPLL_IVA_REG,\r
585 CKGEN_CM_CORE_AON_CM_DIV_M2_DPLL_IVA_REG_DIVHS, ivaPllcParam->divM2);\r
586 }\r
587 \r
588 void pllcCoreUnlock(void)\r
589 {\r
590 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =\r
591 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;\r
592 \r
593 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_CORE_REG,\r
594 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_CORE_REG_DPLL_EN,\r
595 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_CORE_REG_DPLL_EN_DPLL_LP_BYP_MODE);\r
596 }\r
597 \r
598 void pllcCoreLock(void)\r
599 {\r
600 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =\r
601 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;\r
602 \r
603 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_CORE_REG,\r
604 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_CORE_REG_DPLL_EN,\r
605 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_CORE_REG_DPLL_EN_DPLL_LOCK_MODE);\r
606 }\r
607 \r
608 void pllcCoreConfigure(pllcCoreParam *corePllcParam)\r
609 {\r
610 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =\r
611 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;\r
612 \r
613 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_CORE_REG,\r
614 CKGEN_CM_CORE_AON_CM_CLKSEL_CORE_REG_CLKSEL_L3, corePllcParam->l3ClkSel);\r
615 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_CORE_REG,\r
616 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_CORE_REG_DPLL_DIV, corePllcParam->div);\r
617 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_CORE_REG,\r
618 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_CORE_REG_DPLL_MULT, corePllcParam->mult);\r
619 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_M2_DPLL_CORE_REG,\r
620 CKGEN_CM_CORE_AON_CM_DIV_M2_DPLL_CORE_REG_DIVHS, corePllcParam->divM2);\r
621 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_M3_DPLL_CORE_REG,\r
622 CKGEN_CM_CORE_AON_CM_DIV_M3_DPLL_CORE_REG_DIVHS, corePllcParam->divM3);\r
623 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_H12_DPLL_CORE_REG,\r
624 CKGEN_CM_CORE_AON_CM_DIV_H12_DPLL_CORE_REG_DIVHS, corePllcParam->divH12);\r
625 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_H13_DPLL_CORE_REG,\r
626 CKGEN_CM_CORE_AON_CM_DIV_H13_DPLL_CORE_REG_DIVHS, corePllcParam->divH13);\r
627 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_H14_DPLL_CORE_REG,\r
628 CKGEN_CM_CORE_AON_CM_DIV_H14_DPLL_CORE_REG_DIVHS, corePllcParam->divH14);\r
629 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_H22_DPLL_CORE_REG,\r
630 CKGEN_CM_CORE_AON_CM_DIV_H22_DPLL_CORE_REG_DIVHS, corePllcParam->divH22);\r
631 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_H23_DPLL_CORE_REG,\r
632 CKGEN_CM_CORE_AON_CM_DIV_H23_DPLL_CORE_REG_DIVHS, corePllcParam->divH23);\r
633 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_H24_DPLL_CORE_REG,\r
634 CKGEN_CM_CORE_AON_CM_DIV_H24_DPLL_CORE_REG_DIVHS, corePllcParam->divH24);\r
635 }\r
636 \r
637 void pllcAbeUnlock(void)\r
638 {\r
639 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =\r
640 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;\r
641 \r
642 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_ABE_REG,\r
643 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN,\r
644 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN_DPLL_LP_BYP_MODE);\r
645 }\r
646 \r
647 void pllcAbeLock(void)\r
648 {\r
649 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =\r
650 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;\r
651 \r
652 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_ABE_REG,\r
653 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN,\r
654 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN_DPLL_LOCK_MODE);\r
655 }\r
656 \r
657 void pllcAbeConfigure(pllcAbeParam *abePllcParam)\r
658 {\r
659 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =\r
660 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;\r
661 \r
662 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_ABE_REG,\r
663 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_ABE_REG_DPLL_DIV, abePllcParam->div);\r
664 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_ABE_REG,\r
665 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_ABE_REG_DPLL_MULT, abePllcParam->mult);\r
666 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_M2_DPLL_ABE_REG,\r
667 CKGEN_CM_CORE_AON_CM_DIV_M2_DPLL_ABE_REG_DIVHS, abePllcParam->divM2);\r
668 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_M3_DPLL_ABE_REG,\r
669 CKGEN_CM_CORE_AON_CM_DIV_M3_DPLL_ABE_REG_DIVHS, abePllcParam->divM3);\r
670 }\r
671 \r
672 void pllcDdrUnlock(void)\r
673 {\r
674 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =\r
675 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;\r
676 \r
677 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_DDR_REG,\r
678 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_DDR_REG_DPLL_EN,\r
679 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_DDR_REG_DPLL_EN_DPLL_LP_BYP_MODE);\r
680 }\r
681 \r
682 void pllcDdrLock(void)\r
683 {\r
684 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =\r
685 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;\r
686 \r
687 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_DDR_REG,\r
688 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_DDR_REG_DPLL_EN,\r
689 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_DDR_REG_DPLL_EN_DPLL_LOCK_MODE);\r
690 }\r
691 \r
692 void pllcDdrConfigure(pllcDdrParam *ddrPllcParam)\r
693 {\r
694 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =\r
695 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;\r
696 \r
697 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_DDR_REG,\r
698 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_DDR_REG_DPLL_DIV, ddrPllcParam->div);\r
699 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_DDR_REG,\r
700 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_DDR_REG_DPLL_MULT, ddrPllcParam->mult);\r
701 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_M2_DPLL_DDR_REG,\r
702 CKGEN_CM_CORE_AON_CM_DIV_M2_DPLL_DDR_REG_DIVHS, ddrPllcParam->divM2);\r
703 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_M3_DPLL_DDR_REG,\r
704 CKGEN_CM_CORE_AON_CM_DIV_M3_DPLL_DDR_REG_DIVHS, ddrPllcParam->divM3);\r
705 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_H11_DPLL_DDR_REG,\r
706 CKGEN_CM_CORE_AON_CM_DIV_H11_DPLL_DDR_REG_DIVHS, ddrPllcParam->divH11);\r
707 }\r
708 \r
709 void pllcDspUnlock(void)\r
710 {\r
711 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =\r
712 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;\r
713 \r
714 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_DSP_REG,\r
715 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_DSP_REG_DPLL_EN,\r
716 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_DSP_REG_DPLL_EN_DPLL_LP_BYP_MODE);\r
717 }\r
718 \r
719 void pllcDspLock(void)\r
720 {\r
721 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =\r
722 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;\r
723 \r
724 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_DSP_REG,\r
725 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_DSP_REG_DPLL_EN,\r
726 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_DSP_REG_DPLL_EN_DPLL_LOCK_MODE);\r
727 }\r
728 \r
729 void pllcDspConfigure(pllcDspParam *dspPllcParam)\r
730 {\r
731 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =\r
732 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;\r
733 \r
734 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_DSP_REG,\r
735 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_DSP_REG_DPLL_DIV, dspPllcParam->div);\r
736 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_DSP_REG,\r
737 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_DSP_REG_DPLL_MULT, dspPllcParam->mult);\r
738 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_M2_DPLL_DSP_REG,\r
739 CKGEN_CM_CORE_AON_CM_DIV_M2_DPLL_DSP_REG_DIVHS, dspPllcParam->divM2);\r
740 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_M3_DPLL_DSP_REG,\r
741 CKGEN_CM_CORE_AON_CM_DIV_M3_DPLL_DSP_REG_DIVHS, dspPllcParam->divM3);\r
742 }\r
743 \r
744 void pllcGmacUnlock(void)\r
745 {\r
746 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =\r
747 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;\r
748 \r
749 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_GMAC_REG,\r
750 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_GMAC_REG_DPLL_EN,\r
751 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_GMAC_REG_DPLL_EN_DPLL_LP_BYP_MODE);\r
752 }\r
753 \r
754 void pllcGmacLock(void)\r
755 {\r
756 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =\r
757 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;\r
758 \r
759 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_GMAC_REG,\r
760 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_GMAC_REG_DPLL_EN,\r
761 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_GMAC_REG_DPLL_EN_DPLL_LOCK_MODE);\r
762 }\r
763 \r
764 void pllcGmacConfigure(pllcGmacParam *gmacPllcParam)\r
765 {\r
766 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =\r
767 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;\r
768 \r
769 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_GMAC_REG,\r
770 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_GMAC_REG_DPLL_DIV, gmacPllcParam->div);\r
771 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_GMAC_REG,\r
772 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_GMAC_REG_DPLL_MULT, gmacPllcParam->mult);\r
773 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_M2_DPLL_GMAC_REG,\r
774 CKGEN_CM_CORE_AON_CM_DIV_M2_DPLL_GMAC_REG_DIVHS, gmacPllcParam->divM2);\r
775 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_M3_DPLL_GMAC_REG,\r
776 CKGEN_CM_CORE_AON_CM_DIV_M3_DPLL_GMAC_REG_DIVHS, gmacPllcParam->divM3);\r
777 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_H11_DPLL_GMAC_REG,\r
778 CKGEN_CM_CORE_AON_CM_DIV_H11_DPLL_GMAC_REG_DIVHS, gmacPllcParam->divH11);\r
779 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_H12_DPLL_GMAC_REG,\r
780 CKGEN_CM_CORE_AON_CM_DIV_H12_DPLL_GMAC_REG_DIVHS, gmacPllcParam->divH12);\r
781 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_H13_DPLL_GMAC_REG,\r
782 CKGEN_CM_CORE_AON_CM_DIV_H13_DPLL_GMAC_REG_DIVHS, gmacPllcParam->divH13);\r
783 }\r
784 \r
785 void pllcGpuUnlock(void)\r
786 {\r
787 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =\r
788 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;\r
789 \r
790 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_GPU_REG,\r
791 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_GPU_REG_DPLL_EN,\r
792 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_GPU_REG_DPLL_EN_DPLL_LP_BYP_MODE);\r
793 }\r
794 \r
795 void pllcGpuLock(void)\r
796 {\r
797 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =\r
798 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;\r
799 \r
800 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_GPU_REG,\r
801 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_GPU_REG_DPLL_EN,\r
802 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_GPU_REG_DPLL_EN_DPLL_LOCK_MODE);\r
803 }\r
804 \r
805 void pllcGpuConfigure(pllcGpuParam *gpuPllcParam)\r
806 {\r
807 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =\r
808 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;\r
809 \r
810 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_GPU_REG,\r
811 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_GPU_REG_DPLL_DIV, gpuPllcParam->div);\r
812 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_GPU_REG,\r
813 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_GPU_REG_DPLL_MULT, gpuPllcParam->mult);\r
814 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_M2_DPLL_GPU_REG,\r
815 CKGEN_CM_CORE_AON_CM_DIV_M2_DPLL_GPU_REG_DIVHS, gpuPllcParam->divM2);\r
816 }\r
817 \r
818 void pllcPcieUnlock(void)\r
819 {\r
820 CSL_ckgen_cm_coreRegs *ckgenCmCoreReg =\r
821 (CSL_ckgen_cm_coreRegs *) CSL_MPU_CKGEN_CM_CORE_REGS;\r
822 \r
823 CSL_FINS(ckgenCmCoreReg->CM_CLKMODE_DPLL_PCIE_REF_REG,\r
824 CKGEN_CM_CORE_CM_CLKMODE_DPLL_PCIE_REF_REG_DPLL_EN,\r
825 CSL_CKGEN_CM_CORE_CM_CLKMODE_DPLL_PCIE_REF_REG_DPLL_EN_DPLL_LP_BYP_MODE);\r
826 }\r
827 \r
828 void pllcPcieLock(void)\r
829 {\r
830 CSL_ckgen_cm_coreRegs *ckgenCmCoreReg =\r
831 (CSL_ckgen_cm_coreRegs *) CSL_MPU_CKGEN_CM_CORE_REGS;\r
832 \r
833 CSL_FINS(ckgenCmCoreReg->CM_CLKMODE_DPLL_PCIE_REF_REG,\r
834 CKGEN_CM_CORE_CM_CLKMODE_DPLL_PCIE_REF_REG_DPLL_EN,\r
835 CSL_CKGEN_CM_CORE_CM_CLKMODE_DPLL_PCIE_REF_REG_DPLL_EN_DPLL_LOCK_MODE);\r
836 }\r
837 \r
838 void pllcPcieConfigure(pllcPcieParam *pciePllcParam)\r
839 {\r
840 CSL_ckgen_cm_coreRegs *ckgenCmCoreReg =\r
841 (CSL_ckgen_cm_coreRegs *) CSL_MPU_CKGEN_CM_CORE_REGS;\r
842 \r
843 CSL_FINS(ckgenCmCoreReg->CM_CLKSEL_DPLL_PCIE_REF_REG,\r
844 CKGEN_CM_CORE_CM_CLKSEL_DPLL_PCIE_REF_REG_DPLL_DIV, pciePllcParam->div);\r
845 CSL_FINS(ckgenCmCoreReg->CM_CLKSEL_DPLL_PCIE_REF_REG,\r
846 CKGEN_CM_CORE_CM_CLKSEL_DPLL_PCIE_REF_REG_DPLL_MULT, pciePllcParam->mult);\r
847 CSL_FINS(ckgenCmCoreReg->CM_DIV_M2_DPLL_PCIE_REF_REG,\r
848 CKGEN_CM_CORE_CM_DIV_M2_DPLL_PCIE_REF_REG_DIVHS, pciePllcParam->divM2);\r
849 }\r
850 \r
851 void pllcPerUnlock(void)\r
852 {\r
853 CSL_ckgen_cm_coreRegs *ckgenCmCoreReg =\r
854 (CSL_ckgen_cm_coreRegs *) CSL_MPU_CKGEN_CM_CORE_REGS;\r
855 \r
856 CSL_FINS(ckgenCmCoreReg->CM_CLKMODE_DPLL_PER_REG,\r
857 CKGEN_CM_CORE_CM_CLKMODE_DPLL_PER_REG_DPLL_EN,\r
858 CSL_CKGEN_CM_CORE_CM_CLKMODE_DPLL_PER_REG_DPLL_EN_DPLL_LP_BYP_MODE);\r
859 }\r
860 \r
861 void pllcPerLock(void)\r
862 {\r
863 CSL_ckgen_cm_coreRegs *ckgenCmCoreReg =\r
864 (CSL_ckgen_cm_coreRegs *) CSL_MPU_CKGEN_CM_CORE_REGS;\r
865 \r
866 CSL_FINS(ckgenCmCoreReg->CM_CLKMODE_DPLL_PER_REG,\r
867 CKGEN_CM_CORE_CM_CLKMODE_DPLL_PER_REG_DPLL_EN,\r
868 CSL_CKGEN_CM_CORE_CM_CLKMODE_DPLL_PER_REG_DPLL_EN_DPLL_LOCK_MODE);\r
869 }\r
870 \r
871 void pllcPerConfigure(pllcPerParam *perPllcParam)\r
872 {\r
873 CSL_ckgen_cm_coreRegs *ckgenCmCoreReg =\r
874 (CSL_ckgen_cm_coreRegs *) CSL_MPU_CKGEN_CM_CORE_REGS;\r
875 \r
876 CSL_FINS(ckgenCmCoreReg->CM_CLKSEL_DPLL_PER_REG,\r
877 CKGEN_CM_CORE_CM_CLKSEL_DPLL_PER_REG_DPLL_DIV, perPllcParam->div);\r
878 CSL_FINS(ckgenCmCoreReg->CM_CLKSEL_DPLL_PER_REG,\r
879 CKGEN_CM_CORE_CM_CLKSEL_DPLL_PER_REG_DPLL_MULT, perPllcParam->mult);\r
880 CSL_FINS(ckgenCmCoreReg->CM_DIV_M2_DPLL_PER_REG,\r
881 CKGEN_CM_CORE_CM_DIV_M2_DPLL_PER_REG_DIVHS, perPllcParam->divM2);\r
882 CSL_FINS(ckgenCmCoreReg->CM_DIV_M3_DPLL_PER_REG,\r
883 CKGEN_CM_CORE_CM_DIV_M3_DPLL_PER_REG_DIVHS, perPllcParam->divM3);\r
884 CSL_FINS(ckgenCmCoreReg->CM_DIV_H11_DPLL_PER_REG,\r
885 CKGEN_CM_CORE_CM_DIV_H11_DPLL_PER_REG_DIVHS, perPllcParam->divH11);\r
886 CSL_FINS(ckgenCmCoreReg->CM_DIV_H12_DPLL_PER_REG,\r
887 CKGEN_CM_CORE_CM_DIV_H12_DPLL_PER_REG_DIVHS, perPllcParam->divH12);\r
888 CSL_FINS(ckgenCmCoreReg->CM_DIV_H13_DPLL_PER_REG,\r
889 CKGEN_CM_CORE_CM_DIV_H13_DPLL_PER_REG_DIVHS, perPllcParam->divH13);\r
890 CSL_FINS(ckgenCmCoreReg->CM_DIV_H14_DPLL_PER_REG,\r
891 CKGEN_CM_CORE_CM_DIV_H14_DPLL_PER_REG_DIVHS, perPllcParam->divH14);\r
892 }\r