1 /******************************************************************************\r
2 * Copyright (c) 2010-2015 Texas Instruments Incorporated - http://www.ti.com\r
3 *\r
4 * Redistribution and use in source and binary forms, with or without\r
5 * modification, are permitted provided that the following conditions\r
6 * are met:\r
7 *\r
8 * Redistributions of source code must retain the above copyright\r
9 * notice, this list of conditions and the following disclaimer.\r
10 *\r
11 * Redistributions in binary form must reproduce the above copyright\r
12 * notice, this list of conditions and the following disclaimer in the\r
13 * documentation and/or other materials provided with the\r
14 * distribution.\r
15 *\r
16 * Neither the name of Texas Instruments Incorporated nor the names of\r
17 * its contributors may be used to endorse or promote products derived\r
18 * from this software without specific prior written permission.\r
19 *\r
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
31 *\r
32 *****************************************************************************/\r
33 \r
34 #include <ti/csl/csl_bootcfgAux.h>\r
35 #include <ti/csl/cslr_device.h>\r
36 #include <ti/csl/csl_xmcAux.h>\r
37 #include <ti/csl/csl_emif4fAux.h>\r
38 #include <ti/csl/hw_types.h>\r
39 \r
40 #include "board_internal.h"\r
41 \r
42 extern void BOARD_delay(uint32_t usecs);\r
43 \r
44 static void xmc_add_emif_cfg_region()\r
45 {\r
46 /* mapping for ddr emif registers XMPAX*2 */\r
47 CSL_XMC_XMPAXL mpaxl;\r
48 CSL_XMC_XMPAXH mpaxh;\r
49 \r
50 /* base addr + seg size (64KB)*/ //"1B"-->"B" by xj */\r
51 mpaxh.bAddr = (0x2100000B >> 12);\r
52 mpaxh.segSize = (0x2100000B & 0x0000001F);\r
53 \r
54 /* replacement addr + perm*/\r
55 mpaxl.rAddr = 0x100000;\r
56 mpaxl.sr = 1;\r
57 mpaxl.sw = 1;\r
58 mpaxl.sx = 1;\r
59 mpaxl.ur = 1;\r
60 mpaxl.uw = 1;\r
61 mpaxl.ux = 1;\r
62 \r
63 /* set the xmpax for index2 */\r
64 CSL_XMC_setXMPAXH(2, &mpaxh);\r
65 CSL_XMC_setXMPAXL(2, &mpaxl);\r
66 }\r
67 \r
68 /* Set the desired DDR3 configuration -- assumes 66.67 MHz DDR3 clock input */\r
69 Board_STATUS Board_DDR3Init()\r
70 {\r
71 Board_STATUS status = BOARD_SOK;\r
72 uint32_t ddr3config, ddrPhyCtrl;\r
73 uint8_t ddrPHYReadLatency;\r
74 EMIF4F_TIMING1_CONFIG sdram_tim1;\r
75 EMIF4F_TIMING2_CONFIG sdram_tim2;\r
76 EMIF4F_TIMING3_CONFIG sdram_tim3;\r
77 EMIF4F_OUTPUT_IMP_CONFIG zqcfg;\r
78 EMIF4F_PWR_MGMT_CONFIG pwrmgmtcfg;\r
79 EMIF4F_SDRAM_CONFIG sdramcfg;\r
80 \r
81 xmc_add_emif_cfg_region();\r
82 \r
83 CSL_BootCfgUnlockKicker();\r
84 \r
85 /**************** 3.3 Leveling Register Configuration ********************/\r
86 CSL_BootCfgGetDDRConfig(0, &ddr3config);\r
87 ddr3config &= ~(0x007FE000); // clear ctrl_slave_ratio field\r
88 CSL_BootCfgSetDDRConfig(0, ddr3config);\r
89 \r
90 CSL_BootCfgGetDDRConfig(0, &ddr3config);\r
91 ddr3config |= 0x00200000; // set ctrl_slave_ratio to 0x100\r
92 CSL_BootCfgSetDDRConfig(0, ddr3config);\r
93 \r
94 CSL_BootCfgGetDDRConfig(12, &ddr3config);\r
95 ddr3config |= 0x08000000; // Set invert_clkout = 1\r
96 CSL_BootCfgSetDDRConfig(12, ddr3config);\r
97 \r
98 CSL_BootCfgGetDDRConfig(0, &ddr3config);\r
99 ddr3config |= 0xF; // set dll_lock_diff to 15\r
100 CSL_BootCfgSetDDRConfig(0, ddr3config);\r
101 \r
102 CSL_BootCfgGetDDRConfig(23, &ddr3config);\r
103 ddr3config |= 0x00000200; // See section 4.2.1, set for partial automatic levelling\r
104 CSL_BootCfgSetDDRConfig(23, ddr3config);\r
105 \r
106 /**************** 3.3 Partial Automatic Leveling ********************/\r
107 ddr3config = 0x00;\r
108 CSL_BootCfgSetDDRConfig(2, ddr3config);\r
109 ddr3config = 0x00;\r
110 CSL_BootCfgSetDDRConfig(3, ddr3config);\r
111 ddr3config = 0x00;\r
112 CSL_BootCfgSetDDRConfig(4, ddr3config);\r
113 ddr3config = 0x00;\r
114 CSL_BootCfgSetDDRConfig(5, ddr3config);\r
115 ddr3config = 0x00000033;\r
116 CSL_BootCfgSetDDRConfig(6, ddr3config);\r
117 ddr3config = 0x0000003A;\r
118 CSL_BootCfgSetDDRConfig(7, ddr3config);\r
119 ddr3config = 0x0000002C;\r
120 CSL_BootCfgSetDDRConfig(8, ddr3config);\r
121 ddr3config = 0x0000002C;\r
122 CSL_BootCfgSetDDRConfig(9, ddr3config);\r
123 ddr3config = 0x0000001C;\r
124 CSL_BootCfgSetDDRConfig(10, ddr3config);\r
125 \r
126 ddr3config = 0x00;\r
127 CSL_BootCfgSetDDRConfig(14, ddr3config);\r
128 ddr3config = 0x00;\r
129 CSL_BootCfgSetDDRConfig(15, ddr3config);\r
130 ddr3config = 0x00;\r
131 CSL_BootCfgSetDDRConfig(16, ddr3config);\r
132 ddr3config = 0x00;\r
133 CSL_BootCfgSetDDRConfig(17, ddr3config);\r
134 ddr3config = 0x000000B7;\r
135 CSL_BootCfgSetDDRConfig(18, ddr3config);\r
136 ddr3config = 0x000000B1;\r
137 CSL_BootCfgSetDDRConfig(19, ddr3config);\r
138 ddr3config = 0x000000A4;\r
139 CSL_BootCfgSetDDRConfig(20, ddr3config);\r
140 ddr3config = 0x000000A4;\r
141 CSL_BootCfgSetDDRConfig(21, ddr3config);\r
142 ddr3config = 0x00000098;\r
143 CSL_BootCfgSetDDRConfig(22, ddr3config);\r
144 \r
145 /* Correct DQS-DQ write timing offset */\r
146 ddr3config = 0x01000000;\r
147 CSL_BootCfgSetDDRConfig(1, ddr3config);\r
148 \r
149 /*Do a PHY reset. Toggle DDR_PHY_CTRL_1 bit 15 0->1->0 */\r
150 CSL_EMIF4F_GetPhyControl(&ddrPhyCtrl, &ddrPHYReadLatency);\r
151 ddrPhyCtrl &= ~(0x00008000);\r
152 CSL_EMIF4F_SetPhyControl(ddrPhyCtrl, ddrPHYReadLatency);\r
153 \r
154 CSL_EMIF4F_GetPhyControl(&ddrPhyCtrl, &ddrPHYReadLatency);\r
155 ddrPhyCtrl |= (0x00008000);\r
156 CSL_EMIF4F_SetPhyControl(ddrPhyCtrl, ddrPHYReadLatency);\r
157 \r
158 CSL_EMIF4F_GetPhyControl(&ddrPhyCtrl, &ddrPHYReadLatency);\r
159 ddrPhyCtrl &= ~(0x00008000);\r
160 CSL_EMIF4F_SetPhyControl(ddrPhyCtrl, ddrPHYReadLatency);\r
161 \r
162 /***************** 3.4 Basic Controller and DRAM configuration ************/\r
163 /* enable configuration */\r
164 /* hEmif->SDRAM_REF_CTRL = 0x00006180; */\r
165 CSL_EMIF4F_EnableInitRefresh();\r
166 CSL_EMIF4F_SetRefreshRate(0x515C);\r
167 \r
168 sdram_tim1.t_wtr = 4;\r
169 sdram_tim1.t_rrd = 1;\r
170 sdram_tim1.t_rc = 0x20;\r
171 sdram_tim1.t_ras = 0x17;\r
172 sdram_tim1.t_wr = 0x09;\r
173 sdram_tim1.t_rcd = 0x09;\r
174 sdram_tim1.t_rp = 0x09;\r
175 CSL_EMIF4F_SetTiming1Config(&sdram_tim1);\r
176 \r
177 /* hEmif->SDRAM_TIM_2 = 0x40877FEC; */\r
178 sdram_tim2.t_cke = 3;\r
179 sdram_tim2.t_rtp = 4;\r
180 sdram_tim2.t_xsrd = 0x1FF;\r
181 sdram_tim2.t_xsnr = 0x071;\r
182 sdram_tim2.t_xp = 3;\r
183 sdram_tim2.t_odt = 0;\r
184 CSL_EMIF4F_SetTiming2Config(&sdram_tim2);\r
185 \r
186 /* hEmif->SDRAM_TIM_3 = 0x55BF87FF; */\r
187 sdram_tim3.t_rasMax = 0xF;\r
188 sdram_tim3.t_rfc = 0x06A;\r
189 sdram_tim3.t_tdqsckmax = 0;\r
190 sdram_tim3.zq_zqcs = 0x3F;\r
191 sdram_tim3.t_ckesr = 4;\r
192 sdram_tim3.t_csta = 0x5;\r
193 sdram_tim3.t_pdll_ul = 0x5;\r
194 CSL_EMIF4F_SetTiming3Config(&sdram_tim3);\r
195 \r
196 /* hEmif->DDR_PHY_CTRL_1 = 0x0010010F; */\r
197 ddrPHYReadLatency = 0x0F;\r
198 ddrPhyCtrl = (0x0010010F);\r
199 CSL_EMIF4F_SetPhyControl(ddrPhyCtrl, ddrPHYReadLatency);\r
200 \r
201 /* hEmif->ZQ_CONFIG = 0x70074C1F; */\r
202 zqcfg.zqRefInterval = 0x4C1F;\r
203 zqcfg.zqZQCLMult = 3;\r
204 zqcfg.zqZQCLInterval = 1;\r
205 zqcfg.zqSFEXITEn = 1;\r
206 zqcfg.zqDualCSEn = 1;\r
207 zqcfg.zqCS0En = 1;\r
208 zqcfg.zqCS1En = 0;\r
209 CSL_EMIF4F_SetOutputImpedanceConfig(&zqcfg);\r
210 \r
211 /* hEmif->PWR_MGMT_CTRL = 0x0; */\r
212 pwrmgmtcfg.csTime = 0;\r
213 pwrmgmtcfg.srTime = 0;\r
214 pwrmgmtcfg.lpMode = 0;\r
215 pwrmgmtcfg.dpdEnable = 0;\r
216 pwrmgmtcfg.pdTime = 0;\r
217 CSL_EMIF4F_SetPowerMgmtConfig(&pwrmgmtcfg);\r
218 \r
219 /* New value with DYN_ODT disabled and SDRAM_DRIVE = RZQ/7 */\r
220 /* hEmif->SDRAM_CONFIG = 0x63077AB3; */\r
221 CSL_EMIF4F_GetSDRAMConfig (&sdramcfg);\r
222 sdramcfg.pageSize = 2;\r
223 sdramcfg.eBank = 0;\r
224 sdramcfg.iBank = 3;\r
225 sdramcfg.rowSize = 5;\r
226 sdramcfg.CASLatency = 14;\r
227 sdramcfg.narrowMode = 1;\r
228 sdramcfg.CASWriteLat = 3;\r
229 sdramcfg.SDRAMDrive = 1;\r
230 sdramcfg.disableDLL = 0;\r
231 sdramcfg.dynODT = 2;\r
232 sdramcfg.ddrDDQS = 0;\r
233 sdramcfg.ddrTerm = 2;\r
234 sdramcfg.iBankPos = 0;\r
235 sdramcfg.type = 3;\r
236 \r
237 CSL_EMIF4F_SetSDRAMConfig(&sdramcfg);\r
238 \r
239 BOARD_delay(600); /*Wait 600us for HW init to complete*/\r
240 \r
241 /* Refresh rate = (7.8*666MHz] */\r
242 /* hEmif->SDRAM_REF_CTRL = 0x0000144F; */\r
243 CSL_EMIF4F_SetRefreshRate(0x0000144F);\r
244 \r
245 /***************** 4.2.1 Partial automatic leveling ************/\r
246 /* hEmif->RDWR_LVL_RMP_CTRL = 0x80000000; */\r
247 CSL_EMIF4F_SetLevelingRampControlInfo(1, 0, 0, 0, 0);\r
248 \r
249 /* Trigger full leveling - This ignores read DQS leveling result and uses ratio forced value */\r
250 /* hEmif->RDWR_LVL_CTRL = 0x80000000; */\r
251 CSL_EMIF4F_SetLevelingControlInfo(1, 0, 0, 0, 0);\r
252 \r
253 /************************************************************\r
254 Wait for min 1048576 DDR clock cycles for leveling to complete\r
255 = 1048576 * 1.5ns = 1572864ns = 1.57ms.\r
256 Actual time = ~10-15 ms\r
257 **************************************************************/\r
258 BOARD_delay(3000); //Wait 3ms for leveling to complete\r
259 \r
260 return status;\r
261 }\r
262 \r