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33 \r
34 #ifndef EVM_K2E_PLL_H
35 #define EVM_K2E_PLL_H
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
41 /** \brief Keystone Main/PA/ARM PLL control registers */
43 /* Main/PA/DDR3 PLLC0 Register Bits */
44 #define PLL_BWADJ_LO_SMASK CSL_BOOTCFG_MAIN_PLL_CTL0_BWADJ_MASK\r
45 #define PLL_BWADJ_LO_SHIFT CSL_BOOTCFG_MAIN_PLL_CTL0_BWADJ_SHIFT\r
46 #define PLL_BWADJ_LO_MASK (PLL_BWADJ_LO_SMASK >> PLL_BWADJ_LO_SHIFT)\r
47 #define PLL_CLKOD_SMASK CSL_BOOTCFG_PASS_PLL_CTL0_CLKOD_MASK\r
48 #define PLL_CLKOD_SHIFT CSL_BOOTCFG_PASS_PLL_CTL0_CLKOD_SHIFT\r
49 #define PLL_CLKOD_MASK (CSL_BOOTCFG_PASS_PLL_CTL0_CLKOD_MASK >> PLL_CLKOD_SHIFT)\r
50 #define PLLM_MULT_HI_SMASK CSL_BOOTCFG_MAIN_PLL_CTL0_PLLM_MASK\r
51 #define PLL_MULT_SHIFT CSL_BOOTCFG_PASS_PLL_CTL0_PLLM_SHIFT\r
52 #define PLL_DIV_MASK CSL_BOOTCFG_MAIN_PLL_CTL0_PLLD_MASK\r
53 \r
54 /* Main/ARM/PA PLLC1 Register Bits */\r
55 #define PLL_BWADJ_HI_MASK CSL_BOOTCFG_MAIN_PLL_CTL1_BWADJ_MASK\r
56 #define PLL_PLLRST CSL_BOOTCFG_PASS_PLL_CTL1_PLLRST_MASK\r
57 #define PLLCTL_ENSAT CSL_BOOTCFG_MAIN_PLL_CTL1_ENSAT_MASK\r
58 #define MAIN_ENSAT_OFFSET CSL_BOOTCFG_MAIN_PLL_CTL1_ENSAT_SHIFT\r
59 #define PA_PLL_SEL CSL_BOOTCFG_PASS_PLL_CTL1_PLLSEL_MASK\r
60 \r
61 /** \brief PLL controller registers */\r
62 \r
63 /* PLLC Register Base address */\r
64 #define PLLCTL_REGS_BASE_ADDR CSL_PLLC_REGS\r
65 \r
66 /* PLLC PLLCTL Register Bits */\r
67 #define PLLCTL_PLLENSRC CSL_PLLC_PLLCTL_PLLENSRC_MASK\r
68 #define PLLCTL_PLLRST CSL_PLLC_PLLCTL_PLLRST_MASK\r
69 #define PLLCTL_PLLPWRDN CSL_PLLC_PLLCTL_PLLPWRDN_MASK\r
70 #define PLLCTL_PLLEN CSL_PLLC_PLLCTL_PLLEN_MASK\r
71 \r
72 /* PLLC SECCTL Register Bits */\r
73 #define PLLCTL_BYPASS CSL_PLLC_SECCTL_BYPASS_MASK\r
74 \r
75 /* PLLC PLLM Bits */\r
76 #define PLLM_MULT_LO_MASK CSL_PLLC_PLLM_PLLM_MASK\r
77 \r
78 /* PLLC PLLDIV Bits */\r
79 #define PLLDIV_ENABLE CSL_PLLC_PLLDIV1_3_DNEN_MASK\r
80 #define PLLM_RATIO_DIV1 (PLLDIV_ENABLE | 0x0)\r
81 #define PLLM_RATIO_DIV2 (PLLDIV_ENABLE | 0x0)\r
82 #define PLLM_RATIO_DIV3 (PLLDIV_ENABLE | 0x1)\r
83 #define PLLM_RATIO_DIV4 (PLLDIV_ENABLE | 0x4)\r
84 #define PLLM_RATIO_DIV5 (PLLDIV_ENABLE | 0x17)\r
85 \r
86 /* PLLC PLLCMD Bits */\r
87 #define PLLSTAT_GO CSL_PLLC_PLLCMD_GOSET_MASK\r
88 \r
89 /* Keystone II Chip misc 1 register */\r
90 #define KS2_CHIP_MISC1 (CSL_BOOT_CFG_REGS + 0xc7c)
91 #define KS2_ARM_PLL_EN CSL_BOOTCFG_CHIP_MISC1_TETRIS_PLL_ENABLE_MASK
93 #ifdef __cplusplus
94 }
95 #endif
97 #endif /* EVM_K2E_PLL_H */