[processor-sdk/pdk.git] / packages / ti / board / src / j7200_evm / AM7xxx_pinmux_data_gesi_cpsw9g.c
1 /**\r
2 * Note: This file was auto-generated by TI PinMux on 5/15/2019 at 8:07:17 AM.\r
3 *\r
4 * \file AM7xxx_pinmux_data.c\r
5 *\r
6 * \brief This file contains the pin mux configurations for the boards.\r
7 * These are prepared based on how the peripherals are extended on\r
8 * the boards.\r
9 *\r
10 * \copyright Copyright (CU) 2019 Texas Instruments Incorporated -\r
11 * http://www.ti.com/\r
12 */\r
13 \r
14 /* ========================================================================== */\r
15 /* Include Files */\r
16 /* ========================================================================== */\r
17 \r
18 #include "AM7xxx_pinmux.h"\r
19 \r
20 /** Peripheral Pin Configurations */\r
21 \r
22 \r
23 static pinmuxPerCfg_t gCpsw9g0PinCfg[] =\r
24 {\r
25 /* MyCPSW9G3 -> CLKOUT -> AA25 */\r
26 {\r
27 PIN_PRG0_PRU1_GPO10, PIN_MODE(0) | \\r
28 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
29 },\r
30 {PINMUX_END}\r
31 };\r
32 \r
33 static pinmuxModuleCfg_t gCpsw9gPinCfg[] =\r
34 {\r
35 {0, TRUE, gCpsw9g0PinCfg},\r
36 {PINMUX_END}\r
37 };\r
38 \r
39 \r
40 static pinmuxPerCfg_t gGpio0PinCfg[] =\r
41 {\r
42 /* MyGPIO0 -> GPIO0_96 -> T23 */\r
43 {\r
44 PIN_RGMII5_RD0, PIN_MODE(7) | \\r
45 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
46 },\r
47 /* MyGPIO0 -> GPIO0_104 -> W26 */\r
48 {\r
49 PIN_RGMII6_RXC, PIN_MODE(7) | \\r
50 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
51 },\r
52 {PINMUX_END}\r
53 };\r
54 \r
55 static pinmuxModuleCfg_t gGpioPinCfg[] =\r
56 {\r
57 {0, TRUE, gGpio0PinCfg},\r
58 {PINMUX_END}\r
59 };\r
60 \r
61 \r
62 static pinmuxPerCfg_t gMdio0PinCfg[] =\r
63 {\r
64 /* MyMDIO1 -> MDIO0_MDC -> V24 */\r
65 {\r
66 PIN_MDIO0_MDC, PIN_MODE(0) | \\r
67 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
68 },\r
69 /* MyMDIO1 -> MDIO0_MDIO -> V26 */\r
70 {\r
71 PIN_MDIO0_MDIO, PIN_MODE(0) | \\r
72 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
73 },\r
74 {PINMUX_END}\r
75 };\r
76 \r
77 static pinmuxModuleCfg_t gMdioPinCfg[] =\r
78 {\r
79 {0, TRUE, gMdio0PinCfg},\r
80 {PINMUX_END}\r
81 };\r
82 \r
83 \r
84 static pinmuxPerCfg_t gRgmii3PinCfg[] =\r
85 {\r
86 /* MyRGMII3 -> RGMII3_RD0 -> AF28 */\r
87 {\r
88 PIN_PRG0_PRU0_GPO0, PIN_MODE(4) | \\r
89 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
90 },\r
91 /* MyRGMII3 -> RGMII3_RD1 -> AE28 */\r
92 {\r
93 PIN_PRG0_PRU0_GPO1, PIN_MODE(4) | \\r
94 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
95 },\r
96 /* MyRGMII3 -> RGMII3_RD2 -> AE27 */\r
97 {\r
98 PIN_PRG0_PRU0_GPO2, PIN_MODE(4) | \\r
99 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
100 },\r
101 /* MyRGMII3 -> RGMII3_RD3 -> AD26 */\r
102 {\r
103 PIN_PRG0_PRU0_GPO3, PIN_MODE(4) | \\r
104 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
105 },\r
106 /* MyRGMII3 -> RGMII3_RXC -> AE26 */\r
107 {\r
108 PIN_PRG0_PRU0_GPO6, PIN_MODE(4) | \\r
109 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
110 },\r
111 /* MyRGMII3 -> RGMII3_RX_CTL -> AD25 */\r
112 {\r
113 PIN_PRG0_PRU0_GPO4, PIN_MODE(4) | \\r
114 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
115 },\r
116 /* MyRGMII3 -> RGMII3_TD0 -> AJ28 */\r
117 {\r
118 PIN_PRG0_PRU0_GPO11, PIN_MODE(4) | \\r
119 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
120 },\r
121 /* MyRGMII3 -> RGMII3_TD1 -> AH27 */\r
122 {\r
123 PIN_PRG0_PRU0_GPO12, PIN_MODE(4) | \\r
124 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
125 },\r
126 /* MyRGMII3 -> RGMII3_TD2 -> AH29 */\r
127 {\r
128 PIN_PRG0_PRU0_GPO13, PIN_MODE(4) | \\r
129 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
130 },\r
131 /* MyRGMII3 -> RGMII3_TD3 -> AG28 */\r
132 {\r
133 PIN_PRG0_PRU0_GPO14, PIN_MODE(4) | \\r
134 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
135 },\r
136 /* MyRGMII3 -> RGMII3_TXC -> AH28 */\r
137 {\r
138 PIN_PRG0_PRU0_GPO16, PIN_MODE(4) | \\r
139 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
140 },\r
141 /* MyRGMII3 -> RGMII3_TX_CTL -> AG27 */\r
142 {\r
143 PIN_PRG0_PRU0_GPO15, PIN_MODE(4) | \\r
144 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
145 },\r
146 {PINMUX_END}\r
147 };\r
148 \r
149 static pinmuxPerCfg_t gRgmii4PinCfg[] =\r
150 {\r
151 /* MyRGMII4 -> RGMII4_RD0 -> AE29 */\r
152 {\r
153 PIN_PRG0_PRU1_GPO0, PIN_MODE(4) | \\r
154 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
155 },\r
156 /* MyRGMII4 -> RGMII4_RD1 -> AD28 */\r
157 {\r
158 PIN_PRG0_PRU1_GPO1, PIN_MODE(4) | \\r
159 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
160 },\r
161 /* MyRGMII4 -> RGMII4_RD2 -> AD27 */\r
162 {\r
163 PIN_PRG0_PRU1_GPO2, PIN_MODE(4) | \\r
164 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
165 },\r
166 /* MyRGMII4 -> RGMII4_RD3 -> AC25 */\r
167 {\r
168 PIN_PRG0_PRU1_GPO3, PIN_MODE(4) | \\r
169 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
170 },\r
171 /* MyRGMII4 -> RGMII4_RXC -> AC26 */\r
172 {\r
173 PIN_PRG0_PRU1_GPO6, PIN_MODE(4) | \\r
174 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
175 },\r
176 /* MyRGMII4 -> RGMII4_RX_CTL -> AD29 */\r
177 {\r
178 PIN_PRG0_PRU1_GPO4, PIN_MODE(4) | \\r
179 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
180 },\r
181 /* MyRGMII4 -> RGMII4_TD0 -> AG26 */\r
182 {\r
183 PIN_PRG0_PRU1_GPO11, PIN_MODE(4) | \\r
184 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
185 },\r
186 /* MyRGMII4 -> RGMII4_TD1 -> AF27 */\r
187 {\r
188 PIN_PRG0_PRU1_GPO12, PIN_MODE(4) | \\r
189 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
190 },\r
191 /* MyRGMII4 -> RGMII4_TD2 -> AF26 */\r
192 {\r
193 PIN_PRG0_PRU1_GPO13, PIN_MODE(4) | \\r
194 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
195 },\r
196 /* MyRGMII4 -> RGMII4_TD3 -> AE25 */\r
197 {\r
198 PIN_PRG0_PRU1_GPO14, PIN_MODE(4) | \\r
199 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
200 },\r
201 /* MyRGMII4 -> RGMII4_TXC -> AG29 */\r
202 {\r
203 PIN_PRG0_PRU1_GPO16, PIN_MODE(4) | \\r
204 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
205 },\r
206 /* MyRGMII4 -> RGMII4_TX_CTL -> AF29 */\r
207 {\r
208 PIN_PRG0_PRU1_GPO15, PIN_MODE(4) | \\r
209 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
210 },\r
211 {PINMUX_END}\r
212 };\r
213 \r
214 static pinmuxPerCfg_t gRgmii1PinCfg[] =\r
215 {\r
216 /* MyRGMII1 -> RGMII1_RD0 -> AC23 */\r
217 {\r
218 PIN_PRG1_PRU0_GPO0, PIN_MODE(4) | \\r
219 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
220 },\r
221 /* MyRGMII1 -> RGMII1_RD1 -> AG22 */\r
222 {\r
223 PIN_PRG1_PRU0_GPO1, PIN_MODE(4) | \\r
224 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
225 },\r
226 /* MyRGMII1 -> RGMII1_RD2 -> AF22 */\r
227 {\r
228 PIN_PRG1_PRU0_GPO2, PIN_MODE(4) | \\r
229 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
230 },\r
231 /* MyRGMII1 -> RGMII1_RD3 -> AJ23 */\r
232 {\r
233 PIN_PRG1_PRU0_GPO3, PIN_MODE(4) | \\r
234 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
235 },\r
236 /* MyRGMII1 -> RGMII1_RXC -> AD22 */\r
237 {\r
238 PIN_PRG1_PRU0_GPO6, PIN_MODE(4) | \\r
239 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
240 },\r
241 /* MyRGMII1 -> RGMII1_RX_CTL -> AH23 */\r
242 {\r
243 PIN_PRG1_PRU0_GPO4, PIN_MODE(4) | \\r
244 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
245 },\r
246 /* MyRGMII1 -> RGMII1_TD0 -> AF24 */\r
247 {\r
248 PIN_PRG1_PRU0_GPO11, PIN_MODE(4) | \\r
249 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
250 },\r
251 /* MyRGMII1 -> RGMII1_TD1 -> AJ24 */\r
252 {\r
253 PIN_PRG1_PRU0_GPO12, PIN_MODE(4) | \\r
254 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
255 },\r
256 /* MyRGMII1 -> RGMII1_TD2 -> AG24 */\r
257 {\r
258 PIN_PRG1_PRU0_GPO13, PIN_MODE(4) | \\r
259 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
260 },\r
261 /* MyRGMII1 -> RGMII1_TD3 -> AD24 */\r
262 {\r
263 PIN_PRG1_PRU0_GPO14, PIN_MODE(4) | \\r
264 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
265 },\r
266 /* MyRGMII1 -> RGMII1_TXC -> AE24 */\r
267 {\r
268 PIN_PRG1_PRU0_GPO16, PIN_MODE(4) | \\r
269 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
270 },\r
271 /* MyRGMII1 -> RGMII1_TX_CTL -> AC24 */\r
272 {\r
273 PIN_PRG1_PRU0_GPO15, PIN_MODE(4) | \\r
274 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
275 },\r
276 {PINMUX_END}\r
277 };\r
278 \r
279 static pinmuxPerCfg_t gRgmii2PinCfg[] =\r
280 {\r
281 /* MyRGMII2 -> RGMII2_RD0 -> AE22 */\r
282 {\r
283 PIN_PRG1_PRU1_GPO0, PIN_MODE(4) | \\r
284 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
285 },\r
286 /* MyRGMII2 -> RGMII2_RD1 -> AG23 */\r
287 {\r
288 PIN_PRG1_PRU1_GPO1, PIN_MODE(4) | \\r
289 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
290 },\r
291 /* MyRGMII2 -> RGMII2_RD2 -> AF23 */\r
292 {\r
293 PIN_PRG1_PRU1_GPO2, PIN_MODE(4) | \\r
294 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
295 },\r
296 /* MyRGMII2 -> RGMII2_RD3 -> AD23 */\r
297 {\r
298 PIN_PRG1_PRU1_GPO3, PIN_MODE(4) | \\r
299 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
300 },\r
301 /* MyRGMII2 -> RGMII2_RXC -> AE23 */\r
302 {\r
303 PIN_PRG1_PRU1_GPO6, PIN_MODE(4) | \\r
304 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
305 },\r
306 /* MyRGMII2 -> RGMII2_RX_CTL -> AH24 */\r
307 {\r
308 PIN_PRG1_PRU1_GPO4, PIN_MODE(4) | \\r
309 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
310 },\r
311 /* MyRGMII2 -> RGMII2_TD0 -> AJ25 */\r
312 {\r
313 PIN_PRG1_PRU1_GPO11, PIN_MODE(4) | \\r
314 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
315 },\r
316 /* MyRGMII2 -> RGMII2_TD1 -> AH25 */\r
317 {\r
318 PIN_PRG1_PRU1_GPO12, PIN_MODE(4) | \\r
319 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
320 },\r
321 /* MyRGMII2 -> RGMII2_TD2 -> AG25 */\r
322 {\r
323 PIN_PRG1_PRU1_GPO13, PIN_MODE(4) | \\r
324 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
325 },\r
326 /* MyRGMII2 -> RGMII2_TD3 -> AH26 */\r
327 {\r
328 PIN_PRG1_PRU1_GPO14, PIN_MODE(4) | \\r
329 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
330 },\r
331 /* MyRGMII2 -> RGMII2_TXC -> AJ26 */\r
332 {\r
333 PIN_PRG1_PRU1_GPO16, PIN_MODE(4) | \\r
334 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
335 },\r
336 /* MyRGMII2 -> RGMII2_TX_CTL -> AJ27 */\r
337 {\r
338 PIN_PRG1_PRU1_GPO15, PIN_MODE(4) | \\r
339 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
340 },\r
341 {PINMUX_END}\r
342 };\r
343 \r
344 static pinmuxModuleCfg_t gRgmiiPinCfg[] =\r
345 {\r
346 {3, TRUE, gRgmii3PinCfg},\r
347 {4, TRUE, gRgmii4PinCfg},\r
348 {1, TRUE, gRgmii1PinCfg},\r
349 {2, TRUE, gRgmii2PinCfg},\r
350 {PINMUX_END}\r
351 };\r
352 \r
353 \r
354 static pinmuxPerCfg_t gRmii8PinCfg[] =\r
355 {\r
356 /* MyRMII8 -> RMII8_CRS_DV -> Y28 */\r
357 {\r
358 PIN_RGMII6_TX_CTL, PIN_MODE(1) | \\r
359 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
360 },\r
361 /* MyRMII8 -> RMII8_RXD0 -> W25 */\r
362 {\r
363 PIN_RGMII6_RD0, PIN_MODE(1) | \\r
364 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
365 },\r
366 /* MyRMII8 -> RMII8_RXD1 -> W24 */\r
367 {\r
368 PIN_RGMII6_RD1, PIN_MODE(1) | \\r
369 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
370 },\r
371 /* MyRMII8 -> RMII8_RX_ER -> V23 */\r
372 {\r
373 PIN_RGMII6_RX_CTL, PIN_MODE(1) | \\r
374 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
375 },\r
376 /* MyRMII8 -> RMII8_TXD0 -> W27 */\r
377 {\r
378 PIN_RGMII6_TD0, PIN_MODE(1) | \\r
379 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
380 },\r
381 /* MyRMII8 -> RMII8_TXD1 -> V25 */\r
382 {\r
383 PIN_RGMII6_TD1, PIN_MODE(1) | \\r
384 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
385 },\r
386 /* MyRMII8 -> RMII8_TX_EN -> W29 */\r
387 {\r
388 PIN_RGMII6_TXC, PIN_MODE(1) | \\r
389 ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
390 },\r
391 {PINMUX_END}\r
392 };\r
393 \r
394 static pinmuxPerCfg_t gRmii0PinCfg[] =\r
395 {\r
396 /* MyRMII0 -> RMII_REF_CLK -> AD18 */\r
397 {\r
398 PIN_PRG1_MDIO0_MDC, PIN_MODE(5) | \\r
399 ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))\r
400 },\r
401 {PINMUX_END}\r
402 };\r
403 \r
404 static pinmuxModuleCfg_t gRmiiPinCfg[] =\r
405 {\r
406 {8, TRUE, gRmii8PinCfg},\r
407 {0, TRUE, gRmii0PinCfg},\r
408 {PINMUX_END}\r
409 };\r
410 \r
411 \r
412 pinmuxBoardCfg_t gAM7xMainPinmuxDataGesiCpsw9g[] =\r
413 {\r
414 {0, gCpsw9gPinCfg},\r
415 {1, gGpioPinCfg},\r
416 {2, gMdioPinCfg},\r
417 {3, gRgmiiPinCfg},\r
418 {4, gRmiiPinCfg},\r
419 {PINMUX_END}\r
420 };\r
421 \r
422 pinmuxBoardCfg_t gAM7xWkupPinmuxDataGesiCpsw9g[] =\r
423 {\r
424 {PINMUX_END}\r
425 };\r