1 /******************************************************************************\r
2 * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com\r
3 *\r
4 * Redistribution and use in source and binary forms, with or without\r
5 * modification, are permitted provided that the following conditions\r
6 * are met:\r
7 *\r
8 * Redistributions of source code must retain the above copyright\r
9 * notice, this list of conditions and the following disclaimer.\r
10 *\r
11 * Redistributions in binary form must reproduce the above copyright\r
12 * notice, this list of conditions and the following disclaimer in the\r
13 * documentation and/or other materials provided with the\r
14 * distribution.\r
15 *\r
16 * Neither the name of Texas Instruments Incorporated nor the names of\r
17 * its contributors may be used to endorse or promote products derived\r
18 * from this software without specific prior written permission.\r
19 *\r
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
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30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
31 *\r
32 *****************************************************************************/\r
33 \r
34 /** \r
35 * \file board_pinmux.c\r
36 *\r
37 * \brief This file enables pinmux for the board \r
38 *\r
39 */\r
40 \r
41 #include <ti/csl/soc.h>\r
42 #include "board_internal.h"\r
43 #include "board_pinmux.h"\r
44 \r
45 static Board_PinmuxConfig_t gBoardPinmuxCfg = {BOARD_PINMUX_CUSTOM,\r
46 BOARD_PINMUX_INFO_VOUT,\r
47 BOARD_PINMUX_CSI_COMMON,\r
48 BOARD_PINMUX_ENET_QSGMII};\r
49 \r
50 /**\r
51 * \brief Gets base address of padconfig registers\r
52 *\r
53 * \param domain [IN] SoC domain for pinmux\r
54 * \n BOARD_SOC_DOMAIN_MAIN - Main domain\r
55 * \n BOARD_SOC_DOMAIN_WKUP - Wakeup domain\r
56 *\r
57 * \return Valid address in case success or 0 in case of failure\r
58 */\r
59 static void Board_pinmuxWriteProxy1Reg(uint8_t domain,\r
60 uint32_t baseAddr,\r
61 uint32_t regVal)\r
62 {\r
63 uint32_t claimAddr;\r
64 uint32_t claimOffset;\r
65 uint32_t claimShift;\r
66 uint32_t claimRegVal;\r
67 \r
68 if(domain == BOARD_SOC_DOMAIN_MAIN)\r
69 {\r
70 claimAddr = BOARD_MAIN_MMR_P7_CLAIM_ADDR;\r
71 /* Get the register offset from base of P7 claim offset range */\r
72 claimOffset = (baseAddr - BOARD_MAIN_PMUX_CTRL_ADDR);\r
73 }\r
74 else\r
75 {\r
76 claimAddr = BOARD_WKUP_MMR_P7_CLAIM_ADDR;\r
77 /* Get the register offset from base of P7 claim offset range */\r
78 claimOffset = (baseAddr - BOARD_WKUP_PMUX_CTRL_ADDR);\r
79 }\r
80 \r
81 /* Each claim register configures 128 byte address range.\r
82 Calculate the register offset for P7 claim register block and\r
83 and shift values within the claim register */\r
84 claimShift = claimOffset % BOARD_MMR_CLAIM_ADDR_PER_REG;\r
85 claimOffset = claimOffset / BOARD_MMR_CLAIM_ADDR_PER_REG;\r
86 \r
87 claimRegVal = HW_RD_REG32((claimAddr + 4*claimOffset));\r
88 claimRegVal |= (1 << claimShift);\r
89 \r
90 /* Claim the register access */\r
91 HW_WR_REG32((claimAddr + 4*claimOffset), claimRegVal);\r
92 \r
93 /* Write PAD config MMR register */\r
94 HW_WR_REG32(baseAddr, regVal);\r
95 }\r
96 \r
97 /**\r
98 * \brief Gets base address of padconfig registers\r
99 *\r
100 * \param domain [IN] SoC domain for pinmux\r
101 * \n BOARD_SOC_DOMAIN_MAIN - Main domain\r
102 * \n BOARD_SOC_DOMAIN_WKUP - Wakeup domain\r
103 *\r
104 * \return Valid address in case success or 0 in case of failure\r
105 */\r
106 static uint32_t Board_pinmuxGetBaseAddr(uint8_t domain)\r
107 {\r
108 uint32_t baseAddr;\r
109 \r
110 switch(domain)\r
111 {\r
112 case BOARD_SOC_DOMAIN_MAIN:\r
113 baseAddr = BOARD_MAIN_PMUX_CTRL_ADDR;\r
114 break;\r
115 case BOARD_SOC_DOMAIN_WKUP:\r
116 baseAddr = BOARD_WKUP_PMUX_CTRL_ADDR;\r
117 break;\r
118 default:\r
119 baseAddr = 0;\r
120 break;\r
121 }\r
122 \r
123 return baseAddr;\r
124 }\r
125 \r
126 #if defined (_TMS320C6X)\r
127 /**\r
128 * \brief Sets RAT configuration for C66x core\r
129 *\r
130 * MAIN padconfig registers are not directly accessible for C66x core\r
131 * which requires RAT configuration for the access.\r
132 *\r
133 * \return None\r
134 */\r
135 static void Board_setC66xRATCfg(void)\r
136 {\r
137 HW_WR_REG32((CSL_C66_COREPAC_C66_RATCFG_BASE + 0x24),\r
138 BOARD_PINMUX_C66X_RAT_OFFSET);\r
139 HW_WR_REG32((CSL_C66_COREPAC_C66_RATCFG_BASE + 0x28), 0);\r
140 HW_WR_REG32((CSL_C66_COREPAC_C66_RATCFG_BASE + 0x20), \r
141 BOARD_PINMUX_C66X_RAT_CONFIG);\r
142 }\r
143 \r
144 /**\r
145 * \brief Clears RAT configuration for C66x core\r
146 *\r
147 * \return None\r
148 */\r
149 static void Board_clearC66xRATCfg(void)\r
150 {\r
151 HW_WR_REG32((CSL_C66_COREPAC_C66_RATCFG_BASE + 0x20), 0);\r
152 HW_WR_REG32((CSL_C66_COREPAC_C66_RATCFG_BASE + 0x24), 0);\r
153 HW_WR_REG32((CSL_C66_COREPAC_C66_RATCFG_BASE + 0x28), 0);\r
154 }\r
155 #endif /* #if defined (_TMS320C6X) */\r
156 \r
157 /**\r
158 * \brief Sets pinmux mode for a pin in main domain\r
159 *\r
160 * Only pinmux mode is updated by this function. Other values of\r
161 * padconfig register remains unchanged after this function call.\r
162 *\r
163 * \param offset [IN] Pad config offset of the pin\r
164 * \param mode [IN] Pad config mux mode.\r
165 *\r
166 * \return None\r
167 */\r
168 void Board_pinMuxSetMode(uint32_t offset, uint32_t mode)\r
169 {\r
170 uint32_t baseAddr;\r
171 uint32_t regVal;\r
172 \r
173 Board_unlockMMR();\r
174 \r
175 baseAddr = Board_pinmuxGetBaseAddr(BOARD_SOC_DOMAIN_MAIN);\r
176 \r
177 regVal = HW_RD_REG32((baseAddr + offset));\r
178 regVal &= ~(BOARD_MODE_PIN_MASK);\r
179 mode &= BOARD_MODE_PIN_MASK;\r
180 regVal |= mode;\r
181 Board_pinmuxWriteProxy1Reg(BOARD_SOC_DOMAIN_MAIN, \r
182 (baseAddr + offset), \r
183 regVal);\r
184 }\r
185 \r
186 /**\r
187 * \brief Sets pinmux mode for a pin in wake-up domain\r
188 *\r
189 * Only pinmux mode is updated by this function. Other values of\r
190 * padconfig register remains unchanged after this function call.\r
191 *\r
192 * \param offset [IN] Pad config offset of the pin\r
193 * \param mode [IN] Pad config mux mode.\r
194 *\r
195 * \return None\r
196 */\r
197 void Board_pinMuxSetModeWkup(uint32_t offset, uint32_t mode)\r
198 {\r
199 uint32_t baseAddr;\r
200 uint32_t regVal;\r
201 \r
202 Board_unlockMMR();\r
203 \r
204 baseAddr = Board_pinmuxGetBaseAddr(BOARD_SOC_DOMAIN_WKUP);\r
205 \r
206 regVal = HW_RD_REG32((baseAddr + offset));\r
207 regVal &= ~(BOARD_MODE_PIN_MASK);\r
208 mode &= BOARD_MODE_PIN_MASK;\r
209 regVal |= mode;\r
210 Board_pinmuxWriteProxy1Reg(BOARD_SOC_DOMAIN_WKUP, \r
211 (baseAddr + offset), \r
212 regVal);\r
213 }\r
214 \r
215 /**\r
216 * \brief Sets padconfig register of a pin at given offset\r
217 *\r
218 * Configures whole padconfig register of the pin at given offset\r
219 * with the value in 'muxData'.\r
220 *\r
221 * \param domain [IN] SoC domain for pinmux\r
222 * \n BOARD_SOC_DOMAIN_MAIN - Main domain\r
223 * \n BOARD_SOC_DOMAIN_WKUP - Wakeup domain\r
224 *\r
225 * \param offset [IN] Pad config offset of the pin\r
226 * \param muxData [IN] Value to be written to padconfig register\r
227 *\r
228 * \return BOARD_SOK in case of success or appropriate error code\r
229 *\r
230 */\r
231 Board_STATUS Board_pinmuxSetReg(uint8_t domain,\r
232 uint32_t offset,\r
233 uint32_t muxData)\r
234 {\r
235 uint32_t baseAddr;\r
236 Board_STATUS status = BOARD_SOK;\r
237 \r
238 Board_unlockMMR();\r
239 \r
240 baseAddr = Board_pinmuxGetBaseAddr(domain);\r
241 if(baseAddr != 0)\r
242 {\r
243 Board_pinmuxWriteProxy1Reg(domain, \r
244 (baseAddr + offset), \r
245 muxData);\r
246 }\r
247 else\r
248 {\r
249 status = BOARD_INVALID_PARAM;\r
250 }\r
251 \r
252 return status;\r
253 }\r
254 \r
255 /**\r
256 * \brief Gets padconfig register of a pin at given offset\r
257 *\r
258 * \param domain [IN] SoC domain for pinmux\r
259 * \n BOARD_SOC_DOMAIN_MAIN - Main domain\r
260 * \n BOARD_SOC_DOMAIN_WKUP - Wakeup domain\r
261 * \param offset [IN] Pad config offset of the pin\r
262 * \param muxData [OUT] Value of padconfig register\r
263 *\r
264 * \return BOARD_SOK in case of success or appropriate error code\r
265 *\r
266 */\r
267 Board_STATUS Board_pinmuxGetReg(uint8_t domain,\r
268 uint32_t offset,\r
269 uint32_t *muxData)\r
270 {\r
271 uint32_t baseAddr;\r
272 Board_STATUS status = BOARD_SOK;\r
273 \r
274 baseAddr = Board_pinmuxGetBaseAddr(domain);\r
275 if(baseAddr != 0)\r
276 {\r
277 *muxData = HW_RD_REG32((baseAddr + offset));\r
278 }\r
279 else\r
280 {\r
281 status = BOARD_INVALID_PARAM;\r
282 }\r
283 \r
284 return status;\r
285 }\r
286 \r
287 /**\r
288 * \brief Sets the board pinmux configuration.\r
289 *\r
290 * There are multiple addon cards that can connected to baseboard and\r
291 * multiple addon cards can be connected to one expansion connector.\r
292 * Pinmux configured through Board_init will be set to a default\r
293 * combination of the boards which can be changed using this function.\r
294 *\r
295 * \n Usage:\r
296 * \n - Call Board_pinmuxGetCfg to get default pinmux config\r
297 * \n - Call Board_pinmuxSetCfg to change pinmux config\r
298 * \n - Call Board_init with pinmux flag to apply the updated pinmux config\r
299 *\r
300 * \param pinmuxCfg [IN] Pinmux configurations\r
301 *\r
302 * \return BOARD_SOK in case of success or appropriate error code\r
303 *\r
304 */\r
305 Board_STATUS Board_pinmuxSetCfg(Board_PinmuxConfig_t *pinmuxCfg)\r
306 {\r
307 gBoardPinmuxCfg = *pinmuxCfg;\r
308 \r
309 return BOARD_SOK;\r
310 }\r
311 \r
312 /**\r
313 * \brief Gets the board pinmux configuration.\r
314 *\r
315 * There are multiple addon cards that can connected to baseboard and\r
316 * multiple addon cards can be connected to one expansion connector.\r
317 * Pinmux configured through Board_init will be set to a default\r
318 * combination of the boards which can be read using this function.\r
319 *\r
320 * \param pinmuxCfg [IN] Pinmux configurations\r
321 *\r
322 * \return BOARD_SOK in case of success or appropriate error code\r
323 *\r
324 */\r
325 Board_STATUS Board_pinmuxGetCfg(Board_PinmuxConfig_t *pinmuxCfg)\r
326 {\r
327 *pinmuxCfg = gBoardPinmuxCfg;\r
328 \r
329 return BOARD_SOK;\r
330 }\r
331 \r
332 /**\r
333 * \brief Board pinmuxing update function\r
334 *\r
335 * Provides the option to configure/update the pinmux.\r
336 * This function can be used to change the pinmux set by\r
337 * Board_init by default.\r
338 *\r
339 * \param pinmuxData [IN] Pinmux data structure\r
340 * \param domain [IN] SoC domain for pinmux\r
341 * \n BOARD_SOC_DOMAIN_MAIN - Main domain\r
342 * \n BOARD_SOC_DOMAIN_WKUP - Wakeup domain\r
343 *\r
344 * \return BOARD_SOK in case of success or appropriate error code\r
345 *\r
346 */\r
347 Board_STATUS Board_pinmuxUpdate (pinmuxBoardCfg_t *pinmuxData,\r
348 uint32_t domain)\r
349 {\r
350 pinmuxModuleCfg_t *pModuleData = NULL;\r
351 pinmuxPerCfg_t *pInstanceData = NULL;\r
352 int32_t i, j, k;\r
353 uint32_t rdRegVal;\r
354 uint32_t baseAddr;\r
355 Board_STATUS status = BOARD_SOK;\r
356 \r
357 Board_unlockMMR();\r
358 \r
359 #if defined (_TMS320C6X)\r
360 /* MAIN domain pinmux needs RAT configuration for C66x core. */\r
361 if(domain == BOARD_SOC_DOMAIN_MAIN)\r
362 {\r
363 Board_setC66xRATCfg();\r
364 }\r
365 #endif\r
366 \r
367 baseAddr = Board_pinmuxGetBaseAddr(domain);\r
368 if(baseAddr != 0)\r
369 {\r
370 for(i = 0; PINMUX_END != pinmuxData[i].moduleId; i++)\r
371 {\r
372 pModuleData = pinmuxData[i].modulePinCfg;\r
373 for(j = 0; (PINMUX_END != pModuleData[j].modInstNum); j++)\r
374 {\r
375 if(pModuleData[j].doPinConfig == TRUE)\r
376 {\r
377 pInstanceData = pModuleData[j].instPins;\r
378 for(k = 0; (PINMUX_END != pInstanceData[k].pinOffset); k++)\r
379 {\r
380 rdRegVal = HW_RD_REG32((baseAddr + pInstanceData[k].pinOffset));\r
381 rdRegVal = (rdRegVal & BOARD_PINMUX_BIT_MASK);\r
382 Board_pinmuxWriteProxy1Reg(domain, \r
383 (baseAddr + pInstanceData[k].pinOffset), \r
384 (pInstanceData[k].pinSettings));\r
385 }\r
386 }\r
387 }\r
388 }\r
389 }\r
390 else\r
391 {\r
392 status = BOARD_INVALID_PARAM;\r
393 }\r
394 \r
395 #if defined (_TMS320C6X)\r
396 if(domain == BOARD_SOC_DOMAIN_MAIN)\r
397 {\r
398 /* Clear the RAT configuration to allow applications to use the region */\r
399 Board_clearC66xRATCfg();\r
400 }\r
401 #endif\r
402 \r
403 return status;\r
404 }\r
405 \r
406 /**\r
407 * \brief Board pinmuxing enable function\r
408 *\r
409 * Enables pinmux for the board interfaces. Pin mux is done based\r
410 * on the default/primary functionality of the board. Any pins shared by\r
411 * multiple interfaces need to be reconfigured to access the secondary\r
412 * functionality.\r
413 *\r
414 * \param void\r
415 *\r
416 * \return BOARD_SOK in case of success or appropriate error code\r
417 *\r
418 */\r
419 Board_STATUS Board_pinmuxConfig (void)\r
420 {\r
421 Board_STATUS status = BOARD_SOK;\r
422 uint32_t i2cPinmux;\r
423 \r
424 Board_pinmuxUpdate(gAM7xMainPinmuxData,\r
425 BOARD_SOC_DOMAIN_MAIN);\r
426 Board_pinmuxUpdate(gAM7xWkupPinmuxData,\r
427 BOARD_SOC_DOMAIN_WKUP);\r
428 \r
429 if(gBoardPinmuxCfg.autoCfg)\r
430 {\r
431 /* Enable pinmux for board ID I2C */\r
432 i2cPinmux = PIN_MODE(0) | \r
433 ((PIN_PULL_DIRECTION | \r
434 PIN_INPUT_ENABLE) & \r
435 (~PIN_PULL_DISABLE));\r
436 Board_pinmuxSetReg(BOARD_SOC_DOMAIN_WKUP, PIN_WKUP_I2C0_SCL, i2cPinmux);\r
437 Board_pinmuxSetReg(BOARD_SOC_DOMAIN_WKUP, PIN_WKUP_I2C0_SDA, i2cPinmux);\r
438 \r
439 if(Board_detectBoard(BOARD_ID_GESI) == TRUE)\r
440 {\r
441 gBoardPinmuxCfg.gesiExp = BOARD_PINMUX_GESI_ICSSG;\r
442 }\r
443 else\r
444 {\r
445 if(Board_detectBoard(BOARD_ID_INFOTAINMENT) == TRUE)\r
446 {\r
447 gBoardPinmuxCfg.gesiExp = BOARD_PINMUX_INFO_VOUT;\r
448 }\r
449 }\r
450 }\r
451 \r
452 if((gBoardPinmuxCfg.gesiExp == BOARD_PINMUX_GESI_ICSSG) ||\r
453 (gBoardPinmuxCfg.gesiExp == BOARD_PINMUX_GESI_CPSW9G))\r
454 {\r
455 /* By default ICSSG RGMII is enabled */\r
456 Board_pinmuxUpdate(gAM7xMainPinmuxDataGesiIcssg,\r
457 BOARD_SOC_DOMAIN_MAIN);\r
458 Board_pinmuxUpdate(gAM7xWkupPinmuxDataGesiIcssg,\r
459 BOARD_SOC_DOMAIN_WKUP);\r
460 \r
461 if(gBoardPinmuxCfg.gesiExp == BOARD_PINMUX_GESI_CPSW9G)\r
462 {\r
463 /* Overwrite the ICSSG RGMII muc configurations with CPSW9G RGMII */\r
464 Board_pinmuxUpdate(gAM7xMainPinmuxDataGesiCpsw9g,\r
465 BOARD_SOC_DOMAIN_MAIN);\r
466 Board_pinmuxUpdate(gAM7xWkupPinmuxDataGesiCpsw9g,\r
467 BOARD_SOC_DOMAIN_WKUP);\r
468 }\r
469 }\r
470 else if(gBoardPinmuxCfg.gesiExp == BOARD_PINMUX_INFO_VOUT)\r
471 {\r
472 Board_pinmuxUpdate(gAM7xMainPinmuxDataInfo,\r
473 BOARD_SOC_DOMAIN_MAIN);\r
474 Board_pinmuxUpdate(gAM7xWkupPinmuxDataInfo,\r
475 BOARD_SOC_DOMAIN_WKUP);\r
476 }\r
477 else\r
478 {\r
479 return (BOARD_INVALID_PARAM);\r
480 }\r
481 \r
482 if(gBoardPinmuxCfg.fssCfg == BOARD_PINMUX_FSS_HPB)\r
483 {\r
484 Board_pinmuxUpdate(gAM7xWkupPinmuxDataHpb,\r
485 BOARD_SOC_DOMAIN_WKUP);\r
486 }\r
487 \r
488 return status;\r
489 }\r