53ccac2dbfe2988ca8ee30315a039839ad812dc4
1 /******************************************************************************\r
2 * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com\r
3 *\r
4 * Redistribution and use in source and binary forms, with or without\r
5 * modification, are permitted provided that the following conditions\r
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11 * Redistributions in binary form must reproduce the above copyright\r
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32 *****************************************************************************/\r
33 /**\r
34 * \file board_cfg.c\r
35 *\r
36 * \brief EVM serdes configuration file\r
37 *\r
38 * Configures the serdes module.\r
39 *\r
40 */\r
41 \r
42 #include "board_serdes_cfg.h"\r
43 \r
44 static Board_STATUS Board_serdesInitParams(CSL_SerdesLaneEnableParams *laneParams,\r
45 uint32_t phyType)\r
46 {\r
47 laneParams->serdesInstance = (CSL_SerdesInstance)BOARD_SERDES_INSTANCE;\r
48 laneParams->baseAddr = CSL_SERDES_10G1_BASE;\r
49 laneParams->refClock = CSL_SERDES_REF_CLOCK_100M;\r
50 laneParams->refClkSrc = CSL_SERDES_REF_CLOCK_INT;\r
51 laneParams->numLanes = 0x4;\r
52 laneParams->laneMask = 0xf;\r
53 laneParams->SSC_mode = CSL_SERDES_NO_SSC;\r
54 laneParams->phyType = phyType;\r
55 laneParams->operatingMode = CSL_SERDES_FUNCTIONAL_MODE;\r
56 laneParams->phyInstanceNum = SERDES_LANE_SELECT_CPSW;\r
57 \r
58 laneParams->laneCtrlRate[0] = CSL_SERDES_LANE_FULL_RATE;\r
59 laneParams->loopbackMode[0] = CSL_SERDES_LOOPBACK_DISABLED;\r
60 \r
61 laneParams->laneCtrlRate[1] = CSL_SERDES_LANE_FULL_RATE;\r
62 laneParams->loopbackMode[1] = CSL_SERDES_LOOPBACK_DISABLED;\r
63 \r
64 if(phyType == CSL_SERDES_PHY_TYPE_SGMII)\r
65 {\r
66 laneParams->pcieGenType = CSL_SERDES_PCIE_GEN3;\r
67 laneParams->linkRate = CSL_SERDES_LINK_RATE_1p25G;\r
68 }\r
69 else if (phyType == CSL_SERDES_PHY_TYPE_QSGMII)\r
70 {\r
71 laneParams->pcieGenType = CSL_SERDES_PCIE_GEN4;\r
72 laneParams->linkRate = CSL_SERDES_LINK_RATE_5G;\r
73 }\r
74 else\r
75 {\r
76 /* Unsupported phy type */\r
77 return BOARD_FAIL;\r
78 }\r
79 \r
80 return BOARD_SOK;\r
81 }\r
82 \r
83 static Board_STATUS Board_serdesCfgEthernet(uint32_t phyType)\r
84 {\r
85 CSL_SerdesResult result;\r
86 CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
87 CSL_SerdesLaneEnableParams serdesLane0EnableParams = {0};\r
88 \r
89 memset(&serdesLane0EnableParams, 0, sizeof(serdesLane0EnableParams));\r
90 \r
91 Board_serdesInitParams(&serdesLane0EnableParams, phyType);\r
92 \r
93 CSL_serdesPorReset(serdesLane0EnableParams.baseAddr);\r
94 \r
95 /* Select the IP type, IP instance num, Serdes Lane Number */\r
96 CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,\r
97 serdesLane0EnableParams.phyType,\r
98 serdesLane0EnableParams.phyInstanceNum,\r
99 serdesLane0EnableParams.serdesInstance,\r
100 BOARD_SERDES_SGMII_LANE_NUM);\r
101 \r
102 result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,\r
103 serdesLane0EnableParams.baseAddr,\r
104 serdesLane0EnableParams.refClock,\r
105 serdesLane0EnableParams.refClkSrc,\r
106 serdesLane0EnableParams.serdesInstance,\r
107 serdesLane0EnableParams.phyType);\r
108 \r
109 if (result != CSL_SERDES_NO_ERR)\r
110 {\r
111 return BOARD_FAIL;\r
112 }\r
113 \r
114 /* Assert PHY reset and disable all lanes */\r
115 CSL_serdesDisablePllAndLanes(serdesLane0EnableParams.baseAddr, serdesLane0EnableParams.numLanes, serdesLane0EnableParams.laneMask);\r
116 \r
117 /* Load the Serdes Config File */\r
118 result = CSL_serdesEthernetInit(&serdesLane0EnableParams);\r
119 /* Return error if input params are invalid */\r
120 if (result != CSL_SERDES_NO_ERR)\r
121 {\r
122 return BOARD_FAIL;\r
123 }\r
124 \r
125 /* Common Lane Enable API for lane enable, pll enable etc */\r
126 laneRetVal = CSL_serdesLaneEnable(&serdesLane0EnableParams);\r
127 if (laneRetVal != 0)\r
128 {\r
129 return BOARD_FAIL;\r
130 }\r
131 \r
132 return BOARD_SOK;\r
133 }\r
134 \r
135 /**\r
136 * \brief serdes configurations\r
137 *\r
138 * The function configures the serdes1 module for one lane pcie interface\r
139 *\r
140 * \return BOARD_SOK in case of success or appropriate error code\r
141 *\r
142 */\r
143 Board_STATUS Board_serdesCfgSgmii(void)\r
144 {\r
145 Board_STATUS ret;\r
146 \r
147 /* SERDES0 Initializations */\r
148 ret = Board_serdesCfgEthernet(CSL_SERDES_PHY_TYPE_SGMII);\r
149 if(ret != BOARD_SOK)\r
150 {\r
151 return ret;\r
152 }\r
153 \r
154 return BOARD_SOK;\r
155 }\r
156 \r
157 /**\r
158 * \brief serdes configurations\r
159 *\r
160 * The function configures the serdes1 module for one lane pcie interface\r
161 *\r
162 * \return BOARD_SOK in case of success or appropriate error code\r
163 *\r
164 */\r
165 Board_STATUS Board_serdesCfgQsgmii(void)\r
166 {\r
167 Board_STATUS ret;\r
168 \r
169 /* SERDES0 Initializations */\r
170 ret = Board_serdesCfgEthernet(CSL_SERDES_PHY_TYPE_QSGMII);\r
171 if(ret != BOARD_SOK)\r
172 {\r
173 return ret;\r
174 }\r
175 \r
176 return BOARD_SOK;\r
177 }\r