1 /******************************************************************************\r
2 * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com\r
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32 *****************************************************************************/\r
33 /**\r
34 * \file board_cfg.c\r
35 *\r
36 * \brief EVM serdes configuration file\r
37 *\r
38 * Configures the serdes module.\r
39 *\r
40 */\r
41 \r
42 #include "board_serdes_cfg.h"\r
43 \r
44 static Board_STATUS Board_serdesInitParams(CSL_SerdesLaneEnableParams *laneParams,\r
45 uint32_t phyType)\r
46 {\r
47 laneParams->serdesInstance = (CSL_SerdesInstance)BOARD_SERDES_INSTANCE;\r
48 laneParams->baseAddr = CSL_SERDES_10G1_BASE;\r
49 laneParams->refClock = CSL_SERDES_REF_CLOCK_100M;\r
50 laneParams->refClkSrc = CSL_SERDES_REF_CLOCK_INT;\r
51 laneParams->numLanes = 0x4;\r
52 laneParams->laneMask = 0xf;\r
53 laneParams->SSC_mode = CSL_SERDES_NO_SSC;\r
54 laneParams->phyType = phyType;\r
55 laneParams->operatingMode = CSL_SERDES_FUNCTIONAL_MODE;\r
56 laneParams->phyInstanceNum = SERDES_LANE_SELECT_CPSW;\r
57 \r
58 laneParams->laneCtrlRate[0] = CSL_SERDES_LANE_FULL_RATE;\r
59 laneParams->loopbackMode[0] = CSL_SERDES_LOOPBACK_DISABLED;\r
60 \r
61 laneParams->laneCtrlRate[1] = CSL_SERDES_LANE_FULL_RATE;\r
62 laneParams->loopbackMode[1] = CSL_SERDES_LOOPBACK_DISABLED;\r
63 \r
64 if(phyType == CSL_SERDES_PHY_TYPE_SGMII)\r
65 {\r
66 laneParams->pcieGenType = CSL_SERDES_PCIE_GEN3;\r
67 laneParams->linkRate = CSL_SERDES_LINK_RATE_1p25G;\r
68 }\r
69 else if (phyType == CSL_SERDES_PHY_TYPE_QSGMII)\r
70 {\r
71 laneParams->pcieGenType = CSL_SERDES_PCIE_GEN4;\r
72 laneParams->linkRate = CSL_SERDES_LINK_RATE_5G;\r
73 }\r
74 else\r
75 {\r
76 /* Unsupported phy type */\r
77 return BOARD_FAIL;\r
78 }\r
79 \r
80 return BOARD_SOK;\r
81 }\r
82 \r
83 static Board_STATUS Board_serdesCfgEthernet(uint32_t phyType)\r
84 {\r
85 CSL_SerdesStatus status;\r
86 CSL_SerdesResult result;\r
87 CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
88 CSL_SerdesLaneEnableParams serdesLane0EnableParams = {0};\r
89 \r
90 memset(&serdesLane0EnableParams, 0, sizeof(serdesLane0EnableParams));\r
91 \r
92 Board_serdesInitParams(&serdesLane0EnableParams, phyType);\r
93 \r
94 /* Bail out early if SERDES is already configured */\r
95 status = CSL_serdesConfigStatus(serdesLane0EnableParams.baseAddr);\r
96 if (status == 1U)\r
97 {\r
98 return BOARD_SOK;\r
99 }\r
100 \r
101 CSL_serdesPorReset(serdesLane0EnableParams.baseAddr);\r
102 \r
103 /* Select the IP type, IP instance num, Serdes Lane Number */\r
104 CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,\r
105 serdesLane0EnableParams.phyType,\r
106 serdesLane0EnableParams.phyInstanceNum,\r
107 serdesLane0EnableParams.serdesInstance,\r
108 BOARD_SERDES_SGMII_LANE_NUM);\r
109 \r
110 result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,\r
111 serdesLane0EnableParams.baseAddr,\r
112 serdesLane0EnableParams.refClock,\r
113 serdesLane0EnableParams.refClkSrc,\r
114 serdesLane0EnableParams.serdesInstance,\r
115 serdesLane0EnableParams.phyType);\r
116 \r
117 if (result != CSL_SERDES_NO_ERR)\r
118 {\r
119 return BOARD_FAIL;\r
120 }\r
121 \r
122 /* Assert PHY reset and disable all lanes */\r
123 CSL_serdesDisablePllAndLanes(serdesLane0EnableParams.baseAddr, serdesLane0EnableParams.numLanes, serdesLane0EnableParams.laneMask);\r
124 \r
125 /* Load the Serdes Config File */\r
126 result = CSL_serdesEthernetInit(&serdesLane0EnableParams);\r
127 /* Return error if input params are invalid */\r
128 if (result != CSL_SERDES_NO_ERR)\r
129 {\r
130 return BOARD_FAIL;\r
131 }\r
132 \r
133 /* Common Lane Enable API for lane enable, pll enable etc */\r
134 laneRetVal = CSL_serdesLaneEnable(&serdesLane0EnableParams);\r
135 if (laneRetVal != 0)\r
136 {\r
137 return BOARD_FAIL;\r
138 }\r
139 \r
140 return BOARD_SOK;\r
141 }\r
142 \r
143 static Board_STATUS Board_serdesCfgEthernetUsxgmii(void)\r
144 {\r
145 CSL_SerdesStatus status;\r
146 CSL_SerdesResult result;\r
147 CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
148 CSL_SerdesLaneEnableParams laneParams_serdes0;\r
149 \r
150 memset(&laneParams_serdes0, 0, sizeof(laneParams_serdes0));\r
151 \r
152 /* Serdes-0: Lanes 2 and 3 (Ports 0 and 1 resp.) */\r
153 laneParams_serdes0.serdesInstance = (CSL_SerdesInstance)CSL_TORRENT_SERDES0;\r
154 laneParams_serdes0.baseAddr = CSL_SERDES_10G1_BASE;\r
155 laneParams_serdes0.refClock = CSL_SERDES_REF_CLOCK_100M;\r
156 laneParams_serdes0.refClkSrc = CSL_SERDES_REF_CLOCK_INT;\r
157 laneParams_serdes0.numLanes = 0x1;\r
158 laneParams_serdes0.laneMask = 0x4;\r
159 laneParams_serdes0.SSC_mode = CSL_SERDES_NO_SSC;\r
160 laneParams_serdes0.phyType = CSL_SERDES_PHY_TYPE_USXGMII;\r
161 laneParams_serdes0.operatingMode = CSL_SERDES_FUNCTIONAL_MODE;\r
162 laneParams_serdes0.phyInstanceNum = SERDES_LANE_SELECT_CPSW;\r
163 \r
164 laneParams_serdes0.laneCtrlRate[2] = CSL_SERDES_LANE_FULL_RATE;\r
165 laneParams_serdes0.loopbackMode[2] = CSL_SERDES_LOOPBACK_DISABLED;\r
166 \r
167 laneParams_serdes0.laneCtrlRate[3] = CSL_SERDES_LANE_FULL_RATE;\r
168 laneParams_serdes0.loopbackMode[3] = CSL_SERDES_LOOPBACK_DISABLED;\r
169 \r
170 laneParams_serdes0.pcieGenType = CSL_SERDES_PCIE_GEN3;\r
171 laneParams_serdes0.linkRate = CSL_SERDES_LINK_RATE_5p15625G;\r
172 /* End: Serdes-0: Lanes 2 and 3 (MAC Ports 0 and 1) */\r
173 \r
174 /* Bail out early if SERDES is already configured */\r
175 status = CSL_serdesConfigStatus(laneParams_serdes0.baseAddr);\r
176 if (status == 1U)\r
177 {\r
178 return BOARD_SOK;\r
179 }\r
180 \r
181 CSL_serdesPorReset(laneParams_serdes0.baseAddr);\r
182 \r
183 /* Select the IP type, IP instance num, Serdes Lane Number */\r
184 CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,\r
185 laneParams_serdes0.phyType,\r
186 laneParams_serdes0.phyInstanceNum,\r
187 laneParams_serdes0.serdesInstance,\r
188 2);\r
189 \r
190 /* Select the IP type, IP instance num, Serdes Lane Number */\r
191 CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,\r
192 laneParams_serdes0.phyType,\r
193 laneParams_serdes0.phyInstanceNum,\r
194 laneParams_serdes0.serdesInstance,\r
195 3);\r
196 \r
197 result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,\r
198 laneParams_serdes0.baseAddr,\r
199 laneParams_serdes0.refClock,\r
200 laneParams_serdes0.refClkSrc,\r
201 laneParams_serdes0.serdesInstance,\r
202 laneParams_serdes0.phyType);\r
203 \r
204 if (result != CSL_SERDES_NO_ERR)\r
205 {\r
206 return BOARD_FAIL;\r
207 }\r
208 \r
209 /* Assert PHY reset and disable all lanes */\r
210 CSL_serdesDisablePllAndLanes(laneParams_serdes0.baseAddr, laneParams_serdes0.numLanes, laneParams_serdes0.laneMask);\r
211 \r
212 /* Load the Serdes Config File */\r
213 result = CSL_serdesEthernetInit(&laneParams_serdes0);\r
214 /* Return error if input params are invalid */\r
215 if (result != CSL_SERDES_NO_ERR)\r
216 {\r
217 return BOARD_FAIL;\r
218 }\r
219 \r
220 /* Common Lane Enable API for lane enable, pll enable etc */\r
221 laneRetVal = CSL_serdesLaneEnable(&laneParams_serdes0);\r
222 if (laneRetVal != 0)\r
223 {\r
224 return BOARD_FAIL;\r
225 }\r
226 \r
227 return BOARD_SOK;\r
228 }\r
229 \r
230 /**\r
231 * \brief serdes configurations\r
232 *\r
233 * The function configures the serdes1 module for one lane pcie interface\r
234 *\r
235 * \return BOARD_SOK in case of success or appropriate error code\r
236 *\r
237 */\r
238 Board_STATUS Board_serdesCfgSgmii(void)\r
239 {\r
240 Board_STATUS ret;\r
241 \r
242 /* SERDES0 Initializations */\r
243 ret = Board_serdesCfgEthernet(CSL_SERDES_PHY_TYPE_SGMII);\r
244 if(ret != BOARD_SOK)\r
245 {\r
246 return ret;\r
247 }\r
248 \r
249 return BOARD_SOK;\r
250 }\r
251 \r
252 /**\r
253 * \brief serdes configurations\r
254 *\r
255 * The function configures the serdes1 module for one lane pcie interface\r
256 *\r
257 * \return BOARD_SOK in case of success or appropriate error code\r
258 *\r
259 */\r
260 Board_STATUS Board_serdesCfgQsgmii(void)\r
261 {\r
262 Board_STATUS ret;\r
263 \r
264 /* SERDES0 Initializations */\r
265 ret = Board_serdesCfgEthernet(CSL_SERDES_PHY_TYPE_QSGMII);\r
266 if(ret != BOARD_SOK)\r
267 {\r
268 return ret;\r
269 }\r
270 \r
271 return BOARD_SOK;\r
272 }\r
273 \r
274 /**\r
275 * \brief serdes configurations\r
276 *\r
277 * The function configures the serdes module for USXGMII interface\r
278 *\r
279 * \return BOARD_SOK in case of success or appropriate error code\r
280 *\r
281 */\r
282 Board_STATUS Board_serdesCfgUsxgmii(void)\r
283 {\r
284 Board_STATUS ret;\r
285 \r
286 /* SERDES0 Initializations */\r
287 ret = Board_serdesCfgEthernetUsxgmii();\r
288 if(ret != BOARD_SOK)\r
289 {\r
290 return ret;\r
291 }\r
292 \r
293 return BOARD_SOK;\r
294 }\r
295 \r
296 int32_t Board_serdesCfgStatus(void)\r
297 {\r
298 CSL_SerdesStatus serdesStatus;\r
299 int32_t ret = FALSE;\r
300 \r
301 serdesStatus = CSL_serdesConfigStatus(CSL_SERDES_10G1_BASE);\r
302 if (serdesStatus == CSL_SERDES_STATUS_PLL_LOCKED)\r
303 {\r
304 ret = TRUE;\r
305 }\r
306 \r
307 return ret;\r
308 }\r