1 /******************************************************************************\r
2 * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com\r
3 *\r
4 * Redistribution and use in source and binary forms, with or without\r
5 * modification, are permitted provided that the following conditions\r
6 * are met:\r
7 *\r
8 * Redistributions of source code must retain the above copyright\r
9 * notice, this list of conditions and the following disclaimer.\r
10 *\r
11 * Redistributions in binary form must reproduce the above copyright\r
12 * notice, this list of conditions and the following disclaimer in the\r
13 * documentation and/or other materials provided with the\r
14 * distribution.\r
15 *\r
16 * Neither the name of Texas Instruments Incorporated nor the names of\r
17 * its contributors may be used to endorse or promote products derived\r
18 * from this software without specific prior written permission.\r
19 *\r
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
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29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
31 *\r
32 *****************************************************************************/\r
33 \r
34 /**\r
35 * \file board_ethernet_config.c\r
36 *\r
37 * \brief\r
38 * This file contains the boards specific Ethernet PHY configurations.\r
39 *\r
40 */\r
41 \r
42 #include "board_ethernet_config.h"\r
43 #include "board_internal.h"\r
44 #include <ti/csl/soc.h>\r
45 #include <ti/csl/cslr_mdio.h>\r
46 \r
47 \r
48 Board_pruicssMdioInfo Board_gPruicssMdioInfo[BOARD_ICSS_EMAC_PORT_MAX] =\r
49 {{CSL_PRU_ICSSG0_PR1_MDIO_V1P7_MDIO_BASE, BOARD_ICSS0_EMAC_PHY0_ADDR},\r
50 {CSL_PRU_ICSSG0_PR1_MDIO_V1P7_MDIO_BASE, BOARD_ICSS0_EMAC_PHY1_ADDR},\r
51 {CSL_PRU_ICSSG1_PR1_MDIO_V1P7_MDIO_BASE, BOARD_ICSS1_EMAC_PHY0_ADDR},\r
52 {CSL_PRU_ICSSG1_PR1_MDIO_V1P7_MDIO_BASE, BOARD_ICSS1_EMAC_PHY1_ADDR},\r
53 };\r
54 \r
55 Board_pruicssMdioInfo Board_cpswMdioInfo[BOARD_CPSW9G_EMAC_PORT_MAX] =\r
56 {{(CSL_CPSW0_NUSS_BASE + BOARD_CPSW_MDIO_REG_OFFSET), BOARD_ICSS0_EMAC_PHY0_ADDR},\r
57 {(CSL_CPSW0_NUSS_BASE + BOARD_CPSW_MDIO_REG_OFFSET), BOARD_ICSS0_EMAC_PHY1_ADDR},\r
58 {(CSL_CPSW0_NUSS_BASE + BOARD_CPSW_MDIO_REG_OFFSET), BOARD_ICSS1_EMAC_PHY0_ADDR},\r
59 {(CSL_CPSW0_NUSS_BASE + BOARD_CPSW_MDIO_REG_OFFSET), BOARD_ICSS1_EMAC_PHY1_ADDR},\r
60 };\r
61 /**\r
62 * \brief Function to initialize MDIO\r
63 *\r
64 * \param baseAddr [IN] MDIO base address\r
65 *\r
66 * \return uint32_t\r
67 TRUE Read is successful.\r
68 * FALSE Read is not acknowledged properly.\r
69 */\r
70 static void Board_mdioInit(uint32_t baseAddr)\r
71 {\r
72 HW_WR_REG32((baseAddr + BOARD_MDIO_CTRL_REG_OFFSET),\r
73 (CSL_FMKT(MDIO_CONTROL_REG_ENABLE, YES) |\r
74 CSL_FMK(MDIO_CONTROL_REG_CLKDIV,\r
75 BOARD_MDIO_CLK_DIV_CFG)));\r
76 }\r
77 \r
78 /**\r
79 * \brief PHY register write function\r
80 *\r
81 * This function is used to writes a PHY register using MDIO.\r
82 *\r
83 * \param baseAddr [IN] MDIO base address\r
84 * phyAddr [IN] PHY Address\r
85 * regAddr [IN] Register offset to be written\r
86 * data [IN] Value to be written\r
87 *\r
88 */\r
89 static void Board_ethPhyRegWrite(uint32_t baseAddr, uint32_t phyAddr,\r
90 uint32_t regAddr, uint16_t data)\r
91 {\r
92 uint32_t regVal = 0U;\r
93 \r
94 /* Wait till transaction completion if any */\r
95 while(HW_RD_FIELD32(baseAddr + CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U),\r
96 CSL_MDIO_USER_GROUP_USER_ACCESS_REG_GO) == 1)\r
97 {}\r
98 \r
99 HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_GO, 1);\r
100 HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_WRITE, 1);\r
101 HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_PHYADR, phyAddr);\r
102 HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_REGADR, regAddr);\r
103 HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_DATA, data);\r
104 HW_WR_REG32(baseAddr + CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U), regVal);\r
105 \r
106 /* wait for command completion */\r
107 while(HW_RD_FIELD32(baseAddr + CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U),\r
108 CSL_MDIO_USER_GROUP_USER_ACCESS_REG_GO) == 1)\r
109 {}\r
110 }\r
111 \r
112 /**\r
113 * \brief PHY register read function\r
114 *\r
115 * This function is used to Read a PHY register using MDIO.\r
116 *\r
117 * \param baseAddr [IN] MDIO base address\r
118 * phyAddr [IN] PHY Address\r
119 * regAddr [IN] Register offset to be written\r
120 * regData [OUT] Pointer where the read value shall be written\r
121 *\r
122 * \return uint32_t\r
123 TRUE Read is successful.\r
124 * FALSE Read is not acknowledged properly.\r
125 */\r
126 static uint32_t BoardDiag_ethPhyRegRead(uint32_t baseAddr, uint32_t phyAddr,\r
127 uint32_t regAddr, uint16_t *regData)\r
128 {\r
129 uint32_t regVal = 0U;\r
130 uint32_t retVal = 0U;\r
131 \r
132 /* Wait till transaction completion if any */\r
133 while(HW_RD_FIELD32(baseAddr + CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U),\r
134 CSL_MDIO_USER_GROUP_USER_ACCESS_REG_GO) == 1)\r
135 {}\r
136 HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_GO,1);\r
137 HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_WRITE, 0);\r
138 HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_PHYADR, phyAddr);\r
139 HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_REGADR, regAddr);\r
140 HW_WR_REG32(baseAddr + CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U), regVal);\r
141 \r
142 /* wait for command completion */\r
143 while(HW_RD_FIELD32(baseAddr + CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U),\r
144 CSL_MDIO_USER_GROUP_USER_ACCESS_REG_GO) == 1)\r
145 {}\r
146 \r
147 /* Store the data if the read is acknowledged */\r
148 if(HW_RD_FIELD32(baseAddr + CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U),\r
149 CSL_MDIO_USER_GROUP_USER_ACCESS_REG_ACK) == 1)\r
150 {\r
151 *regData = (uint16_t)(HW_RD_FIELD32(baseAddr + \\r
152 CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U),\r
153 CSL_MDIO_USER_GROUP_USER_ACCESS_REG_DATA));\r
154 retVal = (uint32_t)TRUE;\r
155 }\r
156 else\r
157 {\r
158 retVal = (uint32_t)FALSE;\r
159 }\r
160 \r
161 return(retVal);\r
162 }\r
163 \r
164 /**\r
165 * \brief Function to write extended address registers of Ethernet PHY\r
166 *\r
167 * \param baseAddr [IN] MDIO base address\r
168 * phyAddr [IN] Ethernet PHY address\r
169 * regNum [IN] PHY Register address\r
170 * pData [OUT] Values read from register\r
171 *\r
172 */\r
173 static void Board_ethPhyExtendedRegRead (uint32_t baseAddr,\r
174 uint32_t phyAddr,\r
175 uint32_t regNum,\r
176 uint16_t *pData)\r
177 {\r
178 Board_ethPhyRegWrite(baseAddr, phyAddr,\r
179 BOARD_ETHPHY_REGCR_REG_ADDR,\r
180 BOARD_ETHPHY_REGCR_ADDR_EN);\r
181 Board_ethPhyRegWrite(baseAddr, phyAddr,\r
182 BOARD_ETHPHY_ADDAR_REG_ADDR, regNum);\r
183 Board_ethPhyRegWrite(baseAddr, phyAddr,\r
184 BOARD_ETHPHY_REGCR_REG_ADDR,\r
185 BOARD_ETHPHY_REGCR_DATA_EN);\r
186 BoardDiag_ethPhyRegRead(baseAddr, phyAddr,\r
187 BOARD_ETHPHY_ADDAR_REG_ADDR, pData);\r
188 }\r
189 \r
190 /**\r
191 * \brief Function to write extended address registers of Ethernet PHY\r
192 *\r
193 * \param baseAddr [IN] MDIO base address\r
194 * \param phyAddr [IN] Ethernet PHY address\r
195 * \param regNum [IN] PHY Register address\r
196 * \param regVal [IN] Register value to be written\r
197 *\r
198 * \return none\r
199 */\r
200 static void Board_ethPhyExtendedRegWrite(uint32_t baseAddr,\r
201 uint32_t phyAddr,\r
202 uint32_t regNum,\r
203 uint16_t regVal)\r
204 {\r
205 Board_ethPhyRegWrite(baseAddr, phyAddr,\r
206 BOARD_ETHPHY_REGCR_REG_ADDR,\r
207 BOARD_ETHPHY_REGCR_ADDR_EN);\r
208 Board_ethPhyRegWrite(baseAddr, phyAddr,\r
209 BOARD_ETHPHY_ADDAR_REG_ADDR, regNum);\r
210 Board_ethPhyRegWrite(baseAddr, phyAddr,\r
211 BOARD_ETHPHY_REGCR_REG_ADDR,\r
212 BOARD_ETHPHY_REGCR_DATA_EN);\r
213 Board_ethPhyRegWrite(baseAddr, phyAddr,\r
214 BOARD_ETHPHY_ADDAR_REG_ADDR, regVal);\r
215 }\r
216 \r
217 /**\r
218 * \brief Disables ICSSG MAC internal delay\r
219 *\r
220 * \return none\r
221 */\r
222 static void Board_disableIcssEmacDelay(void)\r
223 {\r
224 HW_WR_REG32((CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_ICSSG0_CTRL0), BOARD_EMAC_DELAY_CFG);\r
225 HW_WR_REG32((CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_ICSSG0_CTRL1), BOARD_EMAC_DELAY_CFG);\r
226 HW_WR_REG32((CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_ICSSG1_CTRL0), BOARD_EMAC_DELAY_CFG);\r
227 HW_WR_REG32((CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_ICSSG1_CTRL1), BOARD_EMAC_DELAY_CFG);\r
228 }\r
229 \r
230 /**\r
231 * \brief Power down the ENET PHYs\r
232 *\r
233 * \return BOARD_SOK in case of success or appropriate error code\r
234 */\r
235 static Board_STATUS Board_enetPhyPwrDwn(void)\r
236 {\r
237 Board_IoExpCfg_t ioExpCfg;\r
238 Board_STATUS status = BOARD_SOK;\r
239 bool isAlpha = 0;\r
240 \r
241 /*\r
242 * MDIO stability issue due to ENET card is resolved in Beta HW revision.\r
243 * Disabling ENET card is needed only for Alpha CP boards.\r
244 */\r
245 isAlpha = Board_isAlpha(BOARD_ID_CP);\r
246 \r
247 if((isAlpha == TRUE) && (Board_detectBoard(BOARD_ID_ENET) == TRUE))\r
248 {\r
249 ioExpCfg.i2cInst = BOARD_I2C_IOEXP_DEVICE2_INSTANCE;\r
250 ioExpCfg.socDomain = BOARD_SOC_DOMAIN_MAIN;\r
251 ioExpCfg.slaveAddr = BOARD_I2C_IOEXP_DEVICE2_ADDR;\r
252 ioExpCfg.enableIntr = false;\r
253 ioExpCfg.ioExpType = THREE_PORT_IOEXP;\r
254 ioExpCfg.portNum = PORTNUM_2;\r
255 ioExpCfg.pinNum = PIN_NUM_0;\r
256 ioExpCfg.signalLevel = GPIO_SIGNAL_LEVEL_HIGH;\r
257 \r
258 status = Board_control(BOARD_CTRL_CMD_SET_IO_EXP_PIN_OUT, &ioExpCfg);\r
259 \r
260 ioExpCfg.i2cInst = BOARD_I2C_IOEXP_DEVICE2_INSTANCE;\r
261 ioExpCfg.socDomain = BOARD_SOC_DOMAIN_MAIN;\r
262 ioExpCfg.slaveAddr = BOARD_I2C_IOEXP_DEVICE2_ADDR;\r
263 ioExpCfg.enableIntr = false;\r
264 ioExpCfg.ioExpType = THREE_PORT_IOEXP;\r
265 ioExpCfg.portNum = PORTNUM_2;\r
266 ioExpCfg.pinNum = PIN_NUM_1;\r
267 ioExpCfg.signalLevel = GPIO_SIGNAL_LEVEL_LOW;\r
268 \r
269 status = Board_control(BOARD_CTRL_CMD_SET_IO_EXP_PIN_OUT, &ioExpCfg);\r
270 }\r
271 \r
272 return status;\r
273 }\r
274 \r
275 /**\r
276 * \brief Board specific configurations for SGMII Ethernet PHYs\r
277 *\r
278 * This function takes care of configuring the internal delays for SGMII\r
279 * Ethernet PHYs\r
280 *\r
281 * \return BOARD_SOK in case of success or appropriate error code\r
282 */\r
283 Board_STATUS Board_sgmiiEthPhyConfig(void)\r
284 {\r
285 return BOARD_SOK;\r
286 }\r
287 \r
288 /**\r
289 * \brief Board specific configurations for CPSW9G Ethernet PHYs\r
290 *\r
291 * This function takes care of configuring the internal delays for CPSW9G\r
292 * Ethernet PHYs\r
293 *\r
294 * \return BOARD_SOK in case of success or appropriate error code\r
295 */\r
296 Board_STATUS Board_cpsw9gEthPhyConfig(void)\r
297 {\r
298 Board_STATUS status;\r
299 uint32_t baseAddr;\r
300 uint8_t phyAddr;\r
301 uint32_t index;\r
302 uint16_t regData = 0;\r
303 \r
304 /* CPSW9G MDIO access is unstable when ENET card is connected.\r
305 Keeping the ENET PHY in reset as a temporary workaround */\r
306 status = Board_enetPhyPwrDwn();\r
307 if (status != BOARD_SOK)\r
308 {\r
309 return status;\r
310 }\r
311 \r
312 for(index = 0; index < BOARD_CPSW9G_EMAC_PORT_MAX; index++)\r
313 {\r
314 baseAddr = Board_cpswMdioInfo[index].mdioBaseAddrs;\r
315 phyAddr = Board_cpswMdioInfo[index].phyAddrs;\r
316 \r
317 Board_mdioInit(baseAddr);\r
318 \r
319 /* Enable PHY speed LED functionality */\r
320 Board_ethPhyExtendedRegRead(baseAddr, phyAddr,\r
321 BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_ADDR,\r
322 ®Data);\r
323 regData = (regData & ~(BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_MASK)) |\r
324 BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_CFG;\r
325 Board_ethPhyExtendedRegWrite(baseAddr, phyAddr,\r
326 BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_ADDR,\r
327 regData);\r
328 \r
329 regData = 0;\r
330 BoardDiag_ethPhyRegRead(baseAddr, phyAddr,\r
331 BOARD_ETHPHY_LEDCR1_REG_ADDR, ®Data);\r
332 regData = (regData & ~(BOARD_ETHPHY_LEDCR1_REG_MASK)) |\r
333 BOARD_ETHPHY_LEDCR1_REG_CFG;\r
334 Board_ethPhyRegWrite(baseAddr, phyAddr,\r
335 BOARD_ETHPHY_LEDCR1_REG_ADDR, regData);\r
336 \r
337 /* When the Phy is strapped to enable Fast Link Drop (FLD) feature,\r
338 * the detect threshold value becomes 0x2 in bit 2:0 instead of 0x1\r
339 * in the FLD_THRESH (0x2e) register as in non strapped case.\r
340 * This causes the phy link to be unstable.\r
341 * As a workaround, write a value of 0x1 in this bit field if\r
342 * bit 10 of STRAP_STS2 (0x6f) register is set (enable FLD).\r
343 */\r
344 regData = 0;\r
345 Board_ethPhyExtendedRegRead(baseAddr, phyAddr,\r
346 BOARD_ETHPHY_STRAP_STS2_REG_ADDR,\r
347 ®Data);\r
348 if (regData & BOARD_ETHPHY_STRAP_FLD_MASK)\r
349 {\r
350 regData = 0;\r
351 Board_ethPhyExtendedRegRead(baseAddr, phyAddr,\r
352 BOARD_ETHPHY_FLD_THRESH_REG_ADDR,\r
353 ®Data);\r
354 if (regData == BOARD_ETHPHY_STRAP_FLD_THS_CHECK_FLAG)\r
355 {\r
356 regData &= ~0x7;\r
357 Board_ethPhyExtendedRegWrite(baseAddr, phyAddr,\r
358 BOARD_ETHPHY_FLD_THRESH_REG_ADDR,\r
359 (regData | 0x1));\r
360 }\r
361 }\r
362 \r
363 /*Setting IO impedance to 35ohms */\r
364 Board_ethPhyExtendedRegWrite(baseAddr, phyAddr,\r
365 BOARD_ETHPHY_GPIO_MUX_CFG_REG_ADDR,\r
366 BOARD_ETHPHY_IO_IMPEDANCE);\r
367 \r
368 /* Enable the PHY delay configurations */\r
369 Board_ethPhyExtendedRegWrite(baseAddr, phyAddr, BOARD_ETHPHY_RGMIICTL_REG_ADDR,\r
370 BOARD_ETHPHY_DELAY_CTRL);\r
371 \r
372 /* Setting delay */\r
373 Board_ethPhyExtendedRegWrite(baseAddr, phyAddr,\r
374 BOARD_ETHPHY_RGMIIDCTL_REG_ADDR,\r
375 BOARD_ETHPHY_CPSW9G_DELAY);\r
376 }\r
377 \r
378 return BOARD_SOK;\r
379 }\r
380 \r
381 /**\r
382 * \brief Board specific configurations for CPSW2G Ethernet PHY\r
383 *\r
384 * This function takes care of configuring the internal delays for MCU gigabit\r
385 * Ethernet PHY\r
386 *\r
387 * \return BOARD_SOK in case of success or appropriate error code\r
388 */\r
389 Board_STATUS Board_cpsw2gEthPhyConfig(void)\r
390 {\r
391 uint32_t baseAddr;\r
392 uint16_t regData = 0;\r
393 \r
394 baseAddr = (CSL_MCU_CPSW0_NUSS_BASE + 0x0F00);\r
395 \r
396 Board_mdioInit(baseAddr);\r
397 \r
398 /* Enable PHY speed LED functionality */\r
399 Board_ethPhyExtendedRegRead(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,\r
400 BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_ADDR,\r
401 ®Data);\r
402 regData = (regData & ~(BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_MASK)) |\r
403 BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_CFG;\r
404 Board_ethPhyExtendedRegWrite(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,\r
405 BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_ADDR,\r
406 regData);\r
407 \r
408 regData = 0;\r
409 BoardDiag_ethPhyRegRead(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,\r
410 BOARD_ETHPHY_LEDCR1_REG_ADDR, ®Data);\r
411 regData = (regData & ~(BOARD_ETHPHY_LEDCR1_REG_MASK)) |\r
412 BOARD_ETHPHY_LEDCR1_REG_CFG;\r
413 Board_ethPhyRegWrite(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,\r
414 BOARD_ETHPHY_LEDCR1_REG_ADDR, regData);\r
415 \r
416 /* When the Phy is strapped to enable Fast Link Drop (FLD) feature,\r
417 * the detect threshold value becomes 0x2 in bit 2:0 instead of 0x1\r
418 * in the FLD_THRESH (0x2e) register as in non strapped case.\r
419 * This causes the phy link to be unstable.\r
420 * As a workaround, write a value of 0x1 in this bit field if\r
421 * bit 10 of STRAP_STS2 (0x6f) register is set (enable FLD).\r
422 */\r
423 regData = 0;\r
424 Board_ethPhyExtendedRegRead(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,\r
425 BOARD_ETHPHY_STRAP_STS2_REG_ADDR,\r
426 ®Data);\r
427 if (regData & BOARD_ETHPHY_STRAP_FLD_MASK)\r
428 {\r
429 regData = 0;\r
430 Board_ethPhyExtendedRegRead(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,\r
431 BOARD_ETHPHY_FLD_THRESH_REG_ADDR,\r
432 ®Data);\r
433 if (regData == BOARD_ETHPHY_STRAP_FLD_THS_CHECK_FLAG)\r
434 {\r
435 regData &= ~0x7;\r
436 Board_ethPhyExtendedRegWrite(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,\r
437 BOARD_ETHPHY_FLD_THRESH_REG_ADDR,\r
438 (regData | 0x1));\r
439 }\r
440 }\r
441 \r
442 /* Enabling the TX and RX delay */\r
443 Board_ethPhyExtendedRegRead(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,\r
444 BOARD_ETHPHY_RGMIICTL_REG_ADDR, ®Data);\r
445 regData = regData | 0x3;\r
446 Board_ethPhyExtendedRegWrite(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,\r
447 BOARD_ETHPHY_RGMIICTL_REG_ADDR, regData);\r
448 \r
449 /* Setting delay */\r
450 Board_ethPhyExtendedRegWrite(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,\r
451 BOARD_ETHPHY_RGMIIDCTL_REG_ADDR,\r
452 BOARD_ETHPHY_CPSW2G_DELAY);\r
453 \r
454 return BOARD_SOK;\r
455 \r
456 }\r
457 \r
458 /**\r
459 * \brief Board specific configurations for ICSS EMAC Ethernet PHYs\r
460 *\r
461 * This function takes care of configuring the internal delays for ICSS\r
462 * Ethernet PHY\r
463 *\r
464 * \return BOARD_SOK in case of success or appropriate error code\r
465 */\r
466 Board_STATUS Board_icssEthPhyConfig(void)\r
467 {\r
468 uint32_t baseAddr;\r
469 uint8_t phyAddr;\r
470 uint32_t index;\r
471 uint16_t regData = 0;\r
472 Board_STATUS status = BOARD_SOK;\r
473 \r
474 status = Board_control(BOARD_CTRL_CMD_SET_ICSSG_MDIO_MUX, NULL);\r
475 if(status == BOARD_SOK)\r
476 {\r
477 for(index = 0; index < BOARD_ICSS_EMAC_PORT_MAX; index++)\r
478 {\r
479 baseAddr = Board_gPruicssMdioInfo[index].mdioBaseAddrs;\r
480 phyAddr = Board_gPruicssMdioInfo[index].phyAddrs;\r
481 \r
482 Board_mdioInit(baseAddr);\r
483 \r
484 /* Enable the PHY delay configurations */\r
485 Board_ethPhyExtendedRegWrite(baseAddr, phyAddr,\r
486 BOARD_ETHPHY_RGMIICTL_REG_ADDR,\r
487 BOARD_ETHPHY_DELAY_CTRL);\r
488 \r
489 /* Setting delay */\r
490 Board_ethPhyExtendedRegWrite(baseAddr, phyAddr,\r
491 BOARD_ETHPHY_RGMIIDCTL_REG_ADDR,\r
492 BOARD_ETHPHY_ICSSG_DELAY);\r
493 \r
494 /*Setting IO impedance to 35ohms */\r
495 Board_ethPhyExtendedRegWrite(baseAddr, phyAddr,\r
496 BOARD_ETHPHY_GPIO_MUX_CFG_REG_ADDR,\r
497 BOARD_ETHPHY_IO_IMPEDANCE);\r
498 \r
499 /* Enable PHY speed LED functionality */\r
500 Board_ethPhyExtendedRegRead(baseAddr, phyAddr,\r
501 BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_ADDR,\r
502 ®Data);\r
503 regData = (regData & ~(BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_MASK)) | 0x6;\r
504 Board_ethPhyExtendedRegWrite(baseAddr, phyAddr,\r
505 BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_ADDR,\r
506 regData);\r
507 \r
508 regData = 0;\r
509 BoardDiag_ethPhyRegRead(baseAddr, phyAddr,\r
510 BOARD_ETHPHY_LEDCR1_REG_ADDR, ®Data);\r
511 regData = (regData & ~(BOARD_ETHPHY_LEDCR1_REG_MASK)) |\r
512 BOARD_ETHPHY_LEDCR1_REG_CFG;\r
513 Board_ethPhyRegWrite(baseAddr, phyAddr,\r
514 BOARD_ETHPHY_LEDCR1_REG_ADDR, regData);\r
515 \r
516 /* When the Phy is strapped to enable Fast Link Drop (FLD) feature,\r
517 * the detect threshold value becomes 0x2 in bit 2:0 instead of 0x1\r
518 * in the FLD_THRESH (0x2e) register as in non strapped case.\r
519 * This causes the phy link to be unstable.\r
520 * As a workaround, write a value of 0x1 in this bit field if\r
521 * bit 10 of STRAP_STS2 (0x6f) register is set (enable FLD).\r
522 */\r
523 regData = 0;\r
524 Board_ethPhyExtendedRegRead(baseAddr, phyAddr,\r
525 BOARD_ETHPHY_STRAP_STS2_REG_ADDR,\r
526 ®Data);\r
527 if (regData & BOARD_ETHPHY_STRAP_FLD_MASK)\r
528 {\r
529 regData = 0;\r
530 Board_ethPhyExtendedRegRead(baseAddr, phyAddr,\r
531 BOARD_ETHPHY_FLD_THRESH_REG_ADDR,\r
532 ®Data);\r
533 if (regData == BOARD_ETHPHY_STRAP_FLD_THS_CHECK_FLAG)\r
534 {\r
535 regData &= ~0x7;\r
536 Board_ethPhyExtendedRegWrite(baseAddr, phyAddr,\r
537 BOARD_ETHPHY_FLD_THRESH_REG_ADDR,\r
538 (regData | 0x1));\r
539 }\r
540 }\r
541 }\r
542 }\r
543 \r
544 return status;\r
545 }\r
546 \r
547 /**\r
548 * \brief Configures the CPSW9G Subsytem for RGMII and RMII mode\r
549 *\r
550 * \param portNum [IN] EMAC port number\r
551 * \param mode [IN] Mode selection for the specified port number\r
552 * 000 - GMII\r
553 * 001 - RMII\r
554 * 010 - RGMII\r
555 * 011 - SGMII\r
556 * 100 - QSGMII\r
557 *\r
558 * \return BOARD_SOK in case of success or appropriate error code\r
559 */\r
560 static Board_STATUS Board_cpsw9gEthConfig(uint32_t portNum, uint8_t mode)\r
561 {\r
562 uint32_t status;\r
563 uintptr_t modeSel;\r
564 uint32_t regData;\r
565 \r
566 modeSel = CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_ENET1_CTRL + (portNum * 0x04);\r
567 regData = CSL_REG32_RD(modeSel);\r
568 regData = mode;\r
569 if (RGMII == mode)\r
570 {\r
571 regData |= (RGMII_ID_DISABLE_MASK);\r
572 }\r
573 CSL_REG32_WR(modeSel , regData);\r
574 status = CSL_REG32_RD(modeSel);\r
575 if (status != regData)\r
576 {\r
577 return BOARD_FAIL;\r
578 }\r
579 \r
580 return BOARD_SOK;\r
581 }\r
582 \r
583 /**\r
584 * \brief Board specific configurations for ICSSG RGMII Ethernet\r
585 *\r
586 * This function takes care of configuring the internal delays for\r
587 * ICSSG RGMII Ethernet PHY\r
588 *\r
589 * \return BOARD_SOK in case of success or appropriate error code\r
590 */\r
591 static Board_STATUS Board_icssEthConfig(uint32_t portNum, uint8_t mode)\r
592 {\r
593 Board_disableIcssEmacDelay();\r
594 return BOARD_SOK;\r
595 }\r
596 \r
597 \r
598 /**\r
599 * \brief Board specific configurations for SGMII Ethernet\r
600 *\r
601 * This function takes care of configuring the internal delays for\r
602 * SGMII Ethernet PHY\r
603 *\r
604 * \return BOARD_SOK in case of success or appropriate error code\r
605 */\r
606 static Board_STATUS Board_sgmiiEthConfig(uint32_t portNum, uint8_t mode)\r
607 {\r
608 return BOARD_SOK;\r
609 }\r
610 \r
611 /**\r
612 * \brief Configures the CPSW2G Subsytem for RGMII mode\r
613 *\r
614 * \param portNum [IN] EMAC port number\r
615 * \param mode [IN] Mode selection for the specified port number\r
616 * 00 - GMII\r
617 * 01 - RMII\r
618 * 10 - RGMII\r
619 * 11 - SGMII\r
620 *\r
621 * \return BOARD_SOK in case of success or appropriate error code\r
622 */\r
623 Board_STATUS Board_cpsw2gMacModeConfig(uint32_t portNum, uint8_t mode)\r
624 {\r
625 uint32_t status;\r
626 uintptr_t ethModeCtrl;\r
627 uint32_t regData;\r
628 \r
629 ethModeCtrl = CSL_MCU_CTRL_MMR0_CFG0_BASE + CSL_MCU_CTRL_MMR_CFG0_MCU_ENET_CTRL;\r
630 regData = CSL_REG32_RD(ethModeCtrl);\r
631 regData = mode;\r
632 if (RGMII == mode)\r
633 {\r
634 regData |= (RGMII_ID_DISABLE_MASK);\r
635 }\r
636 \r
637 CSL_REG32_WR(ethModeCtrl , regData);\r
638 status = CSL_REG32_RD(ethModeCtrl);\r
639 if (status != regData)\r
640 {\r
641 return BOARD_FAIL;\r
642 }\r
643 \r
644 return BOARD_SOK;\r
645 }\r
646 \r
647 /**\r
648 * \brief Board specific configurations for CPSW2G Ethernet ports\r
649 *\r
650 * This function used to configures CPSW2G Ethernet controllers with the respective modes\r
651 *\r
652 * \return BOARD_SOK in case of success or appropriate error code\r
653 */\r
654 Board_STATUS Board_ethConfigCpsw2g(void)\r
655 {\r
656 Board_STATUS status = BOARD_SOK;\r
657 \r
658 Board_unlockMMR();\r
659 \r
660 /* Configures the MCU Ethernet */\r
661 status = Board_cpsw2gMacModeConfig(CPSW2G_PORTNUM, RGMII);\r
662 if(status != BOARD_SOK)\r
663 {\r
664 return BOARD_FAIL;\r
665 }\r
666 \r
667 return BOARD_SOK;\r
668 }\r
669 \r
670 /**\r
671 * \brief Board specific configurations for CPSW9G Ethernet ports\r
672 *\r
673 * This function used to configures CPSW9G Ethernet controllers with the respective modes\r
674 *\r
675 * \return BOARD_SOK in case of success or appropriate error code\r
676 */\r
677 Board_STATUS Board_ethConfigCpsw9g(void)\r
678 {\r
679 Board_STATUS status = BOARD_SOK;\r
680 uint8_t portNum;\r
681 \r
682 Board_unlockMMR();\r
683 \r
684 /* Configures the CPSW9G RGMII ports */\r
685 for(portNum=0; portNum < BOARD_CPSW9G_EMAC_PORT_MAX; portNum++)\r
686 {\r
687 status = Board_cpsw9gEthConfig(portNum, RGMII);\r
688 if(status != BOARD_SOK)\r
689 {\r
690 return BOARD_FAIL;\r
691 }\r
692 }\r
693 \r
694 /* Configures CPSW9G RMII port */\r
695 status = Board_cpsw9gEthConfig(CPSW9G_RMII_PORTNUM, RMII);\r
696 if(status != BOARD_SOK)\r
697 {\r
698 return BOARD_FAIL;\r
699 }\r
700 \r
701 /* Configures SGMII Ethernet */\r
702 for(portNum=0; portNum<BOARD_SGMII_PORT_MAX; portNum++)\r
703 {\r
704 status = Board_sgmiiEthConfig(portNum, QSGMII);\r
705 if(status != BOARD_SOK)\r
706 {\r
707 return BOARD_FAIL;\r
708 }\r
709 }\r
710 \r
711 return BOARD_SOK;\r
712 }\r
713 \r
714 /**\r
715 * \brief Board specific configurations for ICSS Ethernet ports\r
716 *\r
717 * This function used to configures ICSS Ethernet controllers with the respective modes\r
718 *\r
719 * \return BOARD_SOK in case of success or appropriate error code\r
720 */\r
721 Board_STATUS Board_ethConfigIcss(void)\r
722 {\r
723 Board_STATUS status = BOARD_SOK;\r
724 uint8_t portNum;\r
725 \r
726 Board_unlockMMR();\r
727 \r
728 /* Configures ICSSG Ethernet */\r
729 for(portNum=0; portNum < BOARD_ICSS_EMAC_PORT_MAX; portNum++)\r
730 {\r
731 status = Board_icssEthConfig(portNum, RGMII);\r
732 if(status != BOARD_SOK)\r
733 {\r
734 return BOARD_FAIL;\r
735 }\r
736 }\r
737 \r
738 return BOARD_SOK;\r
739 }\r