1 /******************************************************************************\r
2 * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com\r
3 *\r
4 * Redistribution and use in source and binary forms, with or without\r
5 * modification, are permitted provided that the following conditions\r
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9 * notice, this list of conditions and the following disclaimer.\r
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11 * Redistributions in binary form must reproduce the above copyright\r
12 * notice, this list of conditions and the following disclaimer in the\r
13 * documentation and/or other materials provided with the\r
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20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
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22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
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30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
31 *\r
32 *****************************************************************************/\r
33 \r
34 /**\r
35 * \file board_pll.c\r
36 *\r
37 * \brief Board pll configurations\r
38 *\r
39 */\r
40 \r
41 #include "board_internal.h"\r
42 #include "board_pll.h"\r
43 #include <ti/drv/sciclient/sciclient.h>\r
44 \r
45 static Board_PllClkCfg_t gBoardPllClkCfgMcu[] =\r
46 {\r
47 /* MCU PLL1 Clockout */ \r
48 { TISCI_DEV_MCU_ADC0,\r
49 TISCI_DEV_MCU_ADC0_ADC_CLK,\r
50 60000000\r
51 }, //MCU_PLL0_HSDIV1\r
52 \r
53 /* MCU PLL1 Clockout */ \r
54 { TISCI_DEV_MCU_SA2_UL0,\r
55 TISCI_DEV_SA2_UL0_PKA_IN_CLK,\r
56 400000000\r
57 }, //MCU_PLL1_HSDIV0_CLKOUT\r
58 { TISCI_DEV_MCU_ADC0,\r
59 TISCI_DEV_MCU_ADC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK,\r
60 60000000\r
61 }, //MCU_PLL1_HSDIV1_CLKOUT\r
62 { TISCI_DEV_MCU_MCAN0,\r
63 TISCI_DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK,\r
64 80000000\r
65 }, //MCU_PLL1_HSDIV2_CLKOUT\r
66 { TISCI_DEV_MCU_UART0,\r
67 TISCI_DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK,\r
68 96000000\r
69 }, //MCU_PLL1_HSDIV3_CLKOUT,\r
70 { TISCI_DEV_MCU_FSS0_OSPI_0,\r
71 TISCI_DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK,\r
72 133333333\r
73 }, //MCU_PLL1_HSDIV4_CLKOUT\r
74 /* MCU PLL2 Clockout */ \r
75 { TISCI_DEV_MCU_CPSW0,\r
76 TISCI_DEV_MCU_CPSW0_RGMII_MHZ_250_CLK,\r
77 250000000\r
78 }, //MCU_PLL2_HSDIV0_CLKOUT\r
79 { TISCI_DEV_MCU_CPSW0,\r
80 TISCI_DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK,\r
81 200000000\r
82 }, //MCU_PLL2_HSDIV1_CLKOUT\r
83 { TISCI_DEV_MCU_TIMER0,\r
84 TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK,\r
85 200000000\r
86 }, //MCU_PLL2_HSDIV2_CLKOUT\r
87 { TISCI_DEV_MCU_MCAN0,\r
88 TISCI_DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK,\r
89 80000000\r
90 }, //MCU_PLL2_HSDIV3_CLKOUT\r
91 { TISCI_DEV_MCU_FSS0_HYPERBUS1P0_0,\r
92 TISCI_DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_CLK,\r
93 166666666\r
94 } //MCU_PLL2_HSDIV4_CLKOUT\r
95 };\r
96 \r
97 static Board_PllClkCfg_t gBoardPllClkCfgMain[] =\r
98 {\r
99 /* MAIN PLL0 Clockout */ \r
100 { TISCI_DEV_USB0,\r
101 TISCI_DEV_USB0_ACLK_CLK,\r
102 500000000\r
103 },\r
104 { TISCI_DEV_TIMER0,\r
105 TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK,\r
106 250000000\r
107 }, //MAIN_PLL0_HSDIV1_CLKOUT \r
108 { TISCI_DEV_MMCSD0,\r
109 TISCI_DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK,\r
110 200000000\r
111 }, //MAIN_PLL0_HSDIV2_CLKOUT \r
112 { TISCI_DEV_GPMC0,\r
113 TISCI_DEV_GPMC0_FUNC_CLK,\r
114 133330000\r
115 }, //MAIN_PLL0_HSDIV3_CLKOUT \r
116 { TISCI_DEV_MCAN0,\r
117 TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK,\r
118 80000000\r
119 }, //MAIN_PLL0_HSDIV4_CLKOUT \r
120 { TISCI_DEV_MCSPI0,\r
121 TISCI_DEV_MCSPI0_CLKSPIREF_CLK,\r
122 50000000\r
123 }, //MAIN_PLL0_HSDIV5_CLKOUT \r
124 { TISCI_DEV_PCIE0,\r
125 TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK,\r
126 250000000\r
127 }, //MAIN_PLL0_HSDIV6_CLKOUT \r
128 \r
129 /* MAIN PLL1(PER0_PLL) Clockout */ \r
130 { TISCI_DEV_PRU_ICSSG0,\r
131 TISCI_DEV_PRU_ICSSG0_UCLK_CLK, \r
132 192000000\r
133 }, //MAIN_PLL1_HSDIV0_CLKOUT\r
134 { TISCI_DEV_MMCSD1,\r
135 TISCI_DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK,\r
136 192000000\r
137 }, //MAIN_PLL1_HSDIV2_CLKOUT\r
138 { TISCI_DEV_TIMER0,\r
139 TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK, \r
140 192000000\r
141 }, //MAIN_PLL1_HSDIV3_CLKOUT\r
142 { TISCI_DEV_MCU_UART0,\r
143 TISCI_DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT5_CLK,\r
144 192000000\r
145 }, //MAIN_PLL1_HSDIV5_CLKOUT\r
146 { TISCI_DEV_UFS0,\r
147 TISCI_DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT6_CLK,\r
148 19200000\r
149 }, //MAIN_PLL1_HSDIV6_CLKOUT\r
150 { TISCI_DEV_USB0,\r
151 TISCI_DEV_USB0_CLK_LPM_CLK,\r
152 24000000\r
153 }, //MAIN_PLL1_HSDIV7_CLKOUT\r
154 \r
155 /* MAIN PLL2(PER1_PLL) Clockout */ \r
156 { TISCI_DEV_PRU_ICSSG0,\r
157 TISCI_DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK, \r
158 360000000\r
159 },\r
160 \r
161 { TISCI_DEV_MMCSD0,\r
162 TISCI_DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK, \r
163 200000000\r
164 }, //MAIN_PLL2_HSDIV2_CLKOUTT\r
165 \r
166 { TISCI_DEV_TIMER0,\r
167 TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK,\r
168 225000000\r
169 }, //MAIN_PLL2_HSDIV6_CLKOUT\r
170 \r
171 { TISCI_DEV_PCIE0,\r
172 TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK,\r
173 250000000\r
174 }, //MAIN_PLL3_HSDIV1_CLKOUT\r
175 { TISCI_DEV_MMCSD0,\r
176 TISCI_DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK,\r
177 200000000\r
178 }, //MAIN_PLL3_HSDIV2_CLKOUT\r
179 { TISCI_DEV_TIMER0,\r
180 TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK,\r
181 250000000\r
182 }, //MAIN_PLL3_HSDIV3_CLKOUT\r
183 { TISCI_DEV_SERDES_16G0,\r
184 TISCI_DEV_SERDES_16G0_CORE_REF1_CLK,\r
185 156250000\r
186 }, //MAIN_PLL3_HSDIV4_CLKOUT\r
187 \r
188 /* MAIN PLL4((AUDIO0_PLL) Clockout */ \r
189 { TISCI_DEV_MCASP0,\r
190 TISCI_DEV_MCASP0_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK,\r
191 196608000\r
192 },\r
193 \r
194 { TISCI_DEV_TIMER0,\r
195 TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK,\r
196 196608000\r
197 },\r
198 \r
199 /* MAIN PLL5((VIDEO0_PLL) Clockout */ \r
200 { TISCI_DEV_ENCODER0,\r
201 TISCI_DEV_ENCODER0_SYS_CLK,\r
202 550000000\r
203 }, //MAIN_PLL5_HSDIV0_CLKOUT\r
204 { TISCI_DEV_DECODER0,\r
205 TISCI_DEV_DECODER0_SYS_CLK,\r
206 550000000\r
207 }, //MAIN_PLL5_HSDIV1_CLKOUT\r
208 \r
209 /* MAIN PLL6((GPU_PLL) Clockout */ \r
210 { TISCI_DEV_GPU0_GPU_0,\r
211 TISCI_DEV_GPU0_GPU_0_GPU_PLL_CLK,\r
212 750000000\r
213 },\r
214 \r
215 /* MAIN PLL7(C7x /MSMC PLL) Clockout */\r
216 { TISCI_DEV_A72SS0_CORE0,\r
217 TISCI_DEV_A72SS0_CORE0_MSMC_CLK,\r
218 1000000000\r
219 },\r
220 \r
221 /* MAIN PLL8(ARM0 PLL) Clockout */ \r
222 { TISCI_DEV_A72SS0_CORE0,\r
223 TISCI_DEV_A72SS0_CORE0_ARM_CLK_CLK,\r
224 200000000\r
225 },\r
226 \r
227 /* MAIN PLL14(PULSAR PLL) Clockout */ \r
228 { TISCI_DEV_PULSAR_SL_MAIN_0,\r
229 TISCI_DEV_PULSAR_SL_MAIN_0_INTERFACE0_PHASE_0,\r
230 250000000\r
231 },\r
232 { TISCI_DEV_PULSAR_SL_MAIN_1,\r
233 TISCI_DEV_PULSAR_SL_MAIN_1_INTERFACE0_PHASE_0,\r
234 250000000\r
235 }, //MAIN_PLL14_HSDIV1_CLKOUT\r
236 \r
237 /* MAIN PLL15 (AUDIO1 PLL) Clockout */ \r
238 { TISCI_DEV_MCASP0,\r
239 TISCI_DEV_MCASP0_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK,\r
240 196608000\r
241 },\r
242 { TISCI_DEV_ATL0,\r
243 TISCI_DEV_ATL0_ATL_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT1_CLK,\r
244 294912000\r
245 },\r
246 { TISCI_DEV_TIMER0,\r
247 TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK,\r
248 196608000\r
249 },\r
250 { TISCI_DEV_AASRC0,\r
251 TISCI_DEV_AASRC0_RX1_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK,\r
252 12288000\r
253 },\r
254 \r
255 /* MAIN PLL25 Clockout */ \r
256 { TISCI_DEV_BOARD0,\r
257 TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK,\r
258 520000000\r
259 }\r
260 };\r
261 \r
262 /**\r
263 * \brief PLL clock enable\r
264 *\r
265 * This function is used to set the PLL Module clock frequency\r
266 *\r
267 * \param moduleId [IN] Module for which the state should be set.\r
268 * Refer Sciclient_PmDeviceIds in sciclient_fmwMsgParams.h\r
269 * \param clockId [IN] Clock Id for the module.\r
270 * Refer Sciclient_PmModuleClockIds in sciclient_fmwMsgParams.h\r
271 * \param clkRate [IN] Value of the clock frequency to be set\r
272 *\r
273 * \return int32_t\r
274 * CSL_PASS - on Success\r
275 * CSL_EFAIL - on Failure\r
276 *\r
277 */\r
278 static int32_t Board_PLLSetModuleClkFreq(uint32_t modId,\r
279 uint32_t clkId,\r
280 uint64_t clkRate)\r
281 {\r
282 uint32_t i = 0U;\r
283 int32_t status = CSL_EFAIL;\r
284 uint64_t respClkRate = 0;\r
285 uint32_t numParents = 0U;\r
286 uint32_t moduleClockParentChanged = 0U;\r
287 uint32_t clockStatus = 0U;\r
288 uint32_t origParent = 0U;\r
289 uint32_t foundParent = 0U;\r
290 \r
291 /* Check if the clock is enabled or not */\r
292 status = Sciclient_pmModuleGetClkStatus(modId,\r
293 clkId,\r
294 &clockStatus,\r
295 SCICLIENT_SERVICE_WAIT_FOREVER);\r
296 if (status == CSL_PASS)\r
297 {\r
298 /* Get the number of parents for the clock */\r
299 status = Sciclient_pmGetModuleClkNumParent(modId,\r
300 clkId,\r
301 &numParents,\r
302 SCICLIENT_SERVICE_WAIT_FOREVER);\r
303 if ((status == CSL_PASS) && (numParents > 1U))\r
304 {\r
305 status = Sciclient_pmGetModuleClkParent(modId, clkId, &origParent,\r
306 SCICLIENT_SERVICE_WAIT_FOREVER);\r
307 }\r
308 }\r
309 if (status == CSL_PASS)\r
310 {\r
311 /* Disabling the clock */\r
312 status = Sciclient_pmModuleClkRequest(\r
313 modId,\r
314 clkId,\r
315 TISCI_MSG_VALUE_CLOCK_SW_STATE_UNREQ,\r
316 0U,\r
317 SCICLIENT_SERVICE_WAIT_FOREVER);\r
318 }\r
319 if (status == CSL_PASS)\r
320 {\r
321 foundParent = 0U;\r
322 /* Try to loop and change parents of the clock */\r
323 for(i=0U;i<numParents;i++)\r
324 {\r
325 if (numParents > 1U)\r
326 {\r
327 /* Setting the new parent */\r
328 status = Sciclient_pmSetModuleClkParent(\r
329 modId,\r
330 clkId,\r
331 clkId+i+1,\r
332 SCICLIENT_SERVICE_WAIT_FOREVER);\r
333 /* Check if the clock can be set to desirable freq. */\r
334 if (status == CSL_PASS)\r
335 {\r
336 moduleClockParentChanged = 1U;\r
337 }\r
338 }\r
339 if (status == CSL_PASS)\r
340 {\r
341 status = Sciclient_pmQueryModuleClkFreq(modId,\r
342 clkId,\r
343 clkRate,\r
344 &respClkRate,\r
345 SCICLIENT_SERVICE_WAIT_FOREVER);\r
346 }\r
347 if ((status == CSL_PASS) && (respClkRate == clkRate))\r
348 {\r
349 foundParent = 1U;\r
350 break;\r
351 }\r
352 }\r
353 }\r
354 if (foundParent == 1U)\r
355 {\r
356 /* Set the clock at the desirable frequency*/\r
357 status = Sciclient_pmSetModuleClkFreq(\r
358 modId,\r
359 clkId,\r
360 clkRate,\r
361 TISCI_MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE,\r
362 SCICLIENT_SERVICE_WAIT_FOREVER);\r
363 }\r
364 else\r
365 {\r
366 status = CSL_EFAIL;\r
367 }\r
368 if ((status == CSL_PASS) &&\r
369 (clockStatus == TISCI_MSG_VALUE_CLOCK_SW_STATE_UNREQ))\r
370 {\r
371 /* Restore the clock again to original state */\r
372 status = Sciclient_pmModuleClkRequest(\r
373 modId,\r
374 clkId,\r
375 clockStatus,\r
376 0U,\r
377 SCICLIENT_SERVICE_WAIT_FOREVER);\r
378 }\r
379 if ((status != CSL_PASS) && (moduleClockParentChanged == 1U))\r
380 {\r
381 /* Setting the original parent if failure */\r
382 status = Sciclient_pmSetModuleClkParent(\r
383 modId,\r
384 clkId,\r
385 origParent,\r
386 SCICLIENT_SERVICE_WAIT_FOREVER);\r
387 }\r
388 return status;\r
389 }\r
390 \r
391 /**\r
392 * \brief Function to initialize module clock frequency\r
393 *\r
394 * \param moduleId [IN] Module for which the state should be set.\r
395 * Refer Sciclient_PmDeviceIds in sciclient_fmwMsgParams.h\r
396 * \param clockId [IN] Clock Id for the module.\r
397 * Refer Sciclient_PmModuleClockIds in sciclient_fmwMsgParams.h\r
398 * \param clkRate [IN] Value of the clock frequency to be set\r
399 \r
400 * \return Board_STATUS\r
401 */\r
402 Board_STATUS Board_PLLInit(uint32_t modId,\r
403 uint32_t clkId,\r
404 uint64_t clkRate)\r
405 {\r
406 int32_t status = CSL_EFAIL;\r
407 \r
408 status = Board_PLLSetModuleClkFreq(modId, clkId, clkRate);\r
409 if(status != CSL_PASS)\r
410 {\r
411 return BOARD_FAIL;\r
412 }\r
413 \r
414 return BOARD_SOK;\r
415 }\r
416 \r
417 /**\r
418 * \brief Function to initialize the MCU domain PLL clocks with default values\r
419 *\r
420 * \return Board_STATUS\r
421 */\r
422 Board_STATUS Board_PLLInitMcu(void)\r
423 {\r
424 Board_STATUS status = BOARD_SOK;\r
425 uint32_t index;\r
426 uint32_t loopCount;\r
427 \r
428 loopCount = sizeof (gBoardPllClkCfgMcu)/sizeof(Board_PllClkCfg_t);\r
429 \r
430 for (index = 0; index < loopCount; index++)\r
431 {\r
432 status = Board_PLLInit(gBoardPllClkCfgMcu[index].tisciDevID,\r
433 gBoardPllClkCfgMcu[index].tisciClkID,\r
434 gBoardPllClkCfgMcu[index].clkRate);\r
435 if(status != BOARD_SOK)\r
436 {\r
437 BOARD_DEBUG_LOG("Failed to set the PLL clock freq at index =%d\n\n",index);\r
438 }\r
439 }\r
440 \r
441 return status;\r
442 }\r
443 \r
444 /**\r
445 * \brief Function to initialize the MAIN domain PLL clocks with default values\r
446 *\r
447 * \return Board_STATUS\r
448 */\r
449 Board_STATUS Board_PLLInitMain(void)\r
450 {\r
451 Board_STATUS status = BOARD_SOK;\r
452 uint32_t index;\r
453 uint32_t loopCount;\r
454 \r
455 loopCount = sizeof (gBoardPllClkCfgMain)/sizeof(Board_PllClkCfg_t);\r
456 \r
457 for (index = 0; index < loopCount; index++)\r
458 {\r
459 status = Board_PLLInit(gBoardPllClkCfgMain[index].tisciDevID,\r
460 gBoardPllClkCfgMain[index].tisciClkID,\r
461 gBoardPllClkCfgMain[index].clkRate);\r
462 if(status != BOARD_SOK)\r
463 {\r
464 BOARD_DEBUG_LOG("Failed to set the PLL clock freq at index =%d\n\n",index);\r
465 }\r
466 }\r
467 \r
468 return status;\r
469 }\r
470 \r