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33 /**\r
34 * \file board_serdes_cfg.c\r
35 *\r
36 * \brief EVM serdes configuration file\r
37 *\r
38 * Configures the serdes module.\r
39 *\r
40 */\r
41 \r
42 #include "board_serdes_cfg.h"\r
43 \r
44 static Board_STATUS Board_CfgSgmii(void)\r
45 {\r
46 CSL_SerdesResult result;\r
47 CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
48 CSL_SerdesLaneEnableParams serdesLaneEnableParams = {0};\r
49 \r
50 memset(&serdesLaneEnableParams, 0, sizeof(serdesLaneEnableParams));\r
51 \r
52 /* SGMII Config */\r
53 serdesLaneEnableParams.serdesInstance = (CSL_SerdesInstance)BOARD_SERDES_SGMII_INSTANCE;\r
54 serdesLaneEnableParams.baseAddr = CSL_WIZ16B8M4CT3_2_WIZ16B8M4CT3_BASE;\r
55 serdesLaneEnableParams.refClock = CSL_SERDES_REF_CLOCK_100M;\r
56 serdesLaneEnableParams.refClkSrc = CSL_SERDES_REF_CLOCK_INT0;\r
57 serdesLaneEnableParams.linkRate = CSL_SERDES_LINK_RATE_1p25G;\r
58 serdesLaneEnableParams.numLanes = BOARD_SERDES_SGMII_ENET1_LANE_COUNT;\r
59 serdesLaneEnableParams.laneMask = BOARD_SERDES_SGMII_ENET1_LANE_MASK;\r
60 serdesLaneEnableParams.SSC_mode = CSL_SERDES_NO_SSC;\r
61 serdesLaneEnableParams.phyType = CSL_SERDES_PHY_TYPE_SGMII;\r
62 serdesLaneEnableParams.operatingMode = CSL_SERDES_FUNCTIONAL_MODE;\r
63 serdesLaneEnableParams.phyInstanceNum = BOARD_SERDES_LANE_SELECT_CPSW;\r
64 serdesLaneEnableParams.pcieGenType = CSL_SERDES_PCIE_GEN3;\r
65 \r
66 serdesLaneEnableParams.laneCtrlRate[BOARD_SERDES_SGMII_ENET1_LANE_NUM] = CSL_SERDES_LANE_FULL_RATE;\r
67 serdesLaneEnableParams.loopbackMode[BOARD_SERDES_SGMII_ENET1_LANE_NUM] = CSL_SERDES_LOOPBACK_DISABLED;\r
68 \r
69 CSL_serdesPorReset(serdesLaneEnableParams.baseAddr);\r
70 \r
71 /* Select the IP type, IP instance num, Serdes Lane Number */\r
72 CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,\r
73 serdesLaneEnableParams.phyType,\r
74 serdesLaneEnableParams.phyInstanceNum,\r
75 serdesLaneEnableParams.serdesInstance,\r
76 BOARD_SERDES_SGMII_ENET1_LANE_NUM);\r
77 \r
78 \r
79 result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,\r
80 serdesLaneEnableParams.baseAddr,\r
81 serdesLaneEnableParams.refClock,\r
82 serdesLaneEnableParams.refClkSrc,\r
83 serdesLaneEnableParams.serdesInstance,\r
84 serdesLaneEnableParams.phyType);\r
85 \r
86 if (result != CSL_SERDES_NO_ERR)\r
87 {\r
88 return BOARD_FAIL;\r
89 }\r
90 /* Assert PHY reset and disable all lanes */\r
91 CSL_serdesDisablePllAndLanes(serdesLaneEnableParams.baseAddr,\r
92 serdesLaneEnableParams.numLanes,\r
93 serdesLaneEnableParams.laneMask);\r
94 \r
95 /* Load the Serdes Config File */\r
96 result = CSL_serdesEthernetInit(&serdesLaneEnableParams);\r
97 /* Return error if input params are invalid */\r
98 if (result != CSL_SERDES_NO_ERR)\r
99 {\r
100 return BOARD_FAIL;\r
101 }\r
102 \r
103 /* Common Lane Enable API for lane enable, pll enable etc */\r
104 laneRetVal = CSL_serdesLaneEnable(&serdesLaneEnableParams);\r
105 if (laneRetVal != 0)\r
106 {\r
107 return BOARD_FAIL;\r
108 }\r
109 \r
110 return BOARD_SOK;\r
111 }\r
112 \r
113 static Board_STATUS Board_CfgQsgmii(void)\r
114 {\r
115 CSL_SerdesResult result;\r
116 CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
117 CSL_SerdesLaneEnableParams serdesLaneEnableParams = {0};\r
118 \r
119 memset(&serdesLaneEnableParams, 0, sizeof(serdesLaneEnableParams));\r
120 \r
121 /* QSGMII Config */\r
122 serdesLaneEnableParams.serdesInstance = (CSL_SerdesInstance)BOARD_SERDES_SGMII_INSTANCE;\r
123 serdesLaneEnableParams.baseAddr = CSL_WIZ16B8M4CT3_2_WIZ16B8M4CT3_BASE;\r
124 serdesLaneEnableParams.refClock = CSL_SERDES_REF_CLOCK_100M;\r
125 serdesLaneEnableParams.refClkSrc = CSL_SERDES_REF_CLOCK_INT0;\r
126 serdesLaneEnableParams.linkRate = CSL_SERDES_LINK_RATE_5G;\r
127 serdesLaneEnableParams.numLanes = BOARD_SERDES_SGMII_ENET1_LANE_COUNT;\r
128 serdesLaneEnableParams.laneMask = BOARD_SERDES_SGMII_ENET1_LANE_MASK;\r
129 serdesLaneEnableParams.SSC_mode = CSL_SERDES_NO_SSC;\r
130 serdesLaneEnableParams.phyType = CSL_SERDES_PHY_TYPE_QSGMII;\r
131 serdesLaneEnableParams.operatingMode = CSL_SERDES_FUNCTIONAL_MODE;\r
132 serdesLaneEnableParams.phyInstanceNum = BOARD_SERDES_LANE_SELECT_CPSW;\r
133 serdesLaneEnableParams.pcieGenType = CSL_SERDES_PCIE_GEN4;\r
134 \r
135 serdesLaneEnableParams.laneCtrlRate[BOARD_SERDES_SGMII_ENET1_LANE_NUM] = CSL_SERDES_LANE_FULL_RATE;\r
136 serdesLaneEnableParams.loopbackMode[BOARD_SERDES_SGMII_ENET1_LANE_NUM] = CSL_SERDES_LOOPBACK_DISABLED;\r
137 \r
138 CSL_serdesPorReset(serdesLaneEnableParams.baseAddr);\r
139 \r
140 /* Select the IP type, IP instance num, Serdes Lane Number */\r
141 CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,\r
142 serdesLaneEnableParams.phyType,\r
143 serdesLaneEnableParams.phyInstanceNum,\r
144 serdesLaneEnableParams.serdesInstance,\r
145 BOARD_SERDES_SGMII_ENET1_LANE_NUM);\r
146 \r
147 \r
148 result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,\r
149 serdesLaneEnableParams.baseAddr,\r
150 serdesLaneEnableParams.refClock,\r
151 serdesLaneEnableParams.refClkSrc,\r
152 serdesLaneEnableParams.serdesInstance,\r
153 serdesLaneEnableParams.phyType);\r
154 \r
155 if (result != CSL_SERDES_NO_ERR)\r
156 {\r
157 return BOARD_FAIL;\r
158 }\r
159 \r
160 /* Load the Serdes Config File */\r
161 result = CSL_serdesEthernetInit(&serdesLaneEnableParams);\r
162 /* Return error if input params are invalid */\r
163 if (result != CSL_SERDES_NO_ERR)\r
164 {\r
165 return BOARD_FAIL;\r
166 }\r
167 \r
168 /* Common Lane Enable API for lane enable, pll enable etc */\r
169 laneRetVal = CSL_serdesLaneEnable(&serdesLaneEnableParams);\r
170 if (laneRetVal != 0)\r
171 {\r
172 return BOARD_FAIL;\r
173 }\r
174 \r
175 return BOARD_SOK;\r
176 }\r
177 \r
178 static Board_STATUS Board_serdesCfgEthernetUsxgmii(void)\r
179 {\r
180 CSL_SerdesResult result;\r
181 CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
182 CSL_SerdesLaneEnableParams serdesLaneEnableParams;\r
183 \r
184 memset(&serdesLaneEnableParams, 0, sizeof(serdesLaneEnableParams));\r
185 \r
186 /* Serdes-2: Lane 3 (MAC Port 8) */\r
187 serdesLaneEnableParams.serdesInstance = (CSL_SerdesInstance)BOARD_SERDES_SGMII_INSTANCE;\r
188 serdesLaneEnableParams.baseAddr = CSL_WIZ16B8M4CT3_2_WIZ16B8M4CT3_BASE;\r
189 serdesLaneEnableParams.refClock = CSL_SERDES_REF_CLOCK_156p25M;\r
190 serdesLaneEnableParams.refClkSrc = CSL_SERDES_REF_CLOCK_INT0;\r
191 serdesLaneEnableParams.numLanes = BOARD_SERDES_SGMII_ENET2_LANE_COUNT;\r
192 serdesLaneEnableParams.laneMask = BOARD_SERDES_SGMII_ENET2_LANE_MASK;\r
193 serdesLaneEnableParams.SSC_mode = CSL_SERDES_NO_SSC;\r
194 serdesLaneEnableParams.phyType = CSL_SERDES_PHY_TYPE_USXGMII;\r
195 serdesLaneEnableParams.operatingMode = CSL_SERDES_FUNCTIONAL_MODE;\r
196 serdesLaneEnableParams.phyInstanceNum = BOARD_SERDES_LANE_SELECT_CPSW;\r
197 \r
198 serdesLaneEnableParams.laneCtrlRate[BOARD_SERDES_SGMII_ENET2_LANE_NUM] = CSL_SERDES_LANE_FULL_RATE;\r
199 serdesLaneEnableParams.loopbackMode[BOARD_SERDES_SGMII_ENET2_LANE_NUM] = CSL_SERDES_LOOPBACK_DISABLED;\r
200 \r
201 serdesLaneEnableParams.pcieGenType = CSL_SERDES_PCIE_GEN4;\r
202 serdesLaneEnableParams.linkRate = CSL_SERDES_LINK_RATE_5p15625G;\r
203 /* End: Serdes-2: Lane 3 (MAC Port 8) */\r
204 \r
205 CSL_serdesPorReset(serdesLaneEnableParams.baseAddr);\r
206 \r
207 /* Select the IP type, IP instance num, Serdes Lane Number */\r
208 CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,\r
209 serdesLaneEnableParams.phyType,\r
210 serdesLaneEnableParams.phyInstanceNum,\r
211 serdesLaneEnableParams.serdesInstance,\r
212 BOARD_SERDES_SGMII_ENET2_LANE_NUM);\r
213 \r
214 result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,\r
215 serdesLaneEnableParams.baseAddr,\r
216 serdesLaneEnableParams.refClock,\r
217 serdesLaneEnableParams.refClkSrc,\r
218 serdesLaneEnableParams.serdesInstance,\r
219 serdesLaneEnableParams.phyType);\r
220 \r
221 if (result != CSL_SERDES_NO_ERR)\r
222 {\r
223 return BOARD_FAIL;\r
224 }\r
225 \r
226 /* Load the Serdes Config File */\r
227 result = CSL_serdesEthernetInit(&serdesLaneEnableParams);\r
228 /* Return error if input params are invalid */\r
229 if (result != CSL_SERDES_NO_ERR)\r
230 {\r
231 return BOARD_FAIL;\r
232 }\r
233 \r
234 /* Common Lane Enable API for lane enable, pll enable etc */\r
235 laneRetVal = CSL_serdesLaneEnable(&serdesLaneEnableParams);\r
236 if (laneRetVal != 0)\r
237 {\r
238 return BOARD_FAIL;\r
239 }\r
240 \r
241 return BOARD_SOK;\r
242 }\r
243 \r
244 /**\r
245 * \brief serdes configurations for Sierra 1 in SGMII mode\r
246 *\r
247 * The function configures the serdes module for SGMII instance\r
248 *\r
249 * \return BOARD_SOK in case of success or appropriate error code\r
250 *\r
251 */\r
252 Board_STATUS Board_serdesCfgSgmii(void)\r
253 {\r
254 Board_STATUS ret;\r
255 \r
256 /* SGMII SERDES initializations */\r
257 ret = Board_CfgSgmii();\r
258 if(ret != BOARD_SOK)\r
259 {\r
260 return ret;\r
261 }\r
262 \r
263 return BOARD_SOK;\r
264 }\r
265 \r
266 /**\r
267 * \brief serdes configurations for Sierra 1 in QSGMII mode\r
268 *\r
269 * The function configures the serdes module for QSGMII instances\r
270 *\r
271 * \return BOARD_SOK in case of success or appropriate error code\r
272 *\r
273 */\r
274 Board_STATUS Board_serdesCfgQsgmii(void)\r
275 {\r
276 Board_STATUS ret;\r
277 \r
278 /* QSGMII SERDES initializations */\r
279 ret = Board_CfgQsgmii();\r
280 if(ret != BOARD_SOK)\r
281 {\r
282 return ret;\r
283 }\r
284 \r
285 return BOARD_SOK;\r
286 }\r
287 \r
288 /**\r
289 * \brief serdes configurations for USXGMII mode\r
290 *\r
291 * The function configures the serdes module for USXGMII interface\r
292 *\r
293 * \return BOARD_SOK in case of success or appropriate error code\r
294 *\r
295 */\r
296 Board_STATUS Board_serdesCfgUsxgmii(void)\r
297 {\r
298 Board_STATUS ret;\r
299 \r
300 /* USXGMII SERDES initializations */\r
301 ret = Board_serdesCfgEthernetUsxgmii();\r
302 if(ret != BOARD_SOK)\r
303 {\r
304 return ret;\r
305 }\r
306 \r
307 return BOARD_SOK;\r
308 }\r
309 \r
310 /**\r
311 * \brief Query SerDes configuration status\r
312 *\r
313 * The function gets the configuration status of Torrent SerDes module.\r
314 *\r
315 * \retval TRUE SerDes1 is configured\r
316 * \retval FALSE SerDes1 is not configured\r
317 */\r
318 int32_t Board_serdesCfgStatus(void)\r
319 {\r
320 CSL_SerdesStatus serdesStatus;\r
321 int32_t ret = FALSE;\r
322 \r
323 serdesStatus = CSL_serdesConfigStatus(CSL_WIZ16B8M4CT3_2_WIZ16B8M4CT3_BASE);\r
324 if (serdesStatus == CSL_SERDES_STATUS_PLL_LOCKED)\r
325 {\r
326 ret = TRUE;\r
327 }\r
328 \r
329 return ret;\r
330 }\r