1 /**
2 * \file sbl_main.c
3 *
4 * \brief This file contain main function, call the Board Initialization
5 * functions & slave core boot-up functions in sequence.
6 *
7 */
9 /*
10 * Copyright (C) 2018-2022 Texas Instruments Incorporated - http://www.ti.com/
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 *
16 * Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 *
19 * Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the
22 * distribution.
23 *
24 * Neither the name of Texas Instruments Incorporated nor the names of
25 * its contributors may be used to endorse or promote products derived
26 * from this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 */
42 /* TI RTOS header files */
43 #include "sbl_main.h"
44 #include <ti/csl/cslr_gtc.h>
46 /**********************************************************************
47 ************************** Macros ************************************
48 **********************************************************************/
50 /**********************************************************************
51 ************************** Internal functions ************************
52 **********************************************************************/
54 /**********************************************************************
55 ************************** Global Variables **************************
56 **********************************************************************/
57 extern sblProfileInfo_t sblProfileLog[MAX_PROFILE_LOG_ENTRIES];
58 extern uint32_t sblProfileLogIndx;
59 extern uint32_t sblProfileLogOvrFlw;
61 volatile sblProfileInfo_t * sblProfileLogAddr __attribute__((section(".sbl_profile_info")));
63 volatile uint32_t *sblProfileLogIndxAddr __attribute__((section(".sbl_profile_info")));
65 volatile uint32_t *sblProfileLogOvrFlwAddr __attribute__((section(".sbl_profile_info")));
67 sblEntryPoint_t k3xx_evmEntry;
68 #if defined(SOC_AM64X)
69 const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =
70 {
71 {
72 /* Region 0 configuration: complete 32 bit address space = 4Gbits */
73 .regionId = 0U,
74 .enable = 1U,
75 .baseAddr = 0x0U,
76 .size = CSL_ARM_R5_MPU_REGION_SIZE_4GB,
77 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
78 .exeNeverControl = 1U,
79 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
80 .shareable = 0U,
81 .cacheable = (uint32_t)FALSE,
82 .cachePolicy = 0U,
83 .memAttr = 0U,
84 },
85 {
86 /* Region 1 configuration: 64K bytes ATCM for exception vector execution */
87 .regionId = 1U,
88 .enable = 1U,
89 .baseAddr = 0x0U,
90 .size = CSL_ARM_R5_MPU_REGION_SIZE_32KB,
91 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
92 .exeNeverControl = 0U,
93 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
94 .shareable = 0U,
95 .cacheable = (uint32_t)TRUE,
96 .cachePolicy = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
97 .memAttr = 0U,
98 },
99 {
100 /* Region 2 configuration: 2 MB MCMS3 RAM */
101 .regionId = 2U,
102 .enable = 1U,
103 .baseAddr = 0x70000000,
104 .size = CSL_ARM_R5_MPU_REGION_SIZE_2MB,
105 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
106 .exeNeverControl = 0U,
107 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
108 .shareable = 0U,
109 .cacheable = (uint32_t)TRUE,
110 .cachePolicy = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
111 .memAttr = 0U,
112 },
113 {
114 /* Region 3 configuration: 2 GB DDR RAM */
115 .regionId = 3U,
116 .enable = 1U,
117 .baseAddr = 0x80000000,
118 .size = CSL_ARM_R5_MPU_REGION_SIZE_2GB,
119 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
120 .exeNeverControl = 0U,
121 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
122 .shareable = 0U,
123 .cacheable = (uint32_t)TRUE,
124 .cachePolicy = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
125 .memAttr = 0U,
126 },
127 {
128 /* Region 4 configuration: 64 KB BTCM */
129 .regionId = 4U,
130 .enable = 1U,
131 .baseAddr = 0x41010000,
132 .size = CSL_ARM_R5_MPU_REGION_SIZE_32KB,
133 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
134 .exeNeverControl = 0U,
135 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
136 .shareable = 0U,
137 .cacheable = (uint32_t)TRUE,
138 .cachePolicy = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
139 .memAttr = 0U,
140 },
141 {
142 /* Region 5 configuration: 128 MB FSS DAT0 */
143 .regionId = 5U,
144 .enable = 1U,
145 .baseAddr = 0x60000000,
146 .size = CSL_ARM_R5_MPU_REGION_SIZE_128MB,
147 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
148 .exeNeverControl = 0U,
149 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
150 .shareable = 0U,
151 .cacheable = (uint32_t)TRUE,
152 .cachePolicy = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
153 .memAttr = 0U,
154 },
155 {
156 /* Region 6 configuration (Non-cached for PHY tuning data): Covers last 256KB of EVM Flash (FSS DAT0) */
157 .regionId = 6U,
158 .enable = 1U,
159 .baseAddr = 0x63FC0000,
160 .size = CSL_ARM_R5_MPU_REGION_SIZE_256KB,
161 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
162 .exeNeverControl = 0U,
163 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
164 .shareable = 0U,
165 /* OSPI PHY tuning algorithm which runs in DAC mode needs
166 * cache to be disabled for this section of FSS data region.
167 */
168 .cacheable = (uint32_t)FALSE,
169 .cachePolicy = 0U,
170 .memAttr = 0U,
171 },
172 {
173 /* Region 7 configuration: Covers the M4F memory regions */
174 .regionId = 7U,
175 .enable = 1U,
176 .baseAddr = 0x5000000,
177 .size = CSL_ARM_R5_MPU_REGION_SIZE_512KB,
178 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
179 .exeNeverControl = 0U,
180 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
181 .shareable = 0U,
182 .cacheable = (uint32_t)TRUE,
183 .cachePolicy = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
184 .memAttr = 0U,
185 }
186 };
187 #else
188 const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =
189 {
190 {
191 /* Region 0 configuration: complete 32 bit address space = 4Gbits */
192 .regionId = 0U,
193 .enable = 1U,
194 .baseAddr = 0x0U,
195 .size = CSL_ARM_R5_MPU_REGION_SIZE_4GB,
196 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
197 .exeNeverControl = 1U,
198 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
199 .shareable = 0U,
200 .cacheable = (uint32_t)FALSE,
201 .cachePolicy = 0U,
202 .memAttr = 0U,
203 },
204 {
205 /* Region 1 configuration: 128 bytes memory for exception vector execution */
206 .regionId = 1U,
207 .enable = 1U,
208 .baseAddr = 0x0U,
209 .size = CSL_ARM_R5_MPU_REGION_SIZE_32KB,
210 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
211 .exeNeverControl = 0U,
212 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
213 .shareable = 0U,
214 .cacheable = (uint32_t)TRUE,
215 .cachePolicy = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
216 .memAttr = 0U,
217 },
218 {
219 /* Region 2 configuration: 1 MB OCMS RAM - Covers RAM sizes for multiple SoCs */
220 .regionId = 2U,
221 .enable = 1U,
222 .baseAddr = 0x41C00000,
223 .size = CSL_ARM_R5_MPU_REGION_SIZE_1MB,
224 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
225 .exeNeverControl = 0U,
226 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
227 .shareable = 0U,
228 .cacheable = (uint32_t)TRUE,
229 .cachePolicy = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
230 .memAttr = 0U,
231 },
232 {
233 /* Region 3 configuration: 2 MB MCMS3 RAM */
234 .regionId = 3U,
235 .enable = 1U,
236 .baseAddr = 0x70000000,
237 .size = CSL_ARM_R5_MPU_REGION_SIZE_8MB,
238 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
239 .exeNeverControl = 0U,
240 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
241 .shareable = 0U,
242 .cacheable = (uint32_t)TRUE,
243 .cachePolicy = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
244 .memAttr = 0U,
245 },
246 {
247 /* Region 4 configuration: 2 GB DDR RAM */
248 .regionId = 4U,
249 .enable = 1U,
250 .baseAddr = 0x80000000,
251 .size = CSL_ARM_R5_MPU_REGION_SIZE_2GB,
252 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
253 .exeNeverControl = 0U,
254 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
255 .shareable = 0U,
256 .cacheable = (uint32_t)TRUE,
257 .cachePolicy = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
258 .memAttr = 0U,
259 },
260 {
261 /* Region 5 configuration: 64 KB BTCM */
262 .regionId = 5U,
263 .enable = 1U,
264 .baseAddr = 0x41010000,
265 .size = CSL_ARM_R5_MPU_REGION_SIZE_32KB,
266 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
267 .exeNeverControl = 0U,
268 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
269 .shareable = 0U,
270 .cacheable = (uint32_t)TRUE,
271 .cachePolicy = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
272 .memAttr = 0U,
273 },
274 {
275 /* Region 6 configuration: Covers first 64MB of EVM Flash (FSS DAT0) */
276 .regionId = 6U,
277 .enable = 1U,
278 .baseAddr = 0x50000000,
279 .size = CSL_ARM_R5_MPU_REGION_SIZE_64MB,
280 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
281 .exeNeverControl = 0U,
282 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
283 .shareable = 0U,
284 .cacheable = (uint32_t)TRUE,
285 .cachePolicy = CSL_ARM_R5_CACHE_POLICY_WB_WA,
286 .memAttr = 0U,
287 },
288 {
289 /* Region 14 configuration (Non-cached for PHY tuning data): Covers last 256KB of EVM Flash (FSS DAT0) */
290 .regionId = 7U,
291 .enable = 1U,
292 #if defined(SOC_J7200) || defined(SOC_J721S2) || defined(SOC_J784S4)
293 .baseAddr = 0x53FC0000,
294 .size = CSL_ARM_R5_MPU_REGION_SIZE_256KB,
295 #else
296 .baseAddr = 0x53FE0000,
297 .size = CSL_ARM_R5_MPU_REGION_SIZE_128KB,
298 #endif
299 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
300 .exeNeverControl = 0U,
301 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
302 .shareable = 0U,
303 /* OSPI PHY tuning algorithm which runs in DAC mode needs
304 * cache to be disabled for this section of FSS data region.
305 */
306 .cacheable = (uint32_t)FALSE,
307 .cachePolicy = 0U,
308 .memAttr = 0U,
309 },
310 {
311 /* Region 15 configuration: 128 MB FSS DAT1 */
312 .regionId = 8U,
313 .enable = 1U,
314 .baseAddr = 0x58000000,
315 .size = CSL_ARM_R5_MPU_REGION_SIZE_128MB,
316 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
317 .exeNeverControl = 0U,
318 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
319 .shareable = 0U,
320 .cacheable = (uint32_t)TRUE,
321 .cachePolicy = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
322 .memAttr = 0U,
323 },
324 #if defined(SOC_J721E)
325 {
326 /* Region 9 configuration: 512KB Main OCMRAM - no need for mapping */
327 .regionId = 9U,
328 .enable = 1U,
329 .baseAddr = 0x03600000,
330 .size = CSL_ARM_R5_MPU_REGION_SIZE_512KB,
331 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
332 .exeNeverControl = 0U,
333 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
334 .shareable = 0U,
335 .cacheable = (uint32_t)TRUE,
336 .cachePolicy = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
337 .memAttr = 0U,
338 },
339 #endif
340 #if defined(SBL_OCM_MAIN_DOMAIN_RAT) && defined(SOC_J7200)
341 {
342 /* Region 10 configuration: 512KB Virtually Mapped Main OCMRAM */
343 .regionId = 10U,
344 .enable = 1U,
345 .baseAddr = 0xD0000000,
346 .size = CSL_ARM_R5_MPU_REGION_SIZE_1MB,
347 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
348 .exeNeverControl = 0U,
349 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
350 .shareable = 0U,
351 .cacheable = (uint32_t)TRUE,
352 .cachePolicy = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
353 .memAttr = 0U,
354 },
355 #endif
357 };
359 #endif
360 int main()
361 {
362 #if defined(SBL_ENABLE_HLOS_BOOT) && (defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_J721S2) || defined(SOC_J784S4))
363 cpu_core_id_t core_id;
364 #endif
365 uint32_t atcm_size;
367 SBL_ADD_PROFILE_POINT;
369 /* Any SoC specific Init. */
370 SBL_SocEarlyInit();
372 if (SBL_LOG_LEVEL > SBL_LOG_ERR)
373 {
374 /* Configure UART Tx pinmux. */
375 Board_uartTxPinmuxConfig();
376 }
378 SBL_ADD_PROFILE_POINT;
380 if (SBL_LOG_LEVEL > SBL_LOG_NONE)
381 {
382 UART_HwAttrs uart_cfg;
384 UART_socGetInitCfg(BOARD_UART_INSTANCE, &uart_cfg);
385 /* Use UART fclk freq setup by ROM */
386 uart_cfg.frequency = SBL_ROM_UART_MODULE_INPUT_CLK;
387 /* Disable the UART interrupt */
388 uart_cfg.enableInterrupt = FALSE;
389 UART_socSetInitCfg(BOARD_UART_INSTANCE, &uart_cfg);
390 /* Init UART for logging. */
391 UART_stdioInit(BOARD_UART_INSTANCE);
392 }
394 SBL_ADD_PROFILE_POINT;
396 SBL_log(SBL_LOG_MIN, "%s (%s - %s)\n", SBL_VERSION_STR, __DATE__, __TIME__);
398 SBL_ADD_PROFILE_POINT;
400 /* Initialize the ATCM */
401 atcm_size = sblAtcmSize();
402 memset((void *)SBL_MCU_ATCM_BASE, 0xFF, atcm_size);
404 /* Relocate CSL Vectors to ATCM*/
405 memcpy((void *)SBL_MCU_ATCM_BASE, (void *)_resetvectors, 0x100);
407 SBL_ADD_PROFILE_POINT;
409 #if defined(SBL_OCM_MAIN_DOMAIN_RAT)
410 /* Setup RAT to load data into MCU2_0 OCM RAM for MCU1_0 */
411 /* This is mapping the OCM RAM for MCU2_0 (a 40 bit address) Main domain to 0xD0000000 */
412 SBL_log(SBL_LOG_MAX, "Initializing RAT ...");
413 #define RAT_BASE (0x40F90000)
414 #define REGION_ID (0x0)
415 *(unsigned int *)(RAT_BASE + 0x44 + (REGION_ID*0x10)) = 0xD0000000; //IN ADDRESS
416 *(unsigned int *)(RAT_BASE + 0x48 + (REGION_ID*0x10)) = 0x02000000;
417 *(unsigned int *)(RAT_BASE + 0x4C + (REGION_ID*0x10)) = 0x0000004F; //Upper 16 bits of the real physical address.
418 *(unsigned int *)(RAT_BASE + 0x40 + (REGION_ID*0x10)) = 0x80000013;
419 SBL_log(SBL_LOG_MAX, "done.\n");
420 #endif
422 SBL_ADD_PROFILE_POINT;
424 /* Load SYSFW. */
425 SBL_SciClientInit();
427 SBL_ADD_PROFILE_POINT;
429 #if !defined(SBL_SKIP_PINMUX_ENABLE)
430 /* Board pinmux. */
431 #if defined(SOC_AM64X)
432 /* AM64x should not re-configure Pinmux on reset */
433 uint32_t mmrResetRegister = (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE+CSL_MAIN_CTRL_MMR_CFG0_RST_SRC_PROXY)));
435 uint32_t mmrResetMask = CSL_MAIN_CTRL_MMR_CFG0_RST_SRC_PROXY_RST_SRC_MAIN_RESET_REQ_PROXY_MASK
436 | CSL_MAIN_CTRL_MMR_CFG0_RST_SRC_PROXY_RST_SRC_WARM_OUT_RST_PROXY_MASK
437 | CSL_MAIN_CTRL_MMR_CFG0_RST_SRC_PROXY_RST_SRC_SW_MCU_WARMRST_PROXY_MASK
438 | CSL_MAIN_CTRL_MMR_CFG0_RST_SRC_PROXY_RST_SRC_SW_MAIN_WARMRST_FROM_MCU_PROXY_MASK
439 | CSL_MAIN_CTRL_MMR_CFG0_RST_SRC_PROXY_RST_SRC_SW_MAIN_WARMRST_FROM_MAIN_PROXY_MASK
440 | CSL_MAIN_CTRL_MMR_CFG0_RST_SRC_PROXY_RST_SRC_MAIN_ESM_ERROR_PROXY_MASK;
442 if (mmrResetRegister & mmrResetMask)
443 {
444 /* Do not do PinMux */
445 SBL_log(SBL_LOG_MAX, "SKIPPING PINMUX ENABLE\n");
446 }
447 else
448 {
449 SBL_log(SBL_LOG_MAX, "ENABLING PINMUX\n");
450 Board_init(BOARD_INIT_PINMUX_CONFIG);
451 }
452 #else
453 Board_init(BOARD_INIT_PINMUX_CONFIG);
454 #endif
456 #endif
458 #if !defined(SBL_SKIP_LATE_INIT)
459 SBL_ADD_PROFILE_POINT;
460 /* Any SoC specific Init. */
461 SBL_SocLateInit();
462 #endif
464 #if defined(SBL_ENABLE_PLL) && !defined(SBL_SKIP_SYSFW_INIT)
465 SBL_log(SBL_LOG_MAX, "Initlialzing PLLs ...");
466 SBL_ADD_PROFILE_POINT;
467 Board_init(SBL_PLL_INIT);
468 SBL_log(SBL_LOG_MAX, "done.\n");
469 #endif
471 #if defined(SBL_ENABLE_CLOCKS) && !defined(SBL_SKIP_SYSFW_INIT)
472 SBL_log(SBL_LOG_MAX, "InitlialzingClocks ...");
473 SBL_ADD_PROFILE_POINT;
474 #if defined(SBL_ENABLE_HLOS_BOOT)
475 #if defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_J721S2) || defined(SOC_J784S4) || defined(SOC_AM64X)
476 Board_initParams_t initParams;
477 Board_getInitParams(&initParams);
478 initParams.mainClkGrp = BOARD_MAIN_CLOCK_GROUP1;
479 initParams.mcuClkGrp = BOARD_MCU_CLOCK_GROUP1;
480 Board_setInitParams(&initParams);
481 #endif
482 #endif
483 Board_init(SBL_CLOCK_INIT);
485 SBL_log(SBL_LOG_MAX, "done.\n");
486 #endif
488 #if defined(SBL_ENABLE_DDR) && defined(SBL_ENABLE_PLL) && defined(SBL_ENABLE_CLOCKS) && !defined(SBL_SKIP_SYSFW_INIT)
489 SBL_log(SBL_LOG_MAX, "Initlialzing DDR ...");
490 SBL_ADD_PROFILE_POINT;
491 Board_init(BOARD_INIT_DDR);
492 SBL_log(SBL_LOG_MAX, "done.\n");
493 #endif
495 #if defined(SBL_ENABLE_SERDES)
496 SBL_log(SBL_LOG_MAX, "Initlialzing SERDES ...");
497 Board_init(BOARD_INIT_SERDES_PHY);
498 SBL_log(SBL_LOG_MAX, "done.\n");
499 #endif
501 #if !defined(SBL_USE_MCU_DOMAIN_ONLY) && !defined(SBL_ENABLE_DEV_GRP_MCU)
502 /* Enable GTC */
503 SBL_log(SBL_LOG_MAX, "Initializing GTC ...");
504 volatile uint32_t *gtcRegister = (uint32_t *) CSL_GTC0_GTC_CFG1_BASE;
505 *gtcRegister = *gtcRegister | CSL_GTC_CFG1_CNTCR_EN_MASK | CSL_GTC_CFG1_CNTCR_HDBG_MASK;
507 #if defined(SOC_J721E) || (!defined(SBL_ENABLE_HLOS_BOOT) && defined(SOC_J7200))
508 /* Configure external Ethernet PHY and pinmux */
509 SBL_ConfigureEthernet();
510 #endif
511 #endif
513 SBL_log(SBL_LOG_MAX, "Begin parsing user application\n");
515 /* Boot all non-SBL cores in multi-core app image */
516 SBL_BootImage(&k3xx_evmEntry);
518 /* Export SBL logs */
519 sblProfileLogAddr = sblProfileLog;
520 sblProfileLogIndxAddr = &sblProfileLogIndx;
521 sblProfileLogOvrFlwAddr = &sblProfileLogOvrFlw;
523 #if defined(SBL_ENABLE_HLOS_BOOT) && (defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_J721S2) || defined(SOC_J784S4))
524 /* For J721E/J7200/J721S2/J784S4 we have to manage all core boots at the end, to load mcu1_0 sciserver app */
525 for(core_id = MCU2_CPU0_ID; core_id <= SBL_LAST_CORE_ID; core_id ++)
526 {
527 /* Try booting all MAIN domain cores except the Cortex-A cores */
528 if (k3xx_evmEntry.CpuEntryPoint[core_id] != SBL_INVALID_ENTRY_ADDR)
529 SBL_SlaveCoreBoot(core_id, (uint32_t)NULL, &k3xx_evmEntry, SBL_REQUEST_CORE);
530 }
532 Board_releaseResource(BOARD_RESOURCE_MODULE_CLOCK);
534 /* Boot the HLOS on the Cortex-A cores towards the end */
535 for(core_id = MPU1_CPU0_ID; core_id <= MPU2_CPU3_ID; core_id ++)
536 {
537 /* Try booting all cores other than the cluster running the SBL */
538 if (k3xx_evmEntry.CpuEntryPoint[core_id] != SBL_INVALID_ENTRY_ADDR)
539 SBL_SlaveCoreBoot(core_id, (uint32_t)NULL, &k3xx_evmEntry, SBL_REQUEST_CORE);
540 }
541 #endif
543 #if defined(SBL_ENABLE_HLOS_BOOT) && defined(SOC_AM64X)
544 Board_releaseResource(BOARD_RESOURCE_MODULE_CLOCK);
545 #endif
547 /* Boot the core running SBL in the end */
548 if ((k3xx_evmEntry.CpuEntryPoint[MCU1_CPU1_ID] != SBL_INVALID_ENTRY_ADDR) ||
549 (k3xx_evmEntry.CpuEntryPoint[MCU1_CPU0_ID] < SBL_INVALID_ENTRY_ADDR))
550 {
551 SBL_SlaveCoreBoot(MCU1_CPU0_ID, 0, &k3xx_evmEntry, SBL_REQUEST_CORE);
552 SBL_SlaveCoreBoot(MCU1_CPU1_ID, 0, &k3xx_evmEntry, SBL_REQUEST_CORE);
553 }
555 /* Execute a WFI */
556 asm volatile (" wfi");
558 return 0;
559 }