1 /**
2 * \file sbl_main.c
3 *
4 * \brief This file contain main function, call the Board Initialization
5 * functions & slave core boot-up functions in sequence.
6 *
7 */
9 /*
10 * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 *
16 * Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 *
19 * Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the
22 * distribution.
23 *
24 * Neither the name of Texas Instruments Incorporated nor the names of
25 * its contributors may be used to endorse or promote products derived
26 * from this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 */
42 /* TI RTOS header files */
43 #include "sbl_main.h"
44 #include <ti/csl/cslr_gtc.h>
46 /**********************************************************************
47 ************************** Macros ************************************
48 **********************************************************************/
50 /**********************************************************************
51 ************************** Internal functions ************************
52 **********************************************************************/
54 /**********************************************************************
55 ************************** Global Variables **************************
56 **********************************************************************/
57 extern sblProfileInfo_t sblProfileLog[MAX_PROFILE_LOG_ENTRIES];
58 extern uint32_t sblProfileLogIndx;
59 extern uint32_t sblProfileLogOvrFlw;
61 #pragma DATA_SECTION(sblProfileLogAddr, ".sbl_profile_info")
62 volatile sblProfileInfo_t * sblProfileLogAddr;
64 #pragma DATA_SECTION(sblProfileLogIndxAddr, ".sbl_profile_info")
65 volatile uint32_t *sblProfileLogIndxAddr;
67 #pragma DATA_SECTION(sblProfileLogOvrFlwAddr, ".sbl_profile_info")
68 volatile uint32_t *sblProfileLogOvrFlwAddr;
70 sblEntryPoint_t k3xx_evmEntry;
71 #if defined(SOC_AM64X)
72 const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =
73 {
74 {
75 /* Region 0 configuration: complete 32 bit address space = 4Gbits */
76 .regionId = 0U,
77 .enable = 1U,
78 .baseAddr = 0x0U,
79 .size = CSL_ARM_R5_MPU_REGION_SIZE_4GB,
80 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
81 .exeNeverControl = 1U,
82 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
83 .shareable = 0U,
84 .cacheable = (uint32_t)FALSE,
85 .cachePolicy = 0U,
86 .memAttr = 0U,
87 },
88 {
89 /* Region 1 configuration: 64K bytes ATCM for exception vector execution */
90 .regionId = 1U,
91 .enable = 1U,
92 .baseAddr = 0x0U,
93 .size = CSL_ARM_R5_MPU_REGION_SIZE_32KB,
94 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
95 .exeNeverControl = 0U,
96 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
97 .shareable = 0U,
98 .cacheable = (uint32_t)TRUE,
99 .cachePolicy = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
100 .memAttr = 0U,
101 },
102 {
103 /* Region 2 configuration: 2 MB MCMS3 RAM */
104 .regionId = 2U,
105 .enable = 1U,
106 .baseAddr = 0x70000000,
107 .size = CSL_ARM_R5_MPU_REGION_SIZE_2MB,
108 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
109 .exeNeverControl = 0U,
110 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
111 .shareable = 0U,
112 .cacheable = (uint32_t)TRUE,
113 .cachePolicy = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
114 .memAttr = 0U,
115 },
116 {
117 /* Region 3 configuration: 2 GB DDR RAM */
118 .regionId = 3U,
119 .enable = 1U,
120 .baseAddr = 0x80000000,
121 .size = CSL_ARM_R5_MPU_REGION_SIZE_2GB,
122 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
123 .exeNeverControl = 0U,
124 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
125 .shareable = 0U,
126 .cacheable = (uint32_t)TRUE,
127 .cachePolicy = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
128 .memAttr = 0U,
129 },
130 {
131 /* Region 4 configuration: 64 KB BTCM */
132 .regionId = 4U,
133 .enable = 1U,
134 .baseAddr = 0x41010000,
135 .size = CSL_ARM_R5_MPU_REGION_SIZE_32KB,
136 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
137 .exeNeverControl = 0U,
138 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
139 .shareable = 0U,
140 .cacheable = (uint32_t)TRUE,
141 .cachePolicy = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
142 .memAttr = 0U,
143 },
144 {
145 /* Region 5 configuration: 128 MB FSS DAT0 */
146 .regionId = 5U,
147 .enable = 1U,
148 .baseAddr = 0x60000000,
149 .size = CSL_ARM_R5_MPU_REGION_SIZE_128MB,
150 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
151 .exeNeverControl = 0U,
152 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
153 .shareable = 0U,
154 .cacheable = (uint32_t)TRUE,
155 .cachePolicy = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
156 .memAttr = 0U,
157 }
158 };
159 #else
160 const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =
161 {
162 {
163 /* Region 0 configuration: complete 32 bit address space = 4Gbits */
164 .regionId = 0U,
165 .enable = 1U,
166 .baseAddr = 0x0U,
167 .size = CSL_ARM_R5_MPU_REGION_SIZE_4GB,
168 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
169 .exeNeverControl = 1U,
170 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
171 .shareable = 0U,
172 .cacheable = (uint32_t)FALSE,
173 .cachePolicy = 0U,
174 .memAttr = 0U,
175 },
176 {
177 /* Region 1 configuration: 128 bytes memory for exception vector execution */
178 .regionId = 1U,
179 .enable = 1U,
180 .baseAddr = 0x0U,
181 .size = CSL_ARM_R5_MPU_REGION_SIZE_32KB,
182 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
183 .exeNeverControl = 0U,
184 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
185 .shareable = 0U,
186 .cacheable = (uint32_t)TRUE,
187 .cachePolicy = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
188 .memAttr = 0U,
189 },
190 {
191 /* Region 2 configuration: 1 MB OCMS RAM - Covers RAM sizes for multiple SoCs */
192 .regionId = 2U,
193 .enable = 1U,
194 .baseAddr = 0x41C00000,
195 .size = CSL_ARM_R5_MPU_REGION_SIZE_1MB,
196 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
197 .exeNeverControl = 0U,
198 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
199 .shareable = 0U,
200 .cacheable = (uint32_t)TRUE,
201 .cachePolicy = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
202 .memAttr = 0U,
203 },
204 {
205 /* Region 3 configuration: 2 MB MCMS3 RAM */
206 .regionId = 3U,
207 .enable = 1U,
208 .baseAddr = 0x70000000,
209 .size = CSL_ARM_R5_MPU_REGION_SIZE_8MB,
210 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
211 .exeNeverControl = 0U,
212 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
213 .shareable = 0U,
214 .cacheable = (uint32_t)TRUE,
215 .cachePolicy = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
216 .memAttr = 0U,
217 },
218 {
219 /* Region 4 configuration: 2 GB DDR RAM */
220 .regionId = 4U,
221 .enable = 1U,
222 .baseAddr = 0x80000000,
223 .size = CSL_ARM_R5_MPU_REGION_SIZE_2GB,
224 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
225 .exeNeverControl = 0U,
226 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
227 .shareable = 0U,
228 .cacheable = (uint32_t)TRUE,
229 .cachePolicy = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
230 .memAttr = 0U,
231 },
232 {
233 /* Region 5 configuration: 64 KB BTCM */
234 .regionId = 5U,
235 .enable = 1U,
236 .baseAddr = 0x41010000,
237 .size = CSL_ARM_R5_MPU_REGION_SIZE_32KB,
238 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
239 .exeNeverControl = 0U,
240 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
241 .shareable = 0U,
242 .cacheable = (uint32_t)TRUE,
243 .cachePolicy = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
244 .memAttr = 0U,
245 },
246 {
247 /* Region 6 configuration: Covers first 32MB of EVM Flash (FSS DAT0) */
248 .regionId = 6U,
249 .enable = 1U,
250 .baseAddr = 0x50000000,
251 .size = CSL_ARM_R5_MPU_REGION_SIZE_32MB,
252 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
253 .exeNeverControl = 0U,
254 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
255 .shareable = 0U,
256 .cacheable = (uint32_t)TRUE,
257 .cachePolicy = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
258 .memAttr = 0U,
259 },
260 {
261 /* Region 7 configuration: Covers next 16MB of EVM Flash (FSS DAT0) */
262 .regionId = 7U,
263 .enable = 1U,
264 .baseAddr = 0x52000000,
265 .size = CSL_ARM_R5_MPU_REGION_SIZE_16MB,
266 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
267 .exeNeverControl = 0U,
268 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
269 .shareable = 0U,
270 .cacheable = (uint32_t)TRUE,
271 .cachePolicy = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
272 .memAttr = 0U,
273 },
274 {
275 /* Region 8 configuration: Covers next 8MB of EVM Flash (FSS DAT0) */
276 .regionId = 8U,
277 .enable = 1U,
278 .baseAddr = 0x53000000,
279 .size = CSL_ARM_R5_MPU_REGION_SIZE_8MB,
280 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
281 .exeNeverControl = 0U,
282 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
283 .shareable = 0U,
284 .cacheable = (uint32_t)TRUE,
285 .cachePolicy = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
286 .memAttr = 0U,
287 },
288 {
289 /* Region 9 configuration: Covers next 4MB of EVM Flash (FSS DAT0) */
290 .regionId = 9U,
291 .enable = 1U,
292 .baseAddr = 0x53800000,
293 .size = CSL_ARM_R5_MPU_REGION_SIZE_4MB,
294 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
295 .exeNeverControl = 0U,
296 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
297 .shareable = 0U,
298 .cacheable = (uint32_t)TRUE,
299 .cachePolicy = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
300 .memAttr = 0U,
301 },
302 {
303 /* Region 10 configuration: Covers next 2MB of EVM Flash (FSS DAT0) */
304 .regionId = 10U,
305 .enable = 1U,
306 .baseAddr = 0x53C00000,
307 .size = CSL_ARM_R5_MPU_REGION_SIZE_2MB,
308 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
309 .exeNeverControl = 0U,
310 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
311 .shareable = 0U,
312 .cacheable = (uint32_t)TRUE,
313 .cachePolicy = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
314 .memAttr = 0U,
315 },
316 {
317 /* Region 11 configuration: Covers next 1MB of EVM Flash (FSS DAT0) */
318 .regionId = 11U,
319 .enable = 1U,
320 .baseAddr = 0x53E00000,
321 .size = CSL_ARM_R5_MPU_REGION_SIZE_1MB,
322 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
323 .exeNeverControl = 0U,
324 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
325 .shareable = 0U,
326 .cacheable = (uint32_t)TRUE,
327 .cachePolicy = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
328 .memAttr = 0U,
329 },
330 {
331 /* Region 12 configuration: Covers next 512KB of EVM Flash (FSS DAT0) */
332 .regionId = 12U,
333 .enable = 1U,
334 .baseAddr = 0x53F00000,
335 .size = CSL_ARM_R5_MPU_REGION_SIZE_512KB,
336 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
337 .exeNeverControl = 0U,
338 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
339 .shareable = 0U,
340 .cacheable = (uint32_t)TRUE,
341 .cachePolicy = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
342 .memAttr = 0U,
343 },
344 {
345 /* Region 13 configuration: Covers next 256KB of EVM Flash (FSS DAT0) */
346 .regionId = 13U,
347 .enable = 1U,
348 .baseAddr = 0x53F80000,
349 .size = CSL_ARM_R5_MPU_REGION_SIZE_256KB,
350 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
351 .exeNeverControl = 0U,
352 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
353 .shareable = 0U,
354 .cacheable = (uint32_t)TRUE,
355 .cachePolicy = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
356 .memAttr = 0U,
357 },
358 {
359 /* Region 14 configuration (Non-cached for PHY tuning data): Covers last 256KB of EVM Flash (FSS DAT0) */
360 .regionId = 14U,
361 .enable = 1U,
362 .baseAddr = 0x53FC0000,
363 .size = CSL_ARM_R5_MPU_REGION_SIZE_256KB,
364 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
365 .exeNeverControl = 0U,
366 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
367 .shareable = 0U,
368 /* OSPI PHY tuning algorithm which runs in DAC mode needs
369 * cache to be disabled for this section of FSS data region.
370 */
371 .cacheable = (uint32_t)FALSE,
372 .cachePolicy = 0U,
373 .memAttr = 0U,
374 },
375 {
376 /* Region 15 configuration: 128 MB FSS DAT1 */
377 .regionId = 15U,
378 .enable = 1U,
379 .baseAddr = 0x58000000,
380 .size = CSL_ARM_R5_MPU_REGION_SIZE_128MB,
381 .subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
382 .exeNeverControl = 0U,
383 .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
384 .shareable = 0U,
385 .cacheable = (uint32_t)TRUE,
386 .cachePolicy = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
387 .memAttr = 0U,
388 },
389 };
391 #endif
392 int main()
393 {
394 #if defined(SBL_ENABLE_HLOS_BOOT) && (defined(SOC_J721E) || defined(SOC_J7200))
395 cpu_core_id_t core_id;
396 #endif
397 uint32_t isBuildHs;
398 uint32_t atcm_size;
400 SBL_ADD_PROFILE_POINT;
402 /* Any SoC specific Init. */
403 #if defined (SBL_BUILD_HS)
404 isBuildHs = TRUE;
405 #else
406 isBuildHs = FALSE;
407 #endif
408 SBL_SocEarlyInit(isBuildHs);
410 if (SBL_LOG_LEVEL > SBL_LOG_ERR)
411 {
412 /* Configure UART Tx pinmux. */
413 Board_uartTxPinmuxConfig();
414 }
416 SBL_ADD_PROFILE_POINT;
418 if (SBL_LOG_LEVEL > SBL_LOG_NONE)
419 {
420 UART_HwAttrs uart_cfg;
422 UART_socGetInitCfg(BOARD_UART_INSTANCE, &uart_cfg);
423 /* Use UART fclk freq setup by ROM */
424 uart_cfg.frequency = SBL_ROM_UART_MODULE_INPUT_CLK;
425 /* Disable the UART interrupt */
426 uart_cfg.enableInterrupt = FALSE;
427 UART_socSetInitCfg(BOARD_UART_INSTANCE, &uart_cfg);
428 /* Init UART for logging. */
429 UART_stdioInit(BOARD_UART_INSTANCE);
430 }
432 SBL_ADD_PROFILE_POINT;
434 SBL_log(SBL_LOG_MIN, "%s (%s - %s)\n", SBL_VERSION_STR, __DATE__, __TIME__);
436 SBL_ADD_PROFILE_POINT;
438 /* Initialize the ATCM */
439 atcm_size = sblAtcmSize();
440 memset((void *)SBL_MCU_ATCM_BASE, 0xFF, atcm_size);
442 /* Relocate CSL Vectors to ATCM*/
443 memcpy((void *)SBL_MCU_ATCM_BASE, (void *)_resetvectors, 0x100);
445 SBL_ADD_PROFILE_POINT;
447 /* Setup RAT */
448 SBL_RAT_Config(sblRatCfgList);
450 SBL_ADD_PROFILE_POINT;
452 /* Load SYSFW. */
453 SBL_SciClientInit();
455 SBL_ADD_PROFILE_POINT;
457 #if !defined(SBL_SKIP_PINMUX_ENABLE)
458 /* Board pinmux. */
459 #if defined(SOC_AM64X)
460 /* AM64x should not re-configure Pinmux on reset */
461 uint32_t mmrResetRegister = (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE+CSL_MAIN_CTRL_MMR_CFG0_RST_SRC_PROXY)));
463 uint32_t mmrResetMask = CSL_MAIN_CTRL_MMR_CFG0_RST_SRC_PROXY_RST_SRC_MAIN_RESET_REQ_PROXY_MASK
464 | CSL_MAIN_CTRL_MMR_CFG0_RST_SRC_PROXY_RST_SRC_WARM_OUT_RST_PROXY_MASK
465 | CSL_MAIN_CTRL_MMR_CFG0_RST_SRC_PROXY_RST_SRC_SW_MCU_WARMRST_PROXY_MASK
466 | CSL_MAIN_CTRL_MMR_CFG0_RST_SRC_PROXY_RST_SRC_SW_MAIN_WARMRST_FROM_MCU_PROXY_MASK
467 | CSL_MAIN_CTRL_MMR_CFG0_RST_SRC_PROXY_RST_SRC_SW_MAIN_WARMRST_FROM_MAIN_PROXY_MASK
468 | CSL_MAIN_CTRL_MMR_CFG0_RST_SRC_PROXY_RST_SRC_MAIN_ESM_ERROR_PROXY_MASK;
470 if (mmrResetRegister & mmrResetMask)
471 {
472 /* Do not do PinMux */
473 SBL_log(SBL_LOG_MAX, "SKIPPING PINMUX ENABLE\n");
474 }
475 else
476 {
477 SBL_log(SBL_LOG_MAX, "ENABLING PINMUX\n");
478 Board_init(BOARD_INIT_PINMUX_CONFIG);
479 }
480 #else
481 Board_init(BOARD_INIT_PINMUX_CONFIG);
482 #endif
484 #endif
486 #if !defined(SBL_SKIP_LATE_INIT)
487 SBL_ADD_PROFILE_POINT;
488 /* Any SoC specific Init. */
489 SBL_SocLateInit();
490 #endif
492 #if defined(SBL_ENABLE_PLL) && !defined(SBL_SKIP_SYSFW_INIT)
493 SBL_log(SBL_LOG_MAX, "Initlialzing PLLs ...");
494 SBL_ADD_PROFILE_POINT;
495 Board_init(SBL_PLL_INIT);
496 SBL_log(SBL_LOG_MAX, "done.\n");
497 #endif
499 #if defined(SBL_ENABLE_CLOCKS) && !defined(SBL_SKIP_SYSFW_INIT)
500 SBL_log(SBL_LOG_MAX, "InitlialzingClocks ...");
501 SBL_ADD_PROFILE_POINT;
502 #if defined(SBL_ENABLE_HLOS_BOOT)
503 #if defined(SOC_J721E) || defined(SOC_J7200)
504 Board_initParams_t initParams;
505 Board_getInitParams(&initParams);
506 initParams.mainClkGrp = BOARD_MAIN_CLOCK_GROUP1;
507 initParams.mcuClkGrp = BOARD_MCU_CLOCK_GROUP1;
508 Board_setInitParams(&initParams);
509 #endif
510 #endif
511 Board_init(SBL_CLOCK_INIT);
513 SBL_log(SBL_LOG_MAX, "done.\n");
514 #endif
516 #if defined(SBL_ENABLE_DDR) && defined(SBL_ENABLE_PLL) && defined(SBL_ENABLE_CLOCKS) && !defined(SBL_SKIP_SYSFW_INIT)
517 SBL_log(SBL_LOG_MAX, "Initlialzing DDR ...");
518 SBL_ADD_PROFILE_POINT;
519 Board_init(BOARD_INIT_DDR);
520 SBL_log(SBL_LOG_MAX, "done.\n");
521 #endif
523 #if !defined(SBL_USE_MCU_DOMAIN_ONLY) && !defined(SBL_ENABLE_DEV_GRP_MCU)
524 /* Enable GTC */
525 SBL_log(SBL_LOG_MAX, "Initializing GTC ...");
526 volatile uint32_t *gtcRegister = (uint32_t *) CSL_GTC0_GTC_CFG1_BASE;
527 *gtcRegister = *gtcRegister | CSL_GTC_CFG1_CNTCR_EN_MASK | CSL_GTC_CFG1_CNTCR_HDBG_MASK;
528 #endif
530 SBL_log(SBL_LOG_MAX, "Begin parsing user application\n");
532 /* Boot all non-SBL cores in multi-core app image */
533 SBL_BootImage(&k3xx_evmEntry);
535 /* Export SBL logs */
536 sblProfileLogAddr = sblProfileLog;
537 sblProfileLogIndxAddr = &sblProfileLogIndx;
538 sblProfileLogOvrFlwAddr = &sblProfileLogOvrFlw;
540 #if defined(SBL_ENABLE_HLOS_BOOT) && (defined(SOC_J721E) || defined(SOC_J7200))
541 /* For J721E/J7200 we have to manage all core boots at the end, to load mcu1_0 sciserver app */
542 for (core_id = MCU2_CPU0_ID; core_id <= SBL_LAST_CORE_ID; core_id ++)
543 {
544 /* Try booting all MAIN domain cores except the Cortex-A cores */
545 if (k3xx_evmEntry.CpuEntryPoint[core_id] != SBL_INVALID_ENTRY_ADDR)
546 SBL_SlaveCoreBoot(core_id, NULL, &k3xx_evmEntry, SBL_REQUEST_CORE);
547 }
549 Board_releaseResource(BOARD_RESOURCE_MODULE_CLOCK);
551 /* Boot the HLOS on the Cortex-A cores towards the end */
552 for (core_id = MPU1_CPU0_ID; core_id <= MPU1_CPU1_ID; core_id ++)
553 {
554 /* Try booting all cores other than the cluster running the SBL */
555 if (k3xx_evmEntry.CpuEntryPoint[core_id] != SBL_INVALID_ENTRY_ADDR)
556 SBL_SlaveCoreBoot(core_id, NULL, &k3xx_evmEntry, SBL_REQUEST_CORE);
557 }
558 #endif
560 /* Boot the core running SBL in the end */
561 if ((k3xx_evmEntry.CpuEntryPoint[MCU1_CPU1_ID] != SBL_INVALID_ENTRY_ADDR) ||
562 (k3xx_evmEntry.CpuEntryPoint[MCU1_CPU0_ID] < SBL_INVALID_ENTRY_ADDR))
563 {
564 SBL_SlaveCoreBoot(MCU1_CPU0_ID, 0, &k3xx_evmEntry, SBL_REQUEST_CORE);
565 SBL_SlaveCoreBoot(MCU1_CPU1_ID, 0, &k3xx_evmEntry, SBL_REQUEST_CORE);
566 }
568 /* Execute a WFI */
569 asm volatile (" wfi");
571 return 0;
572 }