1 /**
2 * \file sbl_avs_config.c
3 *
4 * \brief This file contains functions and data related to AVS and ABB
5 * configuration for the voltage rails.
6 *
7 */
9 /*
10 * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 *
16 * Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 *
19 * Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the
22 * distribution.
23 *
24 * Neither the name of Texas Instruments Incorporated nor the names of
25 * its contributors may be used to endorse or promote products derived
26 * from this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 */
42 #include "sbl_avs_config.h"
43 #include "sbl_prcm.h"
45 #include <ti/csl/cslr_device.h>
46 #include <ti/csl/hw_types.h>
47 #include <ti/board/board.h>
48 #include <ti/drv/pm/pmhal.h>
49 #if defined(idkAM572x)
50 #include <ti/board/src/idkAM572x/device/pmic_device.h>
51 #elif defined(idkAM571x)
52 #include <ti/board/src/idkAM571x/device/pmic_device.h>
53 #elif defined(evmAM572x)
54 #include <ti/board/src/evmAM572x/device/pmic_device.h>
55 #elif defined(idkAM574x)
56 #include <ti/board/src/idkAM574x/device/pmic_device.h>
57 #endif
59 /**********************************************************************
60 ************************** Internal functions ************************
61 **********************************************************************/
63 /**
64 * \brief SBL_Read_Efuse_Reg function to read the voltage value from efuse
65 *
66 * \param railVoltage pointer to the rail voltage.
67 *
68 * \retval regVal Value from the Efuse registers.
69 *
70 **/
71 static uint32_t SBL_Read_Efuse_Reg(const voltage_rail_t *railVoltage);
73 /**
74 * \brief SBL_GetOppConfig function to get the
75 *
76 * \param oppVal value representing the OPP mode.
77 * \param boardId Board ID value
78 *
79 * \retval voltCoreData pointer to the AVS data for the particular OPP.
80 *
81 **/
82 static const vcores_data_t* SBL_GetOppConfig(uint32_t oppVal, uint32_t boardId);
84 /**
85 * \brief Initialize the I2C controller by configuring the pinmux and
86 * module clocks.
87 *
88 * \param oppVal value representing the OPP mode.
89 *
90 **/
91 static void SBL_I2CInit();
93 /**
94 * \brief Function to resolve the Board Name string to BoardId.
95 *
96 * \param pBoardName Pointer to the Board Name String.
97 *
98 **/
99 static uint32_t SBL_GetBoardid(char *pBoardName);
101 /**********************************************************************
102 ************************** Macros ************************************
103 **********************************************************************/
105 /* TPS659039 */
106 #define TPS659039_I2C_SLAVE_ADDR 0x58
107 #define TPS659039_REG_ADDR_SMPS12 0x23
108 #define TPS659039_REG_ADDR_SMPS45 0x2B
109 #define TPS659039_REG_ADDR_SMPS6 0x2F
110 #define TPS659039_REG_ADDR_SMPS7 0x33
111 #define TPS659039_REG_ADDR_SMPS8 0x37
113 #define TPS659039_PMIC_DEV_CTRL 0xA0
115 /* TPS659039 Voltage settings in mv for OPP_NOMINAL */
116 #define VDD_MPU_AM57XX 1100
117 #define VDD_DSP_AM57XX 1060
118 #define VDD_GPU_AM57XX 1060
119 #define VDD_CORE_AM57XX 1030
120 #define VDD_IVA_AM57XX 1060
122 /* Efuse register offsets for DRA7xx platform */
123 #define AM57XX_EFUSE_BASE 0x4A002000U
124 #define AM57XX_EFUSE_REGBITS 16
126 /* STD_FUSE_OPP_VMIN_IVA_2 */
127 #define STD_FUSE_OPP_VMIN_IVA_NOM (AM57XX_EFUSE_BASE + 0x05CC)
128 /* STD_FUSE_OPP_VMIN_IVA_3 */
129 #define STD_FUSE_OPP_VMIN_IVA_OD (AM57XX_EFUSE_BASE + 0x05D0)
130 /* STD_FUSE_OPP_VMIN_IVA_4 */
131 #define STD_FUSE_OPP_VMIN_IVA_HIGH (AM57XX_EFUSE_BASE + 0x05D4)
132 /* STD_FUSE_OPP_VMIN_DSPEVE_2 */
133 #define STD_FUSE_OPP_VMIN_DSPEVE_NOM (AM57XX_EFUSE_BASE + 0x05E0)
134 /* STD_FUSE_OPP_VMIN_DSPEVE_3 */
135 #define STD_FUSE_OPP_VMIN_DSPEVE_OD (AM57XX_EFUSE_BASE + 0x05E4)
136 /* STD_FUSE_OPP_VMIN_DSPEVE_4 */
137 #define STD_FUSE_OPP_VMIN_DSPEVE_HIGH (AM57XX_EFUSE_BASE + 0x05E8)
138 /* STD_FUSE_OPP_VMIN_CORE_2 */
139 #define STD_FUSE_OPP_VMIN_CORE_NOM (AM57XX_EFUSE_BASE + 0x05F4)
140 /* STD_FUSE_OPP_VMIN_GPU_2 */
141 #define STD_FUSE_OPP_VMIN_GPU_NOM (AM57XX_EFUSE_BASE + 0x1B08)
142 /* STD_FUSE_OPP_VMIN_GPU_3 */
143 #define STD_FUSE_OPP_VMIN_GPU_OD (AM57XX_EFUSE_BASE + 0x1B0C)
144 /* STD_FUSE_OPP_VMIN_GPU_4 */
145 #define STD_FUSE_OPP_VMIN_GPU_HIGH (AM57XX_EFUSE_BASE + 0x1B10)
146 /* STD_FUSE_OPP_VMIN_MPU_2 */
147 #define STD_FUSE_OPP_VMIN_MPU_NOM (AM57XX_EFUSE_BASE + 0x1B20)
148 /* STD_FUSE_OPP_VMIN_MPU_3 */
149 #define STD_FUSE_OPP_VMIN_MPU_OD (AM57XX_EFUSE_BASE + 0x1B24)
150 /* STD_FUSE_OPP_VMIN_MPU_4 */
151 #define STD_FUSE_OPP_VMIN_MPU_HIGH (AM57XX_EFUSE_BASE + 0x1B28)
153 #define CTRL_CORE_PAD_I2C1_SDA (0x400U)
154 #define CTRL_CORE_PAD_I2C1_SCL (0x404U)
156 #define CTRL_CORE_PAD_I2C1_SCL_PIN_PULLUP_EN (0x00050000U)
157 #define CTRL_CORE_PAD_I2C1_SDA_PIN_PULLUP_EN (0x00050000U)
159 #define BOARD_NAME_LENGTH (8)
160 #define OPP_TABLE_SIZE (3)
162 #if defined(idkAM572x) || defined(idkAM574x)
163 /* Structure to hold the AVS values of all voltage rails for OPP NOM */
164 const vcores_data_t idkAM572x_opp_nom_volts = {
165 {
166 VDD_MPU_AM57XX,
167 TPS659039_REG_ADDR_SMPS12,
168 {
169 STD_FUSE_OPP_VMIN_MPU_NOM,
170 AM57XX_EFUSE_REGBITS
171 },
172 },
174 {
175 VDD_CORE_AM57XX,
176 TPS659039_REG_ADDR_SMPS7,
177 {
178 STD_FUSE_OPP_VMIN_CORE_NOM,
179 AM57XX_EFUSE_REGBITS
180 },
181 },
183 {
184 VDD_DSP_AM57XX,
185 TPS659039_REG_ADDR_SMPS45,
186 {
187 STD_FUSE_OPP_VMIN_DSPEVE_NOM,
188 AM57XX_EFUSE_REGBITS
189 },
190 },
192 {
193 VDD_GPU_AM57XX,
194 TPS659039_REG_ADDR_SMPS6,
195 {
196 STD_FUSE_OPP_VMIN_GPU_NOM,
197 AM57XX_EFUSE_REGBITS
198 },
199 },
201 {
202 VDD_IVA_AM57XX,
203 TPS659039_REG_ADDR_SMPS8,
204 {
205 STD_FUSE_OPP_VMIN_IVA_NOM,
206 AM57XX_EFUSE_REGBITS
207 },
208 }
209 };
211 /* Structure to hold the AVS values of all voltage rails for OPP OD */
212 const vcores_data_t idkAM572x_opp_od_volts = {
213 {
214 VDD_MPU_AM57XX,
215 TPS659039_REG_ADDR_SMPS12,
216 {
217 STD_FUSE_OPP_VMIN_MPU_OD,
218 AM57XX_EFUSE_REGBITS
219 },
220 },
222 {
223 VDD_CORE_AM57XX,
224 /* core does not support opp OD; using opp NOM */
225 TPS659039_REG_ADDR_SMPS7,
226 {
227 STD_FUSE_OPP_VMIN_CORE_NOM,
228 AM57XX_EFUSE_REGBITS
229 },
230 },
232 {
233 VDD_DSP_AM57XX,
234 TPS659039_REG_ADDR_SMPS45,
235 {
236 STD_FUSE_OPP_VMIN_DSPEVE_OD,
237 AM57XX_EFUSE_REGBITS
238 },
239 },
241 {
242 VDD_GPU_AM57XX,
243 TPS659039_REG_ADDR_SMPS6,
244 {
245 STD_FUSE_OPP_VMIN_GPU_OD,
246 AM57XX_EFUSE_REGBITS
247 },
248 },
250 {
251 VDD_IVA_AM57XX,
252 TPS659039_REG_ADDR_SMPS8,
253 {
254 STD_FUSE_OPP_VMIN_IVA_OD,
255 AM57XX_EFUSE_REGBITS
256 },
257 }
258 };
260 /* Structure to hold the AVS values of all voltage rails for OPP HIGH */
261 const vcores_data_t idkAM572x_opp_high_volts = {
262 {
263 VDD_MPU_AM57XX,
264 TPS659039_REG_ADDR_SMPS12,
265 {
266 STD_FUSE_OPP_VMIN_MPU_HIGH,
267 AM57XX_EFUSE_REGBITS
268 },
269 },
271 {
272 VDD_CORE_AM57XX,
273 TPS659039_REG_ADDR_SMPS7,
274 /* core does not support opp high; using opp NOM */
275 {
276 STD_FUSE_OPP_VMIN_CORE_NOM,
277 AM57XX_EFUSE_REGBITS
278 },
279 },
281 {
282 VDD_DSP_AM57XX,
283 TPS659039_REG_ADDR_SMPS45,
284 {
285 STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
286 AM57XX_EFUSE_REGBITS
287 },
288 },
290 {
291 VDD_GPU_AM57XX,
292 TPS659039_REG_ADDR_SMPS6,
293 {
294 STD_FUSE_OPP_VMIN_GPU_HIGH,
295 AM57XX_EFUSE_REGBITS
296 },
297 },
299 {
300 VDD_IVA_AM57XX,
301 TPS659039_REG_ADDR_SMPS8,
302 {
303 STD_FUSE_OPP_VMIN_IVA_HIGH,
304 AM57XX_EFUSE_REGBITS
305 },
306 }
307 };
308 #endif
310 /* Structure defining the OPP table for AM572xIDK. */
311 boardOppData_t gAm572xIdkOppTable[] =
312 {
313 #if defined(idkAM572x) || defined(idkAM574x)
314 {OPP_MODE_NOM, &idkAM572x_opp_nom_volts},
315 {OPP_MODE_OD, &idkAM572x_opp_od_volts},
316 {OPP_MODE_HIGH, &idkAM572x_opp_high_volts}
317 #endif
318 };
320 #if defined(idkAM571x)
321 /* Structure to hold the AVS values of all voltage rails for OPP NOM */
322 const vcores_data_t idkAM571x_opp_nom_volts = {
323 {
324 VDD_MPU_AM57XX,
325 TPS659039_REG_ADDR_SMPS12,
326 {
327 STD_FUSE_OPP_VMIN_MPU_NOM,
328 AM57XX_EFUSE_REGBITS
329 },
330 },
332 {
333 VDD_CORE_AM57XX,
334 TPS659039_REG_ADDR_SMPS7,
335 {
336 STD_FUSE_OPP_VMIN_CORE_NOM,
337 AM57XX_EFUSE_REGBITS
338 },
339 },
341 /* DSP rail not connected for idkAM571x */
342 {
343 0U,
344 0U,
345 {
346 0U,
347 AM57XX_EFUSE_REGBITS
348 },
349 },
351 {
352 VDD_GPU_AM57XX,
353 TPS659039_REG_ADDR_SMPS6,
354 {
355 STD_FUSE_OPP_VMIN_GPU_NOM,
356 AM57XX_EFUSE_REGBITS
357 },
358 },
360 {
361 VDD_IVA_AM57XX,
362 TPS659039_REG_ADDR_SMPS45,
363 {
364 STD_FUSE_OPP_VMIN_IVA_NOM,
365 AM57XX_EFUSE_REGBITS
366 },
367 }
368 };
370 /* Structure to hold the AVS values of all voltage rails for OPP OD */
371 const vcores_data_t idkAM571x_opp_od_volts = {
372 {
373 VDD_MPU_AM57XX,
374 TPS659039_REG_ADDR_SMPS12,
375 {
376 STD_FUSE_OPP_VMIN_MPU_OD,
377 AM57XX_EFUSE_REGBITS
378 },
379 },
381 {
382 VDD_CORE_AM57XX,
383 /* core does not support opp OD; using opp NOM */
384 TPS659039_REG_ADDR_SMPS7,
385 {
386 STD_FUSE_OPP_VMIN_CORE_NOM,
387 AM57XX_EFUSE_REGBITS
388 },
389 },
391 /* DSP rail not connected for idkAM571x */
392 {
393 0U,
394 0U,
395 {
396 0U,
397 AM57XX_EFUSE_REGBITS
398 },
399 },
401 {
402 VDD_GPU_AM57XX,
403 TPS659039_REG_ADDR_SMPS6,
404 {
405 STD_FUSE_OPP_VMIN_GPU_OD,
406 AM57XX_EFUSE_REGBITS
407 },
408 },
410 {
411 VDD_IVA_AM57XX,
412 TPS659039_REG_ADDR_SMPS45,
413 {
414 STD_FUSE_OPP_VMIN_IVA_OD,
415 AM57XX_EFUSE_REGBITS
416 },
417 }
418 };
420 /* Structure to hold the AVS values of all voltage rails for OPP HIGH */
421 const vcores_data_t idkAM571x_opp_high_volts = {
422 {
423 VDD_MPU_AM57XX,
424 TPS659039_REG_ADDR_SMPS12,
425 {
426 STD_FUSE_OPP_VMIN_MPU_HIGH,
427 AM57XX_EFUSE_REGBITS
428 },
429 },
431 {
432 VDD_CORE_AM57XX,
433 TPS659039_REG_ADDR_SMPS7,
434 /* core does not support opp high; using opp NOM */
435 {
436 STD_FUSE_OPP_VMIN_CORE_NOM,
437 AM57XX_EFUSE_REGBITS
438 },
439 },
441 /* DSP rail not connected for idkAM571x */
442 {
443 0U,
444 0U,
445 {
446 0U,
447 AM57XX_EFUSE_REGBITS
448 },
449 },
451 {
452 VDD_GPU_AM57XX,
453 TPS659039_REG_ADDR_SMPS6,
454 {
455 STD_FUSE_OPP_VMIN_GPU_HIGH,
456 AM57XX_EFUSE_REGBITS
457 },
458 },
460 {
461 VDD_IVA_AM57XX,
462 TPS659039_REG_ADDR_SMPS45,
463 {
464 STD_FUSE_OPP_VMIN_IVA_HIGH,
465 AM57XX_EFUSE_REGBITS
466 },
467 }
468 };
469 #endif
471 /* Structure defining the OPP table for AM571xIDK. */
472 boardOppData_t gAm571xIdkOppTable[] =
473 {
474 #if defined(idkAM571x)
475 {OPP_MODE_NOM, &idkAM571x_opp_nom_volts},
476 {OPP_MODE_OD, &idkAM571x_opp_od_volts},
477 {OPP_MODE_HIGH, &idkAM571x_opp_high_volts}
478 #endif
479 };
481 #if defined(evmAM572x)
482 /* Structure to hold the AVS values of all voltage rails for OPP NOM */
483 const vcores_data_t evmAM572x_opp_nom_volts = {
484 {
485 VDD_MPU_AM57XX,
486 TPS659039_REG_ADDR_SMPS12,
487 {
488 STD_FUSE_OPP_VMIN_MPU_NOM,
489 AM57XX_EFUSE_REGBITS
490 },
491 },
493 {
494 VDD_CORE_AM57XX,
495 TPS659039_REG_ADDR_SMPS6,
496 {
497 STD_FUSE_OPP_VMIN_CORE_NOM,
498 AM57XX_EFUSE_REGBITS
499 },
500 },
502 {
503 VDD_DSP_AM57XX,
504 TPS659039_REG_ADDR_SMPS45,
505 {
506 STD_FUSE_OPP_VMIN_DSPEVE_NOM,
507 AM57XX_EFUSE_REGBITS
508 },
509 }
510 };
512 /* Structure to hold the AVS values of all voltage rails for OPP OD */
513 const vcores_data_t evmAM572x_opp_od_volts = {
514 {
515 VDD_MPU_AM57XX,
516 TPS659039_REG_ADDR_SMPS12,
517 {
518 STD_FUSE_OPP_VMIN_MPU_OD,
519 AM57XX_EFUSE_REGBITS
520 },
521 },
523 {
524 VDD_CORE_AM57XX,
525 /* core does not support opp OD; using opp NOM */
526 TPS659039_REG_ADDR_SMPS6,
527 {
528 STD_FUSE_OPP_VMIN_CORE_NOM,
529 AM57XX_EFUSE_REGBITS
530 },
531 },
533 {
534 VDD_DSP_AM57XX,
535 TPS659039_REG_ADDR_SMPS45,
536 {
537 STD_FUSE_OPP_VMIN_DSPEVE_OD,
538 AM57XX_EFUSE_REGBITS
539 },
540 },
542 /* GPU rail not connected for evmAM572x */
543 {
544 0U,
545 0U,
546 {
547 0U,
548 AM57XX_EFUSE_REGBITS
549 },
550 },
552 /* IVA rail not connected for evmAM572x */
553 {
554 0U,
555 0U,
556 {
557 0U,
558 AM57XX_EFUSE_REGBITS
559 },
560 }
561 };
563 /* Structure to hold the AVS values of all voltage rails for OPP HIGH */
564 const vcores_data_t evmAM572x_opp_high_volts = {
565 {
566 VDD_MPU_AM57XX,
567 TPS659039_REG_ADDR_SMPS12,
568 {
569 STD_FUSE_OPP_VMIN_MPU_HIGH,
570 AM57XX_EFUSE_REGBITS
571 },
572 },
574 {
575 VDD_CORE_AM57XX,
576 TPS659039_REG_ADDR_SMPS6,
577 /* core does not support opp high; using opp NOM */
578 {
579 STD_FUSE_OPP_VMIN_CORE_NOM,
580 AM57XX_EFUSE_REGBITS
581 },
582 },
584 {
585 VDD_DSP_AM57XX,
586 TPS659039_REG_ADDR_SMPS45,
587 {
588 STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
589 AM57XX_EFUSE_REGBITS
590 },
591 }
592 };
594 #endif
595 /* Structure defining the OPP table for GPEVM. */
596 boardOppData_t gAm572xGpevmOppTable[] =
597 {
598 #if defined(evmAM572x)
599 {OPP_MODE_NOM, &evmAM572x_opp_nom_volts},
600 {OPP_MODE_OD, &evmAM572x_opp_od_volts},
601 {OPP_MODE_HIGH, &evmAM572x_opp_high_volts}
602 #endif
603 };
605 /** \brief Contains pointers to the OPP Table data for different boards. */
606 static boardOppData_t *gBoardOppTable [BOARD_MAX + 1U]= {
607 NULL, /* BOARD_UNKNOWN */
608 gAm572xGpevmOppTable, /* BOARD_GPEVMAM572x */
609 gAm572xIdkOppTable, /* BOARD_IDKAM572x */
610 gAm571xIdkOppTable, /* BOARD_IDKAM571x */
611 gAm572xIdkOppTable, /* BOARD_IDKAM574x */
612 NULL /* BOARD Custom */
613 };
615 void SBL_Configure_AVS(uint32_t oppMode)
616 {
617 uint32_t val;
618 volatile uint32_t delayVar = 0U;
619 uint32_t offset_code = 0U;
620 const vcores_data_t *vcores = NULL;
621 pmic_data_t *pPmicData;
622 pmhalVmOppId_t pmOpp;
623 Board_IDInfo boardInfo;
624 uint32_t boardId;
626 /*
627 ** Initialize the I2C controller to communicate with PMIC device.
628 ** This initialization includes setting up the clock and pinmux
629 ** for I2C Bus.
630 ** This is required as the AVS setting needs to be completed before
631 ** IO calibration sequence is initiated.
632 */
633 SBL_I2CInit();
635 /* Read the EEPROM to identify the board. */
636 Board_getIDInfo(&boardInfo);
638 /* Resolve the Board Name from EEPROM to a boardID. */
639 boardId = SBL_GetBoardid(boardInfo.boardName);
641 /* Get the OPP configuration data for the specific board. */
642 vcores = SBL_GetOppConfig(oppMode, boardId);
644 /* Get equivalent OPP macro in PM LLD */
645 if (oppMode == OPP_MODE_NOM) pmOpp = PMHAL_VM_OPP_NOM;
646 else if (oppMode == OPP_MODE_OD) pmOpp = PMHAL_VM_OPP_OD;
647 else if (oppMode == OPP_MODE_HIGH) pmOpp = PMHAL_VM_OPP_HIGH;
648 else pmOpp = PMHAL_VM_OPP_UNDEF;
650 /* Get the Pointer to the PMIC data structure. */
651 pPmicData = Board_GetPmicData();
653 pPmicData->pmic_device_open(pPmicData->dev_instance - 1);
655 if(BOARD_GPEVMAM572x == boardId)
656 {
657 /* Set the DEV_CTRL.DEV_ON to 1 to avoid turning off the PMIC for GPEVM */
658 pPmicData->pmic_write(pPmicData->slave_addr, TPS659039_PMIC_DEV_CTRL, 0x01);
659 }
661 /* Configure AVS-0 voltage on CORE_VD */
662 val = SBL_Read_Efuse_Reg(&vcores->core);
663 offset_code = pPmicData->pmic_get_offset(val, pPmicData);
664 /*PMIC I2C write */
665 pPmicData->pmic_write(pPmicData->slave_addr, vcores->core.addr, offset_code);
667 /* Configure the AVS voltage to MPU rail */
668 val = SBL_Read_Efuse_Reg(&vcores->mpu);
669 offset_code = pPmicData->pmic_get_offset(val, pPmicData);
670 /*PMIC I2C write */
671 pPmicData->pmic_write(pPmicData->slave_addr, vcores->mpu.addr, offset_code);
672 PMHALVMEnableABB(PMHAL_PRCM_VD_MPU, pmOpp);
674 /*
675 ** Delay required after configuring 2 voltage rails
676 */
677 for (delayVar = 0; delayVar < 0x1000U; delayVar++) ;
679 /*
680 ** Check if the Voltage rail is Configured If yes then set the AVS value for
681 ** the rail.
682 */
683 if(vcores->dsp.value != 0U)
684 {
685 /* Configure the AVS voltage to DSP rail */
686 val = SBL_Read_Efuse_Reg(&vcores->dsp);
687 offset_code = pPmicData->pmic_get_offset(val, pPmicData);
688 /*PMIC I2C write */
689 pPmicData->pmic_write(pPmicData->slave_addr, vcores->dsp.addr, offset_code);
690 PMHALVMEnableABB(PMHAL_PRCM_VD_DSPEVE, pmOpp);
691 }
693 if(vcores->gpu.value != 0U)
694 {
695 /* Configure the AVS voltage to GPU rail */
696 val = SBL_Read_Efuse_Reg(&vcores->gpu);
697 offset_code = pPmicData->pmic_get_offset(val, pPmicData);
698 /*PMIC I2C write */
699 pPmicData->pmic_write(pPmicData->slave_addr, vcores->gpu.addr, offset_code);
700 PMHALVMEnableABB(PMHAL_PRCM_VD_GPU, pmOpp);
701 }
703 if(vcores->iva.value != 0U)
704 {
705 /* Configure the AVS voltage to IVA rail */
706 val = SBL_Read_Efuse_Reg(&vcores->iva);
707 offset_code = pPmicData->pmic_get_offset(val, pPmicData);
708 /*PMIC I2C write */
709 pPmicData->pmic_write(pPmicData->slave_addr, vcores->iva.addr, offset_code);
710 PMHALVMEnableABB(PMHAL_PRCM_VD_IVAHD, pmOpp);
711 }
713 /* Close the PMIC device. */
714 pPmicData->pmic_device_close();
715 }
717 static const vcores_data_t* SBL_GetOppConfig(uint32_t oppVal, uint32_t boardId)
718 {
719 uint32_t size = OPP_TABLE_SIZE;
720 uint32_t count = 0U;
721 const struct vcores_data *pOppCfg = NULL;
722 boardOppData_t *pOppTable = NULL;
724 /* Assign the pointer to the board specific OPP Table. */
725 pOppTable = gBoardOppTable[boardId];
727 while(count < size)
728 {
729 if(oppVal == (pOppTable + count)->oppVal)
730 {
731 pOppCfg = (pOppTable + count)->pboardOppData;
732 break;
733 }
734 count++;
735 }
737 return pOppCfg;
738 }
740 static void SBL_I2CInit()
741 {
742 /* Set the Clock operational mode for the clock domain. */
743 SBL_PRCMSetClkOperMode(CSL_MPU_L4PER_CM_CORE_REGS, CM_L4PER_CLKSTCTRL,
744 PRCM_CD_CLKTRNMODES_SW_WAKEUP);
746 HW_WR_REG32(CSL_MPU_L4PER_CM_CORE_REGS + CM_L4PER_I2C1_CLKCTRL, 0x2U);
748 /* Check for module enable status */
749 while(2U !=
750 (HW_RD_REG32(CSL_MPU_L4PER_CM_CORE_REGS + CM_L4PER_I2C1_CLKCTRL) & 3U));
752 /* Check clock activity - ungated */
753 while(CM_L4PER_CLKSTCTRL_CLKACTIVITY_L4PER_L3_GICLK_MASK !=
754 (HW_RD_REG32(CSL_MPU_L4PER_CM_CORE_REGS + CM_L4PER_CLKSTCTRL) &
755 CM_L4PER_CLKSTCTRL_CLKACTIVITY_L4PER_L3_GICLK_MASK));
757 /* SDA */
758 HW_WR_REG32((SOC_CORE_PAD_IO_REGISTERS_BASE + CTRL_CORE_PAD_I2C1_SDA),
759 (CTRL_CORE_PAD_I2C1_SDA_PIN_PULLUP_EN));
761 /* SCL */
762 HW_WR_REG32((SOC_CORE_PAD_IO_REGISTERS_BASE + CTRL_CORE_PAD_I2C1_SCL),
763 (CTRL_CORE_PAD_I2C1_SCL_PIN_PULLUP_EN));
764 }
766 static uint32_t SBL_Read_Efuse_Reg(const voltage_rail_t *railVoltage)
767 {
768 uint32_t val;
770 if (!railVoltage->value)
771 return 0;
772 if (!railVoltage->efuse.reg)
773 return railVoltage->value;
775 switch (railVoltage->efuse.reg_bits)
776 {
777 case 16:
778 val = HW_RD_REG16(railVoltage->efuse.reg);
779 break;
780 case 32:
781 val = HW_RD_REG32(railVoltage->efuse.reg);
782 break;
783 default:
784 return railVoltage->value;
785 }
787 if (!val)
788 {
789 return railVoltage->value;
790 }
792 return val;
793 }
795 static uint32_t SBL_GetBoardid(char *pBoardName)
796 {
797 uint32_t boardId;
799 /* Check if the board is GPEVM by comparing the string read from EEPROM. */
800 if (strncmp("AM572PM_", pBoardName, BOARD_NAME_LENGTH) == 0U)
801 {
802 boardId = BOARD_GPEVMAM572x;
803 }
804 /* Check if the board is AM572xIDK by comparing the string read from EEPROM. */
805 else if (strncmp("AM572IDK", pBoardName, BOARD_NAME_LENGTH) == 0U)
806 {
807 boardId = BOARD_IDKAM572x;
808 }
809 /* Check if the board is AM574xIDK by comparing the string read from EEPROM. */
810 else if (strncmp("AM574IDK", pBoardName, BOARD_NAME_LENGTH) == 0U)
811 {
812 boardId = BOARD_IDKAM574x;
813 }
814 /* Check if the board is AM571xIDK by comparing the string read from EEPROM. */
815 else if (strncmp("AM571IDK", pBoardName, BOARD_NAME_LENGTH) == 0U)
816 {
817 boardId = BOARD_IDKAM571x;
818 }
819 else
820 {
821 /* If the board is not one of these, then the board
822 ** ID is returned as BOARD_UNKNOWN.
823 */
824 boardId = BOARD_UNKNOWN;
825 }
827 return boardId;
828 }