[processor-sdk/pdk.git] / packages / ti / boot / sbl / example / tpr12MulticoreApp / r4_tb / include / vim.h
1 /*
2 * VIM Header File
3 *
4 * This is the header file which exposes the API to configure the VIM
5 *
6 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
7 * ALL RIGHTS RESERVED
8 *
9 */
10 #ifndef VIM_H
11 #define VIM_H
13 /**************************************************************************
14 *************************** Include Files ********************************
15 **************************************************************************/
16 /* Standard Include Files. */
17 #include <stdint.h>
19 #ifdef __cplusplus
20 extern "C" {
21 #endif
23 #define VIM_MEM_U_BASE (0xFFF82000U)
24 #define VIM_U_BASE (0xFFFFFE00U)
25 #define VIM_PARITY_U_BASE (0xFFFFFD00U)
27 #define SCIA_INT_REQ (23U)
30 //-------------------------------------------------------VIM-----------------------------------------------------------------------
32 typedef volatile struct
33 {
34 struct
35 {
36 unsigned char IRQIVEC_UB; /* 0x00 */
37 uint32_t : 24U;
38 } IRQIVEC;
40 struct
41 {
42 unsigned char FIQIVEC_UB; /* 0x04 */
43 uint32_t : 24U;
44 } FIQIVEC;
46 struct
47 {
48 uint32_t NEST_ENABLE:4U; /* 0x08 */
49 uint32_t : 28U;
50 } NEST_EN;
52 struct
53 {
54 uint32_t NEST_OVRN :1U; /* 0x0c */
55 uint32_t NEST_STAT :1U;
56 uint32_t : 6U;
57 uint32_t NEST_LEVEL: 8U;
58 uint32_t : 16U;
59 } NEST_CTRL;
61 uint32_t FIRQPR0; /* 0x10 */
63 uint32_t FIRQPR1; /* 0x14 */
65 uint32_t FIRQPR2; /* 0x18 */
67 uint32_t FIRQPR3; /* 0x1c */
69 struct
70 {
71 uint32_t FTC_INT_GA_B1: 1U;
72 uint32_t LFS_INT_GA_B1: 1U;
73 uint32_t BTC_INT_GA_B1: 1U;
74 uint32_t HBC_INT_GA_B1: 1U;
75 uint32_t BER_INT_GA_B1: 1U;
76 uint32_t SCI_TX_INT_B1: 1U;
77 uint32_t SCI_RX_INT_B1: 1U;
78 uint32_t SCI_ER_INT_B1: 1U;
79 uint32_t : 6U;
80 uint32_t RTITB_RQ_B1: 1U;
81 uint32_t RTIOVL_RQ1_B1: 1U;
82 uint32_t RTIOVL_RQ0_B1: 1U;
83 uint32_t RTI_INT_RQ3_B1: 1U;
84 uint32_t RTI_INT_RQ2_B1: 1U;
85 uint32_t RTI_INT_RQ1_B1: 1U;
86 uint32_t RTI_INT_RQ0_B1: 1U;
87 uint32_t : 1U;
88 uint32_t CRC_INT_B1: 1U;
89 uint32_t SYS_ER_INT_B1: 1U;
90 uint32_t SYS_SW_INT_B1: 1U;
91 }INTREQ0;
93 uint32_t INTREQ1; /* 0x24 */
95 uint32_t INTREQ2; /* 0x28 */
97 uint32_t INTREQ3; /* 0x2c */
99 uint32_t REQMASKSET0; /* 0x30 */
101 uint32_t REQMASKSET1; /* 0x34 */
103 uint32_t REQMASKSET2; /* 0x38 */
105 uint32_t REQMASKSET3; /* 0x3c */
107 uint32_t REQMASKCLR0; /* 0x40 */
109 uint32_t REQMASKCLR1; /* 0x44 */
111 uint32_t REQMASKCLR2; /* 0x48 */
113 uint32_t REQMASKCLR3; /* 0x4c */
115 uint32_t WAKEMASKSET0; /* 0x50 */
117 uint32_t WAKEMASKSET1; /* 0x54 */
119 uint32_t WAKEMASKSET2; /* 0x58 */
121 uint32_t WAKEMASKSET3; /* 0x5c */
123 uint32_t WAKEMASKCLR0; /* 0x60 */
125 uint32_t WAKEMASKCLR1; /* 0x64 */
127 uint32_t WAKEMASKCLR2; /* 0x68 */
129 uint32_t WAKEMASKCLR3; /* 0x6c */
131 uint32_t IRQVECREG; /* 0x70 */
133 uint32_t FIQVECREQ; /* 0x74 */
135 struct
136 {
137 uint32_t CAPEVTSRC0_B7 :7U; /* 0x78 */
138 uint32_t : 9U;
139 uint32_t CAPEVTSRC1_B7 :7U;
140 uint32_t : 9U;
141 }CAPEVT;
143 uint32_t : 32U; /* 0x7c */
145 struct
146 {
147 uint32_t CHANMAPX3 : 7U;
148 uint32_t : 1U;
149 uint32_t CHANMAPX2 : 7U;
150 uint32_t : 1U;
151 uint32_t CHANMAPX1 : 7U;
152 uint32_t : 1U;
153 uint32_t CHANMAPX0 : 7U;
154 uint32_t : 1U;
156 }CHANCTRL0;
158 struct
159 {
160 uint32_t CHANMAPX3 : 7U;
161 uint32_t : 1U;
162 uint32_t CHANMAPX2 : 7U;
163 uint32_t : 1U;
164 uint32_t CHANMAPX1 : 7U;
165 uint32_t : 1U;
166 uint32_t CHANMAPX0 : 7U;
167 uint32_t : 1U;
169 }CHANCTRL1;
171 struct
172 {
173 uint32_t CHANMAPX3 : 7U;
174 uint32_t : 1U;
175 uint32_t CHANMAPX2 : 7U;
176 uint32_t : 1U;
177 uint32_t CHANMAPX1 : 7U;
178 uint32_t : 1U;
179 uint32_t CHANMAPX0 : 7U;
180 uint32_t : 1U;
182 }CHANCTRL2;
184 struct
185 {
186 uint32_t CHANMAPX3 : 7U;
187 uint32_t : 1U;
188 uint32_t CHANMAPX2 : 7U;
189 uint32_t : 1U;
190 uint32_t CHANMAPX1 : 7U;
191 uint32_t : 1U;
192 uint32_t CHANMAPX0 : 7U;
193 uint32_t : 1U;
195 }CHANCTRL3;
197 struct
198 {
199 uint32_t CHANMAPX3 : 7U;
200 uint32_t : 1U;
201 uint32_t CHANMAPX2 : 7U;
202 uint32_t : 1U;
203 uint32_t CHANMAPX1 : 7U;
204 uint32_t : 1U;
205 uint32_t CHANMAPX0 : 7U;
206 uint32_t : 1U;
208 }CHANCTRL4;
210 struct
211 {
212 uint32_t CHANMAPX3 : 7U;
213 uint32_t : 1U;
214 uint32_t CHANMAPX2 : 7U;
215 uint32_t : 1U;
216 uint32_t CHANMAPX1 : 7U;
217 uint32_t : 1U;
218 uint32_t CHANMAPX0 : 7U;
219 uint32_t : 1U;
221 }CHANCTRL5;
223 struct
224 {
225 uint32_t CHANMAPX3 : 7U;
226 uint32_t : 1U;
227 uint32_t CHANMAPX2 : 7U;
228 uint32_t : 1U;
229 uint32_t CHANMAPX1 : 7U;
230 uint32_t : 1U;
231 uint32_t CHANMAPX0 : 7U;
232 uint32_t : 1U;
234 }CHANCTRL6;
236 struct
237 {
238 uint32_t CHANMAPX3 : 7U;
239 uint32_t : 1U;
240 uint32_t CHANMAPX2 : 7U;
241 uint32_t : 1U;
242 uint32_t CHANMAPX1 : 7U;
243 uint32_t : 1U;
244 uint32_t CHANMAPX0 : 7U;
245 uint32_t : 1U;
247 }CHANCTRL7;
249 struct
250 {
251 uint32_t CHANMAPX3 : 7U;
252 uint32_t : 1U;
253 uint32_t CHANMAPX2 : 7U;
254 uint32_t : 1U;
255 uint32_t CHANMAPX1 : 7U;
256 uint32_t : 1U;
257 uint32_t CHANMAPX0 : 7U;
258 uint32_t : 1U;
260 }CHANCTRL8;
262 struct
263 {
264 uint32_t CHANMAPX3 : 7U;
265 uint32_t : 1U;
266 uint32_t CHANMAPX2 : 7U;
267 uint32_t : 1U;
268 uint32_t CHANMAPX1 : 7U;
269 uint32_t : 1U;
270 uint32_t CHANMAPX0 : 7U;
271 uint32_t : 1U;
273 }CHANCTRL9;
275 struct
276 {
277 uint32_t CHANMAPX3 : 7U;
278 uint32_t : 1U;
279 uint32_t CHANMAPX2 : 7U;
280 uint32_t : 1U;
281 uint32_t CHANMAPX1 : 7U;
282 uint32_t : 1U;
283 uint32_t CHANMAPX0 : 7U;
284 uint32_t : 1U;
286 }CHANCTRL10;
288 struct
289 {
290 uint32_t CHANMAPX3 : 7U;
291 uint32_t : 1U;
292 uint32_t CHANMAPX2 : 7U;
293 uint32_t : 1U;
294 uint32_t CHANMAPX1 : 7U;
295 uint32_t : 1U;
296 uint32_t CHANMAPX0 : 7U;
297 uint32_t : 1U;
299 }CHANCTRL11;
301 struct
302 {
303 uint32_t CHANMAPX3 : 7U;
304 uint32_t : 1U;
305 uint32_t CHANMAPX2 : 7U;
306 uint32_t : 1U;
307 uint32_t CHANMAPX1 : 7U;
308 uint32_t : 1U;
309 uint32_t CHANMAPX0 : 7U;
310 uint32_t : 1U;
312 }CHANCTRL12;
314 struct
315 {
316 uint32_t CHANMAPX3 : 7U;
317 uint32_t : 1U;
318 uint32_t CHANMAPX2 : 7U;
319 uint32_t : 1U;
320 uint32_t CHANMAPX1 : 7U;
321 uint32_t : 1U;
322 uint32_t CHANMAPX0 : 7U;
323 uint32_t : 1U;
325 }CHANCTRL13;
327 struct
328 {
329 uint32_t CHANMAPX3 : 7U;
330 uint32_t : 1U;
331 uint32_t CHANMAPX2 : 7U;
332 uint32_t : 1U;
333 uint32_t CHANMAPX1 : 7U;
334 uint32_t : 1U;
335 uint32_t CHANMAPX0 : 7U;
336 uint32_t : 1U;
338 }CHANCTRL14;
340 struct
341 {
342 uint32_t CHANMAPX3 : 7U;
343 uint32_t : 1U;
344 uint32_t CHANMAPX2 : 7U;
345 uint32_t : 1U;
346 uint32_t CHANMAPX1 : 7U;
347 uint32_t : 1U;
348 uint32_t CHANMAPX0 : 7U;
349 uint32_t : 1U;
351 }CHANCTRL15;
353 struct
354 {
355 uint32_t CHANMAPX3 : 7U;
356 uint32_t : 1U;
357 uint32_t CHANMAPX2 : 7U;
358 uint32_t : 1U;
359 uint32_t CHANMAPX1 : 7U;
360 uint32_t : 1U;
361 uint32_t CHANMAPX0 : 7U;
362 uint32_t : 1U;
364 }CHANCTRL16;
366 struct
367 {
368 uint32_t CHANMAPX3 : 7U;
369 uint32_t : 1U;
370 uint32_t CHANMAPX2 : 7U;
371 uint32_t : 1U;
372 uint32_t CHANMAPX1 : 7U;
373 uint32_t : 1U;
374 uint32_t CHANMAPX0 : 7U;
375 uint32_t : 1U;
377 }CHANCTRL17;
379 struct
380 {
381 uint32_t CHANMAPX3 : 7U;
382 uint32_t : 1U;
383 uint32_t CHANMAPX2 : 7U;
384 uint32_t : 1U;
385 uint32_t CHANMAPX1 : 7U;
386 uint32_t : 1U;
387 uint32_t CHANMAPX0 : 7U;
388 uint32_t : 1U;
390 }CHANCTRL18;
392 struct
393 {
394 uint32_t CHANMAPX3 : 7U;
395 uint32_t : 1U;
396 uint32_t CHANMAPX2 : 7U;
397 uint32_t : 1U;
398 uint32_t CHANMAPX1 : 7U;
399 uint32_t : 1U;
400 uint32_t CHANMAPX0 : 7U;
401 uint32_t : 1U;
403 }CHANCTRL19;
405 struct
406 {
407 uint32_t CHANMAPX3 : 7U;
408 uint32_t : 1U;
409 uint32_t CHANMAPX2 : 7U;
410 uint32_t : 1U;
411 uint32_t CHANMAPX1 : 7U;
412 uint32_t : 1U;
413 uint32_t CHANMAPX0 : 7U;
414 uint32_t : 1U;
416 }CHANCTRL20;
418 struct
419 {
420 uint32_t CHANMAPX3 : 7U;
421 uint32_t : 1U;
422 uint32_t CHANMAPX2 : 7U;
423 uint32_t : 1U;
424 uint32_t CHANMAPX1 : 7U;
425 uint32_t : 1U;
426 uint32_t CHANMAPX0 : 7U;
427 uint32_t : 1U;
429 }CHANCTRL21;
431 struct
432 {
433 uint32_t CHANMAPX3 : 7U;
434 uint32_t : 1U;
435 uint32_t CHANMAPX2 : 7U;
436 uint32_t : 1U;
437 uint32_t CHANMAPX1 : 7U;
438 uint32_t : 1U;
439 uint32_t CHANMAPX0 : 7U;
440 uint32_t : 1U;
442 }CHANCTRL22;
444 struct
445 {
446 uint32_t CHANMAPX3 : 7U;
447 uint32_t : 1U;
448 uint32_t CHANMAPX2 : 7U;
449 uint32_t : 1U;
450 uint32_t CHANMAPX1 : 7U;
451 uint32_t : 1U;
452 uint32_t CHANMAPX0 : 7U;
453 uint32_t : 1U;
455 }CHANCTRL23;
457 struct
458 {
459 uint32_t CHANMAPX3 : 7U;
460 uint32_t : 1U;
461 uint32_t CHANMAPX2 : 7U;
462 uint32_t : 1U;
463 uint32_t CHANMAPX1 : 7U;
464 uint32_t : 1U;
465 uint32_t CHANMAPX0 : 7U;
466 uint32_t : 1U;
468 }CHANCTRL24;
470 struct
471 {
472 uint32_t CHANMAPX3 : 7U;
473 uint32_t : 1U;
474 uint32_t CHANMAPX2 : 7U;
475 uint32_t : 1U;
476 uint32_t CHANMAPX1 : 7U;
477 uint32_t : 1U;
478 uint32_t CHANMAPX0 : 7U;
479 uint32_t : 1U;
481 }CHANCTRL25;
483 struct
484 {
485 uint32_t CHANMAPX3 : 7U;
486 uint32_t : 1U;
487 uint32_t CHANMAPX2 : 7U;
488 uint32_t : 1U;
489 uint32_t CHANMAPX1 : 7U;
490 uint32_t : 1U;
491 uint32_t CHANMAPX0 : 7U;
492 uint32_t : 1U;
494 }CHANCTRL26;
496 struct
497 {
498 uint32_t CHANMAPX3 : 7U;
499 uint32_t : 1U;
500 uint32_t CHANMAPX2 : 7U;
501 uint32_t : 1U;
502 uint32_t CHANMAPX1 : 7U;
503 uint32_t : 1U;
504 uint32_t CHANMAPX0 : 7U;
505 uint32_t : 1U;
507 }CHANCTRL27;
509 struct
510 {
511 uint32_t CHANMAPX3 : 7U;
512 uint32_t : 1U;
513 uint32_t CHANMAPX2 : 7U;
514 uint32_t : 1U;
515 uint32_t CHANMAPX1 : 7U;
516 uint32_t : 1U;
517 uint32_t CHANMAPX0 : 7U;
518 uint32_t : 1U;
520 }CHANCTRL28;
522 struct
523 {
524 uint32_t CHANMAPX3 : 7U;
525 uint32_t : 1U;
526 uint32_t CHANMAPX2 : 7U;
527 uint32_t : 1U;
528 uint32_t CHANMAPX1 : 7U;
529 uint32_t : 1U;
530 uint32_t CHANMAPX0 : 7U;
531 uint32_t : 1U;
533 }CHANCTRL29;
535 struct
536 {
537 uint32_t CHANMAPX3 : 7U;
538 uint32_t : 1U;
539 uint32_t CHANMAPX2 : 7U;
540 uint32_t : 1U;
541 uint32_t CHANMAPX1 : 7U;
542 uint32_t : 1U;
543 uint32_t CHANMAPX0 : 7U;
544 uint32_t : 1U;
546 }CHANCTRL30;
548 struct
549 {
550 uint32_t CHANMAPX3 : 7U;
551 uint32_t : 1U;
552 uint32_t CHANMAPX2 : 7U;
553 uint32_t : 1U;
554 uint32_t CHANMAPX1 : 7U;
555 uint32_t : 1U;
556 uint32_t CHANMAPX0 : 7U;
557 uint32_t : 1U;
559 }CHANCTRL31;
562 } VIM_ST;
564 typedef volatile struct
565 {
566 struct
567 {
568 uint32_t PARFLG:1U;
569 uint32_t : 7U;
570 uint32_t SBERR: 1U;
571 uint32_t : 23U;
572 } PARFLG;
574 struct
575 {
576 uint32_t PARENA: 4U;
577 uint32_t : 4U;
578 uint32_t TEST : 4U;
579 uint32_t :4U;
580 uint32_t EDAC: 4U;
581 uint32_t : 4U;
582 uint32_t SBE: 4U;
583 uint32_t :4U;
585 } PARCTL;
587 struct
588 {
589 uint32_t : 2U;
590 uint32_t ADDERR: 8U;
591 uint32_t RAMBASE: 22U;
593 } ADDERR;
595 uint32_t FBPAERR; /* 0xFDF8 */
596 struct
597 {
598 uint32_t : 2U;
599 uint32_t SBERR: 8U;
600 uint32_t RAMBASE: 22U;
602 } SBERR;
603 } VIM_PARITY_ST;
606 typedef volatile struct
607 {
608 uint32_t IRQIVEC;
609 uint32_t FIQIVEC;
610 uint32_t NEST_EN;
611 uint32_t NEST_CTRL;
612 uint32_t FIRQPR0;
613 uint32_t FIRQPR1;
614 uint32_t FIRQPR2;
615 uint32_t FIRQPR3;
616 uint32_t INTREQ0;
617 uint32_t INTREQ1;
618 uint32_t INTREQ2;
619 uint32_t INTREQ3;
620 uint32_t REQMASKSET0;
621 uint32_t REQMASKSET1;
622 uint32_t REQMASKSET2;
623 uint32_t REQMASKSET3;
624 uint32_t REQMASKCLR0;
625 uint32_t REQMASKCLR1;
626 uint32_t REQMASKCLR2;
627 uint32_t REQMASKCLR3;
628 uint32_t WAKEMASKSET0;
629 uint32_t WAKEMASKSET1;
630 uint32_t WAKEMASKSET2;
631 uint32_t WAKEMASKSET3;
632 uint32_t WAKEMASKCLR0;
633 uint32_t WAKEMASKCLR1;
634 uint32_t WAKEMASKCLR2;
635 uint32_t WAKEMASKCLR3;
636 uint32_t IRQVECREG;
637 uint32_t FIQVECREQ;
638 uint32_t CAPEVT;
639 uint32_t CHANCTRL0;
640 uint32_t CHANCTRL1;
641 uint32_t CHANCTRL2;
642 uint32_t CHANCTRL3;
643 uint32_t CHANCTRL4;
644 uint32_t CHANCTRL5;
645 uint32_t CHANCTRL6;
646 uint32_t CHANCTRL7;
647 uint32_t CHANCTRL8;
648 uint32_t CHANCTRL9;
649 uint32_t CHANCTRL10;
650 uint32_t CHANCTRL11;
651 uint32_t CHANCTRL12;
652 uint32_t CHANCTRL13;
653 uint32_t CHANCTRL14;
654 uint32_t CHANCTRL15;
655 uint32_t CHANCTRL16;
656 uint32_t CHANCTRL17;
657 uint32_t CHANCTRL18;
658 uint32_t CHANCTRL19;
659 uint32_t CHANCTRL20;
660 uint32_t CHANCTRL21;
661 uint32_t CHANCTRL22;
662 uint32_t CHANCTRL23;
663 uint32_t CHANCTRL24;
664 uint32_t CHANCTRL25;
665 uint32_t CHANCTRL26;
666 uint32_t CHANCTRL27;
667 uint32_t CHANCTRL28;
668 uint32_t CHANCTRL29;
669 uint32_t CHANCTRL30;
670 uint32_t CHANCTRL31;
671 } VIM_ST_REG;
673 typedef volatile struct
674 {
675 uint32_t PARFLG;
676 uint32_t PARCTL;
677 uint32_t ADDERR;
678 uint32_t FBPAERR;
679 uint32_t SBERR;
680 } VIM_PARITY_ST_REG;
682 typedef volatile struct
683 {
684 FuncPtr VIM_MEM[128];
685 } VIM_MEM_ST;
688 VIM_PARITY_ST *TB_VIM_PARITY = (VIM_PARITY_ST *) VIM_PARITY_U_BASE;
689 VIM_PARITY_ST_REG *TB_VIM_PARITY_REG = (VIM_PARITY_ST_REG *) VIM_PARITY_U_BASE;
691 VIM_ST *TB_VIM = (VIM_ST *) VIM_U_BASE;
692 VIM_ST_REG *TB_VIM_REG = (VIM_ST_REG *) VIM_U_BASE;
693 VIM_MEM_ST *TB_VIM_MEM = (VIM_MEM_ST *) VIM_MEM_U_BASE;
695 #ifdef __cplusplus
696 }
697 #endif
699 #endif /* VIM_H */