1 ;******************************************************************************
2 ;* *
3 ;* Copyright (c) 2018-2019 Texas Instruments Incorporated *
4 ;* http://www.ti.com/ *
5 ;* *
6 ;* Redistribution and use in source and binary forms, with or without *
7 ;* modification, are permitted provided that the following conditions *
8 ;* are met: *
9 ;* *
10 ;* Redistributions of source code must retain the above copyright *
11 ;* notice, this list of conditions and the following disclaimer. *
12 ;* *
13 ;* Redistributions in binary form must reproduce the above copyright *
14 ;* notice, this list of conditions and the following disclaimer in *
15 ;* the documentation and/or other materials provided with the *
16 ;* distribution. *
17 ;* *
18 ;* Neither the name of Texas Instruments Incorporated nor the names *
19 ;* of its contributors may be used to endorse or promote products *
20 ;* derived from this software without specific prior written *
21 ;* permission. *
22 ;* *
23 ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS *
24 ;* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT *
25 ;* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR *
26 ;* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT *
27 ;* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
28 ;* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT *
29 ;* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, *
30 ;* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY *
31 ;* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
32 ;* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE *
33 ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
34 ;* *
35 ;******************************************************************************
36 ;****************************************************************************
37 ; Setup Reset Vectors
38 ;****************************************************************************
39 .arm
41 .sect ".rstvectors"
42 .global _sblResetVectors
44 _sblResetVectors:
45 .asmfunc
46 LDR pc, sblEntry ; Reset
47 B _sblLoopForever ; Undefined Instruction
48 B _sblLoopForever ; SVC call
49 B _sblLoopForever ; Prefetch abort
50 B _sblLoopForever ; Data abort
51 B _sblLoopForever ; Hypervisor
52 B _sblLoopForever ; IRQ
53 B _sblLoopForever ; FIQ
55 sblEntry .long _sblEntry
56 .endasmfunc
58 ;****************************************************************************
59 ; SBL Entry
60 ;****************************************************************************
61 .def _sblEntry
62 .ref _c_int00
63 .ref SBL_init_profile
64 .ref _sblTcmEn
66 _c_int00_addr .long _c_int00
67 SBL_init_profile_addr .long SBL_init_profile
68 _sblTcmEnAddr .long _sblTcmEn
70 _sblEntry:
71 .asmfunc
73 MRC p15, #0, r1, c0, c0, #5
74 BFC r1, #8, #24
75 CMP r1, #0
76 BNE _sblLoopForever
78 ADR r1, _sblTestStackBase
79 BIC r1, r1, #0xf
80 MOV sp, r1
82 LDR r1, SBL_init_profile_addr
83 BLX r1
85 LDR r1, _sblTcmEnAddr
86 BLX r1
88 LDR r1, _c_int00_addr
89 BLX r1
91 _sblLoopForever:
92 WFI
93 B _sblLoopForever
95 .endasmfunc
97 _sblTestStackTop:
98 .space 64
99 _sblTestStackBase: