1 /*
2 * Copyright (C) 2018-2020 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
33 #include <ti/csl/tistdtypes.h>
34 #include <ti/csl/soc.h>
35 #include <ti/csl/arch/csl_arch.h>
36 #include <ti/csl/hw_types.h>
37 #include <ti/drv/uart/UART_stdio.h>
38 #include <ti/drv/uart/soc/UART_soc.h>
39 #include <ti/board/board.h>
40 #include <sbl_soc.h>
41 #include <sbl_soc_cfg.h>
42 #include <sbl_err_trap.h>
43 #include <sbl_sci_client.h>
45 #if defined(SBL_ENABLE_HLOS_BOOT) && defined(SOC_AM65XX)
46 const uint32_t gSciclient_boardCfgLow_hlos_rm[(SCICLIENT_BOARDCFG_RM_LINUX_SIZE_IN_BYTES+3U)/4U]
47 __attribute__(( aligned(128), section(".boardcfg_data") ))
48 = SCICLIENT_BOARDCFG_RM_LINUX;
49 #endif
51 #ifdef __cplusplus
52 #pragma DATA_SECTION(".firmware")
53 #else
54 #pragma WEAK (SBL_ReadSysfwImage)
55 #pragma DATA_SECTION(gSciclient_firmware, ".firmware")
56 #endif
57 uint32_t gSciclient_firmware[1];
59 #if SCICLIENT_FIRMWARE_SIZE_IN_BYTES > SBL_SYSFW_MAX_SIZE
60 #error "SYSFW too large...update SBL_SYSFW_MAX_SIZE"
61 #endif
63 #if (!defined(SBL_SKIP_BRD_CFG_PM)) || (!defined(SBL_SKIP_BRD_CFG_RM))
64 static int32_t Sciclient_setBoardConfigHeader ();
65 #endif
66 #if defined(SOC_AM65XX) || defined(SOC_J721E) || defined(SOC_J7200)
67 /* Firewall ID for MCU_FSS0_S0 */
68 #define MCU_FSS0_S0_FWID (1036)
69 #define MCU_FSS0_S0_FW_REGIONS (8)
71 #if defined (SOC_J721E) || defined (SOC_J7200)
72 /** \brief Aligned address at which the X509 header is placed. */
73 #define SCISERVER_COMMON_X509_HEADER_ADDR (0x41cffb00U)
75 /** \brief Aligned address at which the Board Config header is placed. */
76 #define SCISERVER_BOARDCONFIG_HEADER_ADDR (0x41c80000U)
78 /** \brief Aligned address at which the Board Config is placed. */
79 #define SCISERVER_BOARDCONFIG_DATA_ADDR (0x41c80040U)
81 #endif
82 #endif
84 uint32_t SBL_IsAuthReq(void)
85 {
86 uint32_t retVal = SBL_ALWAYS_AUTH_APP;
87 uint32_t dev_type;
88 uint32_t dev_subtype;
90 SBL_ADD_PROFILE_POINT;
92 dev_type = CSL_REG32_RD(SBL_SYS_STATUS_REG) & SBL_SYS_STATUS_DEV_TYPE_MASK;
93 dev_subtype = CSL_REG32_RD(SBL_SYS_STATUS_REG) & SBL_SYS_STATUS_DEV_SUBTYPE_MASK;
95 /* No auth possible, if valid SMPK/BMPK is not present */
96 if ((dev_subtype == SBL_SYS_STATUS_DEV_SUBTYPE_FS) ||
97 (dev_type == SBL_SYS_STATUS_DEV_TYPE_GP) ||
98 (dev_type == SBL_SYS_STATUS_DEV_TYPE_TEST))
99 {
100 retVal = SBL_NEVER_AUTH_APP;
101 }
103 SBL_ADD_PROFILE_POINT;
105 return retVal;
106 }
108 #ifndef SBL_SKIP_SYSFW_INIT
109 Sciclient_BoardCfgPrms_t sblBoardCfgPrms = {0};
110 Sciclient_BoardCfgPrms_t sblBoardCfgPmPrms = {0};
111 Sciclient_BoardCfgPrms_t sblBoardCfgRmPrms = {0};
112 #ifndef SBL_SKIP_BRD_CFG_SEC
113 Sciclient_BoardCfgPrms_t sblBoardCfgSecPrms = {0};
114 #endif
115 #endif
117 void SBL_SciClientInit(void)
118 {
119 int32_t status = CSL_EFAIL;
120 void *sysfw_ptr = gSciclient_firmware;
122 #ifndef SBL_SKIP_SYSFW_INIT
123 /* SYSFW board configurations */
124 Sciclient_DefaultBoardCfgInfo_t boardCfgInfo;
125 Sciclient_ConfigPrms_t config =
126 {
127 SCICLIENT_SERVICE_OPERATION_MODE_POLLED,
128 NULL,
129 1,
130 0,
131 TRUE
132 };
133 #endif
135 SBL_ADD_PROFILE_POINT;
137 status = SBL_ReadSysfwImage(&sysfw_ptr, SBL_SYSFW_MAX_SIZE);
138 if (status != CSL_PASS)
139 {
140 #if defined(SOC_J721E) || defined(SOC_J7200)
141 SBL_log(SBL_LOG_ERR,"TIFS read...FAILED \n");
142 #else
143 SBL_log(SBL_LOG_ERR,"SYSFW read...FAILED \n");
144 #endif
145 SblErrLoop(__FILE__, __LINE__);
146 }
148 #ifndef SBL_SKIP_SYSFW_INIT
149 SBL_ADD_PROFILE_POINT;
151 status = Sciclient_getDefaultBoardCfgInfo(&boardCfgInfo);
153 #if defined(SBL_ENABLE_HLOS_BOOT) && defined(SOC_AM65XX)
154 /* Replace default Sciclient boardCfgLowRm with alternate version for HLOS boot */
155 boardCfgInfo.boardCfgLowRm = &gSciclient_boardCfgLow_hlos_rm[0U];
156 boardCfgInfo.boardCfgLowRmSize = SCICLIENT_BOARDCFG_RM_LINUX_SIZE_IN_BYTES;
157 #endif
159 if (status != CSL_PASS)
160 {
161 SBL_log(SBL_LOG_ERR,"Sciclient get default board config...FAILED \n");
162 SblErrLoop(__FILE__, __LINE__);
163 }
165 status = Sciclient_loadFirmware((const uint32_t *) sysfw_ptr);
166 if (status != CSL_PASS)
167 {
168 #if defined(SOC_J721E) || defined(SOC_J7200)
169 SBL_log(SBL_LOG_ERR,"TIFS load...FAILED \n");
170 #else
171 SBL_log(SBL_LOG_ERR,"SYSFW load...FAILED \n");
172 #endif
173 SblErrLoop(__FILE__, __LINE__);
174 }
176 SBL_ADD_PROFILE_POINT;
177 status = Sciclient_init(&config);
178 if (status != CSL_PASS)
179 {
180 SBL_log(SBL_LOG_ERR,"Sciclient init ...FAILED \n");
181 SblErrLoop(__FILE__, __LINE__);
182 }
184 #ifndef SBL_SKIP_BRD_CFG_BOARD
185 SBL_ADD_PROFILE_POINT;
186 sblBoardCfgPrms.boardConfigLow = (uint32_t)boardCfgInfo.boardCfgLow;
187 sblBoardCfgPrms.boardConfigHigh = 0;
188 sblBoardCfgPrms.boardConfigSize = boardCfgInfo.boardCfgLowSize;
189 sblBoardCfgPrms.devGrp = SBL_DEVGRP;
190 status = Sciclient_boardCfg(&sblBoardCfgPrms);
191 if (status != CSL_PASS)
192 {
193 SBL_log(SBL_LOG_ERR,"Sciclient board config ...FAILED \n");
194 SblErrLoop(__FILE__, __LINE__);
195 }
196 #endif
198 #ifndef SBL_SKIP_BRD_CFG_PM
199 if (SBL_LOG_LEVEL > SBL_LOG_NONE)
200 {
201 SBL_ADD_PROFILE_POINT;
202 UART_stdioDeInit();
203 }
204 SBL_ADD_PROFILE_POINT;
205 sblBoardCfgPmPrms.boardConfigLow = (uint32_t)boardCfgInfo.boardCfgLowPm;
206 sblBoardCfgPmPrms.boardConfigHigh = 0;
207 sblBoardCfgPmPrms.boardConfigSize = boardCfgInfo.boardCfgLowPmSize;
208 sblBoardCfgPmPrms.devGrp = SBL_DEVGRP;
209 status = Sciclient_boardCfgPm(&sblBoardCfgPmPrms);
210 if (status != CSL_PASS)
211 {
212 SBL_log(SBL_LOG_ERR,"Sciclient board config pm...FAILED \n")
213 SblErrLoop(__FILE__, __LINE__);
214 }
216 if (SBL_LOG_LEVEL > SBL_LOG_NONE)
217 {
218 /* Re-init UART for logging */
219 UART_HwAttrs uart_cfg;
221 SBL_ADD_PROFILE_POINT;
222 UART_socGetInitCfg(BOARD_UART_INSTANCE, &uart_cfg);
223 uart_cfg.frequency = SBL_SYSFW_UART_MODULE_INPUT_CLK;
224 UART_socSetInitCfg(BOARD_UART_INSTANCE, &uart_cfg);
225 UART_stdioInit(BOARD_UART_INSTANCE);
226 }
227 #endif
229 #ifndef SBL_SKIP_BRD_CFG_RM
230 SBL_ADD_PROFILE_POINT;
231 sblBoardCfgRmPrms.boardConfigLow = (uint32_t)boardCfgInfo.boardCfgLowRm;
232 sblBoardCfgRmPrms.boardConfigHigh = 0;
233 sblBoardCfgRmPrms.boardConfigSize = boardCfgInfo.boardCfgLowRmSize;
234 sblBoardCfgRmPrms.devGrp = SBL_DEVGRP;
235 status = Sciclient_boardCfgRm(&sblBoardCfgRmPrms);
236 if (status != CSL_PASS)
237 {
238 SBL_log(SBL_LOG_ERR,"Sciclient board config rm...FAILED \n");
239 SblErrLoop(__FILE__, __LINE__);
240 }
241 #endif
243 #ifndef SBL_SKIP_BRD_CFG_SEC
244 SBL_ADD_PROFILE_POINT;
245 sblBoardCfgSecPrms.boardConfigLow = (uint32_t)boardCfgInfo.boardCfgLowSec;
246 sblBoardCfgSecPrms.boardConfigHigh = 0;
247 sblBoardCfgSecPrms.boardConfigSize = boardCfgInfo.boardCfgLowSecSize;
248 sblBoardCfgSecPrms.devGrp = SBL_DEVGRP;
249 status = Sciclient_boardCfgSec(&sblBoardCfgSecPrms);
250 if (status != CSL_PASS)
251 {
252 SBL_log(SBL_LOG_ERR,"Sciclient board config sec...FAILED \n");
253 SblErrLoop(__FILE__, __LINE__);
254 }
255 #if defined(SOC_AM65XX) || defined(SOC_J721E) || defined(SOC_J7200)
256 /* Secure ROM has left firewall regions for FSS DAT0 set. Disable them for DMA usage. */
257 uint16_t i;
258 struct tisci_msg_fwl_set_firewall_region_resp respFwCtrl = {0};
259 struct tisci_msg_fwl_set_firewall_region_req reqFwCtrl =
260 {
261 .fwl_id = (uint16_t) MCU_FSS0_S0_FWID,
262 .region = (uint16_t) 0,
263 .n_permission_regs = (uint32_t) 3,
264 /* Set .control to zero to disable the firewall region */
265 .control = (uint32_t) 0,
266 .permissions[0] = (uint32_t) 0,
267 .permissions[1] = (uint32_t) 0,
268 .permissions[2] = (uint32_t) 0,
269 .start_address = 0,
270 .end_address = 0
271 };
273 for (i = 0; i < MCU_FSS0_S0_FW_REGIONS; i++)
274 {
275 reqFwCtrl.region = i;
276 status = Sciclient_firewallSetRegion(&reqFwCtrl, &respFwCtrl, SCICLIENT_SERVICE_WAIT_FOREVER);
277 if (status != CSL_PASS)
278 {
279 SBL_log(SBL_LOG_ERR,"MCU FSS0_S0 firewall region # %d disable...FAILED \n", i);
280 }
281 }
282 #endif
283 #endif
285 /* Get SYSFW/TIFS version */
286 SBL_ADD_PROFILE_POINT;
288 if (SBL_LOG_LEVEL > SBL_LOG_ERR)
289 {
290 struct tisci_msg_version_req req = {0};
291 const Sciclient_ReqPrm_t reqPrm =
292 {
293 TISCI_MSG_VERSION,
294 TISCI_MSG_FLAG_AOP,
295 (const uint8_t *)&req,
296 sizeof(req),
297 SCICLIENT_SERVICE_WAIT_FOREVER
298 };
300 struct tisci_msg_version_resp response;
301 Sciclient_RespPrm_t respPrm =
302 {
303 0,
304 (uint8_t *) &response,
305 (uint32_t)sizeof (response)
306 };
308 status = Sciclient_service(&reqPrm, &respPrm);
309 if (CSL_PASS == status)
310 {
311 if (respPrm.flags == (uint32_t)TISCI_MSG_FLAG_ACK)
312 {
313 SBL_ADD_PROFILE_POINT;
314 #if defined(SOC_J721E) || defined(SOC_J7200)
315 SBL_log(SBL_LOG_MIN,"TIFS ver: %s\n", (char *) response.str);
316 #else
317 SBL_log(SBL_LOG_MIN,"SYSFW ver: %s\n", (char *) response.str);
318 #endif
319 }
320 else
321 {
322 #if defined(SOC_J721E) || defined(SOC_J7200)
323 SBL_log(SBL_LOG_ERR,"TIFS Get Version failed \n");
324 #else
325 SBL_log(SBL_LOG_ERR,"SYSFW Get Version failed \n");
326 #endif
327 SblErrLoop(__FILE__, __LINE__);
328 }
329 }
330 }
333 #if (!defined(SBL_SKIP_BRD_CFG_PM)) || (!defined(SBL_SKIP_BRD_CFG_RM))
334 status = Sciclient_setBoardConfigHeader();
335 if (CSL_PASS == status)
336 {
337 SBL_log(SBL_LOG_MAX,"Sciclient_setBoardConfigHeader... PASSED\n");
338 }
339 else
340 {
341 SBL_log(SBL_LOG_ERR,"Sciclient_setBoardConfigHeader... FAILED\n");
342 SblErrLoop(__FILE__, __LINE__);
343 }
344 #endif
347 #if !defined(SBL_SKIP_MCU_RESET)
348 /* RTI seems to be turned on by ROM. Turning it off so that Power domain can transition */
349 Sciclient_pmSetModuleState(SBL_DEV_ID_RTI0, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
350 Sciclient_pmSetModuleState(SBL_DEV_ID_RTI1, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
351 #if defined(SOC_AM64X)
352 Sciclient_pmSetModuleState(SBL_DEV_ID_RTI8, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
353 Sciclient_pmSetModuleState(SBL_DEV_ID_RTI9, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
354 Sciclient_pmSetModuleState(SBL_DEV_ID_RTI10, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
355 Sciclient_pmSetModuleState(SBL_DEV_ID_RTI11, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
356 Sciclient_pmSetModuleState(SBL_DEV_ID_MCU_RTI0, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
357 #endif
358 #endif
361 #endif
363 SBL_ADD_PROFILE_POINT;
364 }
366 #if (!defined(SBL_SKIP_BRD_CFG_PM)) || (!defined(SBL_SKIP_BRD_CFG_RM))
367 static int32_t Sciclient_setBoardConfigHeader ()
368 {
369 int32_t status = CSL_PASS;
370 #if defined (SOC_J7200) || defined (SOC_J721E)
371 //uint32_t alignedOffset = ((SCICLIENT_BOARDCFG_PM_SIZE_IN_BYTES + 128U)/128U)*128U;
372 uint32_t alignedOffset = SCICLIENT_BOARDCFG_PM_SIZE_IN_BYTES;
373 Sciclient_BoardCfgPrms_t boardCfgPrms_pm =
374 {
375 .boardConfigLow = (uint32_t)SCISERVER_BOARDCONFIG_DATA_ADDR,
376 .boardConfigHigh = 0,
377 .boardConfigSize = SCICLIENT_BOARDCFG_PM_SIZE_IN_BYTES,
378 .devGrp = DEVGRP_ALL
379 };
380 Sciclient_BoardCfgPrms_t boardCfgPrms_rm =
381 {
382 .boardConfigLow =
383 (uint32_t) SCISERVER_BOARDCONFIG_DATA_ADDR + alignedOffset,
384 .boardConfigHigh = 0,
385 .boardConfigSize = SCICLIENT_BOARDCFG_RM_SIZE_IN_BYTES,
386 .devGrp = DEVGRP_ALL
387 };
388 status = Sciclient_boardCfgPrepHeader (
389 (uint8_t *) SCISERVER_COMMON_X509_HEADER_ADDR,
390 (uint8_t *) SCISERVER_BOARDCONFIG_HEADER_ADDR,
391 &boardCfgPrms_pm, &boardCfgPrms_rm);
392 if (CSL_PASS == status)
393 {
394 SBL_log(SBL_LOG_MAX,"SCISERVER Board Configuration header population... ");
395 SBL_log(SBL_LOG_MAX,"PASSED\n");
396 }
397 else
398 {
399 SBL_log(SBL_LOG_MIN,"SCISERVER Board Configuration header population... ");
400 SBL_log(SBL_LOG_MIN,"FAILED\n");
401 }
402 memcpy((void *)boardCfgPrms_pm.boardConfigLow, (void *) sblBoardCfgPmPrms.boardConfigLow, SCICLIENT_BOARDCFG_PM_SIZE_IN_BYTES);
403 memcpy((void *)boardCfgPrms_rm.boardConfigLow, (void *) sblBoardCfgRmPrms.boardConfigLow, SCICLIENT_BOARDCFG_RM_SIZE_IN_BYTES);
404 #endif
405 return status;
406 }
407 #endif